TWM545363U - Chip package structure - Google Patents
Chip package structure Download PDFInfo
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- TWM545363U TWM545363U TW105218008U TW105218008U TWM545363U TW M545363 U TWM545363 U TW M545363U TW 105218008 U TW105218008 U TW 105218008U TW 105218008 U TW105218008 U TW 105218008U TW M545363 U TWM545363 U TW M545363U
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- heat dissipation
- dissipation substrate
- package structure
- plate body
- chip package
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Description
本新型是有關於一種晶片封裝結構，特別是指一種具有良好散熱功能的晶片封裝結構。 The present invention relates to a chip package structure, and more particularly to a chip package structure having a good heat dissipation function.
半導體封裝是一種用於容納、包覆一個或多個半導體晶片的結構，其作用在防止晶片因受到外力或是濕氣引響而造成損壞，也可以用以作為晶片散熱的媒介。 The semiconductor package is a structure for accommodating and covering one or more semiconductor wafers, which functions to prevent the wafer from being damaged by external force or moisture, and can also be used as a medium for heat dissipation of the wafer.
目前有一種四方形平面無引腳封裝結構(Quad Flat NO-Lead package，簡稱為QFN package)，因為該封裝結構沒有設置外側引腳(lead)，所以在包裝、運送以及生產上都不會有引腳損傷(lead damage)的問題，大幅地提高了封裝結構的穩定性。由於該封裝結構散熱效能、電性功能以及品質穩定性都很高，再加上輕、薄、短、小之特性，現在已成為導線架封裝結構(Lead Frame Base Package)的主流。 There is currently a Quad Flat NO-Lead package (QFN package), because there is no external lead in the package structure, so there will be no packaging, shipping and production. The problem of lead damage greatly improves the stability of the package structure. Due to the high heat dissipation performance, electrical function and quality stability of the package structure, coupled with the characteristics of light, thin, short and small, it has become the mainstream of the Lead Frame Base Package.
一般四方形平面無引腳封裝結構用以裝設半導體晶片的散熱基板是外露於封裝結構的下表面，在使用上可以直接焊接至印刷電路板(PCB)上，並且藉由該散熱基板將晶片運作時所產生的熱導至印刷電路板而散出。然而，印刷電路板的導熱能力有限，難以做為封裝結構良好的散熱媒介。 Generally, the quadrangular planar leadless package structure is used to mount the semiconductor wafer. The heat dissipation substrate is exposed on the lower surface of the package structure, and can be directly soldered to the printed circuit board (PCB) in use, and the wafer is transferred by the heat dissipation substrate. The heat generated during operation is transmitted to the printed circuit board. However, printed circuit boards have limited thermal conductivity and are difficult to use as a heat sink for a good package structure.
因此，本新型之其中一目的，即在提供一種散熱基板是外露於封裝結構之上表面的晶片封裝結構。 Therefore, one of the objects of the present invention is to provide a heat dissipation substrate which is a chip package structure exposed on the upper surface of the package structure.
於是，本新型晶片封裝結構在一些實施態樣中，適用於裝設在一電路板上，該晶片封裝結構包含一散熱基板、一設置於該散熱基板的晶片、一設置在該散熱基板及該電路板之間的導線架，以及一包覆該晶片的絕緣封裝層。該散熱基板包括一朝向該電路板的第一面及一相反於該第一面的第二面，該晶片是設置於該散熱基板的第一面。該導線架設置於該散熱基板及該電路板之間，該導線架包括多個電連接該晶片的引腳，該等引腳電連接該電路板以使該晶片藉由該等引腳電連接該電路板。該絕緣封裝層包覆該晶片，及該散熱基板與該導線架之一部分而使該散熱基板的第二面之部分與導線架之該等引腳之部分裸露出該絕緣封裝層。 Therefore, the chip package structure of the present invention is suitable for being mounted on a circuit board. The chip package structure includes a heat dissipation substrate, a wafer disposed on the heat dissipation substrate, a heat dissipation substrate disposed thereon, and a lead frame between the boards, and an insulating encapsulation layer covering the wafer. The heat dissipation substrate includes a first surface facing the circuit board and a second surface opposite to the first surface, and the wafer is disposed on the first surface of the heat dissipation substrate. The lead frame is disposed between the heat dissipation substrate and the circuit board, and the lead frame includes a plurality of pins electrically connected to the chip, the pins electrically connecting the circuit board to electrically connect the chip by the pins The board. The insulating encapsulation layer covers the wafer, and the heat dissipating substrate and a portion of the lead frame expose a portion of the second surface of the heat dissipating substrate and a portion of the leads of the lead frame to expose the insulating encapsulation layer.
在一些實施態樣中，該散熱基板的材質為金屬。 In some embodiments, the heat dissipation substrate is made of metal.
在一些實施態樣中，該散熱基板包括一陶瓷板體及一結合於該陶瓷板體的第一金屬層，該陶瓷板體具有一連接該晶片的第一表面及一相反於該第一表面的第二表面，該第一金屬層結合於該陶瓷板體的第二表面以與該第二表面共同形成該散熱基板之第二面。 In some embodiments, the heat dissipation substrate comprises a ceramic plate body and a first metal layer coupled to the ceramic plate body, the ceramic plate body having a first surface connecting the wafer and a surface opposite to the first surface The second surface is bonded to the second surface of the ceramic plate body to form a second surface of the heat dissipation substrate together with the second surface.
在一些實施態樣中，該散熱基板之陶瓷板體還具有多個形成於該第一表面且與該晶片電性連接的導電結構，該導線架之該等引腳分別電連接該等導電結構以使該晶片藉由該等導電結構電連接該等引腳。 In some embodiments, the ceramic plate body of the heat dissipation substrate further has a plurality of conductive structures formed on the first surface and electrically connected to the chip, and the pins of the lead frame are electrically connected to the conductive structures respectively. The wafer is electrically connected to the pins by the conductive structures.
在一些實施態樣中，該散熱基板還包括多個結合至該陶瓷板體之第二表面的第二金屬層，及多個嵌設於該陶瓷板體內且兩端貫穿該陶瓷板體之第一表面與第二表面的導接線路，該等導接線路的一端連接於該等第二金屬層且另一端連接於部分之該等導電結構。 In some embodiments, the heat dissipation substrate further includes a plurality of second metal layers bonded to the second surface of the ceramic plate body, and a plurality of the plurality of metal layers embedded in the ceramic plate body and extending through the ceramic plate body a conductive line of a surface and a second surface, wherein one end of the conductive line is connected to the second metal layer and the other end is connected to a portion of the conductive structures.
在一些實施態樣中，該散熱基板的第一金屬層的材質為銅，且該第一金屬層是以共晶鍵合、電鍍方式或是厚膜印刷技術結合於該陶瓷板體之該第二表面。 In some embodiments, the first metal layer of the heat dissipation substrate is made of copper, and the first metal layer is bonded to the ceramic plate by eutectic bonding, electroplating or thick film printing. Two surfaces.
在一些實施態樣中，該散熱基板之陶瓷板體的材質為氮化鋁或是氧化鋁。 In some embodiments, the ceramic plate body of the heat dissipation substrate is made of aluminum nitride or aluminum oxide.
在一些實施態樣中，該散熱基板還包括一設置於該第一金屬層上以供一散熱片貼附的導熱金屬層。 In some embodiments, the heat dissipation substrate further includes a heat conductive metal layer disposed on the first metal layer for attaching a heat sink.
本新型至少具有以下功效：用以裝設晶片的散熱基板是外露於封裝結構的上表面，晶片運作時所產生的熱會導至上表面散出。相較於習知的封裝結構將晶片運作時所產生的熱導至印刷電路板的方式更能有效散除晶片產生的廢熱。 The present invention has at least the following effects: the heat dissipating substrate for mounting the wafer is exposed on the upper surface of the package structure, and heat generated during operation of the wafer is conducted to the upper surface. Compared with the conventional package structure, the heat generated by the operation of the wafer is guided to the printed circuit board more effectively to dissipate the waste heat generated by the wafer.
1‧‧‧散熱基板 1‧‧‧heated substrate
11‧‧‧第一面 11‧‧‧ first side
12‧‧‧第二面 12‧‧‧ second side
13‧‧‧陶瓷板體 13‧‧‧Ceramic plate
131‧‧‧第一表面 131‧‧‧ first surface
132‧‧‧第二表面 132‧‧‧ second surface
133‧‧‧導電結構 133‧‧‧Electrical structure
14‧‧‧第一金屬層 14‧‧‧First metal layer
15‧‧‧第二金屬層 15‧‧‧Second metal layer
16‧‧‧導接線路 16‧‧‧Connected lines
17‧‧‧導熱金屬層 17‧‧‧thermal metal layer
2‧‧‧晶片 2‧‧‧ wafer
3‧‧‧導線架 3‧‧‧ lead frame
31‧‧‧引腳 31‧‧‧ pin
311‧‧‧黏貼面 311‧‧‧Adhesive surface
312‧‧‧連接面 312‧‧‧ Connection surface
4‧‧‧絕緣封裝層 4‧‧‧Insulating encapsulation layer
41‧‧‧上表面 41‧‧‧ upper surface
42‧‧‧下表面 42‧‧‧ lower surface
7‧‧‧電路板 7‧‧‧ boards
8‧‧‧膠帶 8‧‧‧ Tape
9‧‧‧散熱片 9‧‧‧ Heat sink
S1‧‧‧步驟 S1‧‧‧ steps
S2‧‧‧步驟 S2‧‧‧ steps
S3‧‧‧步驟 S3‧‧‧ steps
S4‧‧‧步驟 S4‧‧‧ steps
S5‧‧‧步驟 S5‧‧ steps
S6‧‧‧步驟 S6‧‧ steps
本新型之其他的特徵及功效，將於參照圖式的實施方式中清楚地呈現，其中：圖1是本新型晶片封裝結構的一實施例之製造方法的一步驟流程方塊圖； 圖2至7是該實施例之製造方法的流程示意圖；及圖8是一示意圖，說明該實施例之製造方法的一步驟S5完成時的態樣。 Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: FIG. 1 is a block flow diagram of a method of manufacturing an embodiment of the novel chip package structure; 2 to 7 are schematic views showing the flow of the manufacturing method of the embodiment; and Fig. 8 is a schematic view showing the state at the completion of a step S5 of the manufacturing method of the embodiment.
參閱圖1，是本新型晶片封裝結構之一實施例的製造方法，適用於製作一裝設在一電路板7(見圖7)上的晶片封裝結構。以下配合圖2至圖8具體說明本實施例之實施步驟。 Referring to FIG. 1, a manufacturing method of an embodiment of the novel chip package structure is suitable for fabricating a chip package structure mounted on a circuit board 7 (see FIG. 7). The implementation steps of this embodiment will be specifically described below with reference to FIGS. 2 to 8.
參閱圖2、3，步驟S1以及步驟S2：在執行步驟S3之組裝前，要先執行步驟S1、S2以製備、提供一散熱基板1以及一導線架3，並將一晶片2設置在該散熱基板1，該步驟S1與步驟S2沒有特定之執行先後順序關係。該散熱基板1包括相反的一第一面11以及一第二面12、一陶瓷板體13以及一結合於該陶瓷板體13的第一金屬層14。該散熱基板1的陶瓷板體13之材質可以是氮化鋁或是氧化鋁且該散熱基板1具有一連接該晶片2的第一表面131，以及一相反於該第一表面131的第二表面132。該晶片2藉由銀膠黏貼在該陶瓷板體13的第一表面131。該第一金屬層14是以共晶鍵合方式將一金屬箔片結合於該陶瓷板體13之第二表面132，或是透過電鍍方式形成於該陶瓷板體13之第二表面132，以與該陶瓷板體13之第二表面132共同形成該散熱基板1的第二面12。該陶瓷板體13還具有多個形成於該第一表面131且藉由打線接合之方式與該晶片2電性連接的導電結構133。 Referring to FIGS. 2 and 3, step S1 and step S2: before performing the assembly of step S3, steps S1 and S2 are performed to prepare, provide a heat dissipation substrate 1 and a lead frame 3, and a wafer 2 is disposed in the heat dissipation. The substrate 1 has no specific execution order relationship between the steps S1 and S2. The heat dissipation substrate 1 includes an opposite first surface 11 and a second surface 12, a ceramic plate body 13, and a first metal layer 14 bonded to the ceramic plate body 13. The material of the ceramic plate body 13 of the heat dissipation substrate 1 may be aluminum nitride or aluminum oxide, and the heat dissipation substrate 1 has a first surface 131 connecting the wafer 2 and a second surface opposite to the first surface 131. 132. The wafer 2 is adhered to the first surface 131 of the ceramic plate body 13 by silver glue. The first metal layer 14 is bonded to the second surface 132 of the ceramic plate body 13 by eutectic bonding, or is formed on the second surface 132 of the ceramic plate body 13 by electroplating. The second surface 12 of the heat dissipation substrate 1 is formed together with the second surface 132 of the ceramic plate body 13. The ceramic plate body 13 further has a plurality of conductive structures 133 formed on the first surface 131 and electrically connected to the wafer 2 by wire bonding.
在本實施例的製造方法中，該散熱基板1還包括多個結合至該陶 瓷板體13之第二表面132的第二金屬層15，以及多個嵌設於該陶瓷板體13內且兩端分別貫穿該陶瓷板體13之第一表面131與第二表面132的導接線路16。該等導接線路16的一端連接於該等第二金屬層15且另一端連接於部分之該等導電結構133，以使該晶片2藉由連接該等導接線路16的導電結構133與該第二金屬層15電性連接。該導線架3包括多個引腳31並且暫時地固定在一膠帶8上，每一引腳31包括一供該膠帶8黏貼之黏貼面311以及一相反於該黏貼面311的連接面312。 In the manufacturing method of the embodiment, the heat dissipation substrate 1 further includes a plurality of bonded to the ceramic a second metal layer 15 of the second surface 132 of the porcelain plate body 13 and a plurality of guides embedded in the ceramic plate body 13 and extending through the first surface 131 and the second surface 132 of the ceramic plate body 13 respectively Connect line 16. One end of the conductive line 16 is connected to the second metal layer 15 and the other end is connected to a portion of the conductive structures 133 such that the wafer 2 is connected to the conductive structure 133 of the conductive lines 16 The second metal layer 15 is electrically connected. The lead frame 3 includes a plurality of pins 31 and is temporarily fixed to an adhesive tape 8. Each of the leads 31 includes an adhesive surface 311 to which the adhesive tape 8 is adhered and a connection surface 312 opposite to the adhesive surface 311.
參閱圖4，步驟S3：本步驟要進行該散熱基板1與該導線架3之組裝，具體是令該散熱基板1之第一面11朝向下，且於組裝前將該導線架3安置於該散熱基板1的下方，再使該晶片2以及導線架3之該等引腳31連接以形成電性連接。在本實施例的製造方法中該散熱基板1與該導線架3的連接方式是在該陶瓷板體13的導電結構133上點銀膠以及在該等引腳31之連接面312上打上金屬線，再將導電結構133上之銀膠與金屬線接合，以使該散熱基板1連接該導線架3且使該等引腳31與該晶片2電性連接。在組裝完成後，該散熱基板1之第一面11是朝向下而且面對該等導線架3之每一引腳31的連接面312。 Referring to FIG. 4, step S3: this step is to assemble the heat dissipating substrate 1 and the lead frame 3, specifically, the first surface 11 of the heat dissipating substrate 1 is directed downward, and the lead frame 3 is placed on the lead frame 3 before assembly. Below the heat-dissipating substrate 1, the wafers 2 and the leads 31 of the lead frame 3 are connected to form an electrical connection. In the manufacturing method of the embodiment, the heat dissipation substrate 1 and the lead frame 3 are connected by a silver paste on the conductive structure 133 of the ceramic plate body 13 and a metal wire on the connection surface 312 of the pins 31. Then, the silver paste on the conductive structure 133 is bonded to the metal wire, so that the heat dissipation substrate 1 is connected to the lead frame 3 and the pins 31 are electrically connected to the wafer 2. After the assembly is completed, the first face 11 of the heat dissipation substrate 1 is a connection face 312 that faces downward and faces each of the leads 31 of the lead frames 3.
參閱圖5，步驟S4：完成該散熱基板1與該導線架3之組裝後，本步驟會形成一包覆該晶片2、該散熱基板1與該導線架3的絕緣封裝層4。待步驟S1、S3中所塗佈的銀膠固化、乾燥後，以流體狀或粉末狀的絕緣材料包覆該晶片2、該散熱基板1與該導線架3，待絕緣材料固結後即形成覆蓋並密封該晶片2的絕緣封裝層4。該絕緣封裝層4用以防禦輻射、水氣、氧氣，以及外力破壞該 晶片2。適用的絕緣材料例如環氧樹脂、聚亞醯胺等，或者一些在固結成形為絕緣封裝層4時不會影響該晶片2性質的矽化物、氧化物等。 Referring to FIG. 5, step S4: after the assembly of the heat dissipation substrate 1 and the lead frame 3 is completed, in this step, an insulating encapsulation layer 4 covering the wafer 2, the heat dissipation substrate 1 and the lead frame 3 is formed. After the silver paste applied in the steps S1 and S3 is cured and dried, the wafer 2 is covered with a fluid or powdered insulating material, and the heat dissipating substrate 1 and the lead frame 3 are formed after the insulating material is consolidated. The insulating encapsulation layer 4 of the wafer 2 is covered and sealed. The insulating encapsulation layer 4 is used to protect against radiation, moisture, oxygen, and external forces. Wafer 2. Suitable insulating materials such as epoxy resins, polyamines, etc., or some of the tellurides, oxides, and the like which do not affect the properties of the wafer 2 when consolidated into the insulating encapsulation layer 4.
參閱圖6、8，步驟S5：本步驟為除膠、磨刷步驟，具體是要去除黏貼於每一引腳31之黏貼面311的膠帶8，並且磨刷該絕緣封裝層4之上表面41，以使每一引腳31之黏貼面311裸露出該絕緣封裝層4之下表面42且使該散熱基板1的第二面12之部分(該第一金屬層14以及該等第二金屬層15)裸露出該絕緣封裝層4之上表面41(見圖8)。由於該散熱基板1是裸露出該絕緣封裝層4之上表面41，該晶片2運作時所產生之廢熱可經由該散熱基板1導出該絕緣封裝層4之外，比起習知晶片封裝結構將廢熱導至電路板散出的方式更能有效散除該晶片2產生的廢熱。 Referring to FIGS. 6 and 8, step S5: this step is a step of removing glue and brushing, specifically removing the adhesive tape 8 adhered to the adhesive surface 311 of each of the leads 31, and brushing the upper surface 41 of the insulating encapsulation layer 4. So that the adhesive surface 311 of each of the leads 31 exposes the lower surface 42 of the insulating encapsulation layer 4 and the portion of the second surface 12 of the heat dissipation substrate 1 (the first metal layer 14 and the second metal layer) 15) The upper surface 41 of the insulating encapsulation layer 4 is exposed (see Fig. 8). Since the heat dissipating substrate 1 exposes the upper surface 41 of the insulating encapsulating layer 4, waste heat generated during operation of the wafer 2 can be led out of the insulating encapsulating layer 4 via the heat dissipating substrate 1, compared to a conventional chip package structure. The waste heat is led to the circuit board to dissipate the waste heat generated by the wafer 2 more effectively.
參閱圖7，步驟S6：本步驟是於該散熱基板1鍍覆一導熱金屬層17。該導熱金屬層17是鍍覆在該散熱基板1的第一金屬層14以及第二金屬層15上。在本實施例的製造方法中，還可以在該絕緣封裝層4之上表面41裝設一散熱片9以增進該晶片封裝結構的散熱能力。而該導熱金屬層17可以是錫、錫銀合金，或是化鎳浸金(Electroless Nickel Immersion Gold，簡稱為ENIG)，其作用在於增加該第一金屬層14之機械強度、導熱能力，以及抗腐蝕能力。此外，欲將該晶片封裝結構裝設在該電路板7之前，也須在導線架3之該等引腳31的黏貼面311鍍錫、錫銀合金，或是化鎳浸金，以保護該等引腳31。於該第一金屬層表面以及該等引腳之黏貼面311鍍覆金屬即完成該晶片封裝結構的製作。 Referring to FIG. 7, step S6: this step is to plate a heat conductive metal layer 17 on the heat dissipation substrate 1. The thermally conductive metal layer 17 is plated on the first metal layer 14 and the second metal layer 15 of the heat dissipation substrate 1. In the manufacturing method of the embodiment, a heat sink 9 may be disposed on the upper surface 41 of the insulating package layer 4 to improve the heat dissipation capability of the chip package structure. The conductive metal layer 17 may be tin, tin-silver alloy, or Electroless Nickel Immersion Gold (ENIG), which functions to increase the mechanical strength, thermal conductivity, and resistance of the first metal layer 14. Corrosion ability. In addition, in order to mount the chip package structure in front of the circuit board 7, the bonding surface 311 of the pins 31 of the lead frame 3 must be tinned, tin-silver alloy, or nickel immersion gold to protect the chip. Wait for pin 31. The surface of the first metal layer and the adhesive surface 311 of the pins are plated with metal to complete the fabrication of the chip package structure.
在本實施例的製造方法中，該絕緣封裝層4的上表面41與下表面 42都具有電性輸入/輸出(I/O)的電性接點，使用上較具有彈性。但是在其他實施態樣時也可以僅設置輸入/輸出在該絕緣封裝層4之下表面42，於此情形下即不須在該陶瓷板體13之第二表面132設置該等第二金屬層15也無須設置貫穿陶瓷板體13的該等導接線路16。此外，該散熱基板1也可以是單一金屬板，由於金屬材料之熱膨脹係數較陶瓷材料大，所以遇熱時較易膨脹變形而導致結構崩壞。又因陶瓷材料之熱膨脹係數與半導體晶片較為接近，在頻繁冷熱循環下較不會受到應力影響而分離，所以該散熱基板1較佳為使用陶瓷材料。 In the manufacturing method of the embodiment, the upper surface 41 and the lower surface of the insulating encapsulation layer 4 42 has electrical input/output (I/O) electrical contacts, which are more flexible in use. However, in other embodiments, it is also possible to provide only the input/output on the lower surface 42 of the insulating encapsulation layer 4, in which case the second metal layer is not required to be disposed on the second surface 132 of the ceramic plate body 13. 15 does not need to provide such guiding lines 16 extending through the ceramic plate body 13. In addition, the heat dissipating substrate 1 may also be a single metal plate. Since the thermal expansion coefficient of the metal material is larger than that of the ceramic material, it is more likely to expand and deform when heated, resulting in structural collapse. Moreover, since the thermal expansion coefficient of the ceramic material is relatively close to that of the semiconductor wafer and is not affected by stress under frequent cold and heat cycles, the heat dissipation substrate 1 is preferably made of a ceramic material.
綜上所述，本新型晶片封裝結構，用以裝設晶片2的散熱基板1是外露於絕緣封裝層4的上表面41，晶片2運作時所產生的熱會導至上表面41散出。比起習知的晶片封裝結構是將晶片運作時所產生的熱導至印刷電路板的方式更能有效散除晶片產生的廢熱，確實能達成本新型之目的。 In summary, in the novel chip package structure, the heat dissipation substrate 1 for mounting the wafer 2 is exposed on the upper surface 41 of the insulating package layer 4, and the heat generated when the wafer 2 operates is conducted to the upper surface 41. Compared with the conventional chip package structure, the heat generated by the operation of the wafer is guided to the printed circuit board, which is more effective in dissipating the waste heat generated by the wafer, and the object of the present invention can be achieved.
惟以上所述者，僅為本新型之實施例而已，當不能以此限定本新型實施之範圍，凡是依本新型申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾，皆仍屬本新型專利涵蓋之範圍內。 However, the above is only the embodiment of the present invention, and when it is not possible to limit the scope of the present invention, all the simple equivalent changes and modifications according to the scope of the patent application and the contents of the patent specification are still This new patent covers the scope.
11‧‧‧第一面 11‧‧‧ first side
12‧‧‧第二面 12‧‧‧ second side
13‧‧‧陶瓷板體 13‧‧‧Ceramic plate
131‧‧‧第一表面 131‧‧‧ first surface
132‧‧‧第二表面 132‧‧‧ second surface
133‧‧‧導電結構 133‧‧‧Electrical structure
14‧‧‧第一金屬層 14‧‧‧First metal layer
15‧‧‧第二金屬層 15‧‧‧Second metal layer
16‧‧‧導接線路 16‧‧‧Connected lines
17‧‧‧導熱金屬層 17‧‧‧thermal metal layer
2‧‧‧晶片 2‧‧‧ wafer
3‧‧‧導線架 3‧‧‧ lead frame
31‧‧‧引腳 31‧‧‧ pin
311‧‧‧黏貼面 311‧‧‧Adhesive surface
312‧‧‧連接面 312‧‧‧ Connection surface
41‧‧‧上表面 41‧‧‧ upper surface
42‧‧‧下表面 42‧‧‧ lower surface
7‧‧‧電路板 7‧‧‧ boards
9‧‧‧散熱片 9‧‧‧ Heat sink
Claims (8)
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| TWI607540B (en) * | 2016-11-25 | 2017-12-01 | Tong Hsing Electronic Industries Ltd | Chip package structure and manufacturing method thereof |
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| TWI607540B (en) * | 2016-11-25 | 2017-12-01 | Tong Hsing Electronic Industries Ltd | Chip package structure and manufacturing method thereof |
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