TW413926B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- TW413926B TW413926B TW088108661A TW88108661A TW413926B TW 413926 B TW413926 B TW 413926B TW 088108661 A TW088108661 A TW 088108661A TW 88108661 A TW88108661 A TW 88108661A TW 413926 B TW413926 B TW 413926B
- Authority
- TW
- Taiwan
- Prior art keywords
- signal
- instruction
- instruction decoder
- circuit
- latch
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 111
- 238000012544 monitoring process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 27
- 230000001360 synchronised effect Effects 0.000 description 23
- 230000002079 cooperative effect Effects 0.000 description 22
- 230000004044 response Effects 0.000 description 18
- 230000006870 function Effects 0.000 description 13
- 238000012546 transfer Methods 0.000 description 12
- 230000007704 transition Effects 0.000 description 11
- 238000012545 processing Methods 0.000 description 8
- CGBRFRBHFNDFDP-UHFFFAOYSA-N methyl 2-[3-[2-fluoro-5-(trifluoromethyl)phenyl]indazol-1-yl]acetate Chemical compound C12=CC=CC=C2N(CC(=O)OC)N=C1C1=CC(C(F)(F)F)=CC=C1F CGBRFRBHFNDFDP-UHFFFAOYSA-N 0.000 description 6
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 4
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 4
- 230000000875 corresponding effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000009434 installation Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- RBYOCUDWQCQSAM-UHFFFAOYSA-N 2-(3-phenyl-1-indazolyl)acetic acid methyl ester Chemical compound C12=CC=CC=C2N(CC(=O)OC)N=C1C1=CC=CC=C1 RBYOCUDWQCQSAM-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- RDYMFSUJUZBWLH-UHFFFAOYSA-N endosulfan Chemical compound C12COS(=O)OCC2C2(Cl)C(Cl)=C(Cl)C1(Cl)C2(Cl)Cl RDYMFSUJUZBWLH-UHFFFAOYSA-N 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000010587 phase diagram Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
- H03K3/356139—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14611498A JP4036531B2 (ja) | 1998-05-27 | 1998-05-27 | 半導体集積回路 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW413926B true TW413926B (en) | 2000-12-01 |
Family
ID=15400483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW088108661A TW413926B (en) | 1998-05-27 | 1999-05-26 | Semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6480033B2 (enExample) |
| JP (1) | JP4036531B2 (enExample) |
| KR (1) | KR100392046B1 (enExample) |
| TW (1) | TW413926B (enExample) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6438060B1 (en) * | 2001-02-12 | 2002-08-20 | Micron Technology, Inc. | Method of reducing standby current during power down mode |
| KR100470995B1 (ko) * | 2002-04-23 | 2005-03-08 | 삼성전자주식회사 | 클럭수신 동기회로를 갖는 멀티클럭 도메인 데이터 입력처리장치 및 그에 따른 클럭신호 인가방법 |
| US7601441B2 (en) | 2002-06-24 | 2009-10-13 | Cree, Inc. | One hundred millimeter high purity semi-insulating single crystal silicon carbide wafer |
| US6814801B2 (en) * | 2002-06-24 | 2004-11-09 | Cree, Inc. | Method for producing semi-insulating resistivity in high purity silicon carbide crystals |
| KR100605588B1 (ko) * | 2004-03-05 | 2006-07-28 | 주식회사 하이닉스반도체 | 반도체 기억 소자에서의 지연 고정 루프 및 그의 클럭록킹 방법 |
| KR100636929B1 (ko) * | 2004-11-15 | 2006-10-19 | 주식회사 하이닉스반도체 | 메모리 장치의 데이터 출력 회로 |
| US7656745B2 (en) | 2007-03-15 | 2010-02-02 | Micron Technology, Inc. | Circuit, system and method for controlling read latency |
| KR100909625B1 (ko) * | 2007-06-27 | 2009-07-27 | 주식회사 하이닉스반도체 | 어드레스 동기 회로 |
| KR101003127B1 (ko) * | 2009-02-25 | 2010-12-22 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 그 제어 방법 |
| JP5834798B2 (ja) * | 2011-11-15 | 2015-12-24 | 富士通セミコンダクター株式会社 | 半導体メモリ、半導体メモリの動作方法、システムおよび半導体メモリの製造方法 |
| US9389953B2 (en) | 2013-03-04 | 2016-07-12 | Samsung Electronics Co., Ltd. | Semiconductor memory device and system conducting parity check and operating method of semiconductor memory device |
| US9865317B2 (en) | 2016-04-26 | 2018-01-09 | Micron Technology, Inc. | Methods and apparatuses including command delay adjustment circuit |
| US9997220B2 (en) | 2016-08-22 | 2018-06-12 | Micron Technology, Inc. | Apparatuses and methods for adjusting delay of command signal path |
| US10032508B1 (en) | 2016-12-30 | 2018-07-24 | Intel Corporation | Method and apparatus for multi-level setback read for three dimensional crosspoint memory |
| US10224938B2 (en) | 2017-07-26 | 2019-03-05 | Micron Technology, Inc. | Apparatuses and methods for indirectly detecting phase variations |
| CN112447218B (zh) * | 2019-08-29 | 2025-05-06 | 台湾积体电路制造股份有限公司 | 存储器电路和方法 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2697633B2 (ja) | 1994-09-30 | 1998-01-14 | 日本電気株式会社 | 同期型半導体記憶装置 |
| US5559752A (en) * | 1995-08-14 | 1996-09-24 | Alliance Semiconductor Corporation | Timing control circuit for synchronous static random access memory |
| JP3566429B2 (ja) * | 1995-12-19 | 2004-09-15 | 株式会社ルネサステクノロジ | 同期型半導体記憶装置 |
| JP3759645B2 (ja) * | 1995-12-25 | 2006-03-29 | 三菱電機株式会社 | 同期型半導体記憶装置 |
| JPH10208470A (ja) * | 1997-01-17 | 1998-08-07 | Nec Corp | 同期型半導体記憶装置 |
| JP3827406B2 (ja) * | 1997-06-25 | 2006-09-27 | 富士通株式会社 | クロック同期型入力回路及びそれを利用した半導体記憶装置 |
-
1998
- 1998-05-27 JP JP14611498A patent/JP4036531B2/ja not_active Expired - Fee Related
-
1999
- 1999-05-25 US US09/317,619 patent/US6480033B2/en not_active Expired - Lifetime
- 1999-05-26 TW TW088108661A patent/TW413926B/zh not_active IP Right Cessation
- 1999-05-26 KR KR10-1999-0018988A patent/KR100392046B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US6480033B2 (en) | 2002-11-12 |
| US20020027451A1 (en) | 2002-03-07 |
| JPH11339471A (ja) | 1999-12-10 |
| KR100392046B1 (ko) | 2003-07-22 |
| KR19990088556A (ko) | 1999-12-27 |
| JP4036531B2 (ja) | 2008-01-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |