TW410438B - Integrated circuit with twin tub - Google Patents

Integrated circuit with twin tub Download PDF

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Publication number
TW410438B
TW410438B TW086120081A TW86120081A TW410438B TW 410438 B TW410438 B TW 410438B TW 086120081 A TW086120081 A TW 086120081A TW 86120081 A TW86120081 A TW 86120081A TW 410438 B TW410438 B TW 410438B
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Taiwan
Prior art keywords
integrated circuit
substrate
region
item
type
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TW086120081A
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English (en)
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Sailesh Chittipeddi
William Thomas Cochran
Stephen Knight
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Lucent Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Description

410436 五、發明說明Ο ) 〔發明領域〕 本發明係關於雙槽積體電路及其製造方法^ 〔發明背景〕 有許多的CMO S積體電路係使用具有雙槽之基底。 其中一槽通常摻雜η型摻雜劑，然而另一槽則摻雜ρ型摻 雜劑。有關雙槽專利之例子可見第4 4 3 5 8 9 6號美國 專利，該專利已給予巴里歐（PariUo )等人。 某些雙槽製造法所製成的產品，其中η槽與ρ槽之上 矽表面間具有高度差。易言之，ρ槽之上矽表面和η槽之 上矽表面係非共平面。當積體電路電路佈局之尺寸減縮時 ’欠缺共平面性會導致難以達成適當的步進焦點（stepper focus)。（隨後欲除去或減低非共平面性時，尙需額外的 光罩及負擔額外的成本=) 那些關切積體電路發展之人士皆已一貫地探求能在半 導體基底中製造雙槽之新的及改良的方法。 〔發明槪述〕 本發明係包含： 澱積一種覆蓋基底第一表面之第一材料； 穿透基底第二表面植入一種或更多之第一導電型摻雜 劑： 澱積一種覆蓋基底第二表面之第二材料： 芽透基底第一表面植入一種或更多之第二導電型摻雜 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） 修 -I I I I----- 1 --- (諝先閱讀背面之注意事項再填寫本頁} J 言 --線丨 經濟部智慧財產局員工消費合作社印製 -4- 410438 A7 經濟部智慧財產局員工消費合作社印製 B7___五、發明.說明（2 ) 劑； 〔圖示簡單說明〕 ' 圖1至圖8係有助於理解本發明實施例之剖視圖。 主要元件對照表 11 基底 13 外延層 1 5 '墊狀氧化層 17 光致抗蝕劑 19 1 離子植入法 2 3 區域 2 1 防護材料 19 上表面 2 5 上表面 2 7 區域 3 1 上表面 2 9 上表面 115 墊狀氧化層 116 場氧化層 1 2 3 區域 121 防護材料 19 2 摻雜物質 12 7 區域 (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） -5- 經濟部智慧財產局員工消費合作社印製 _41043^ b7__ 五、發明.說明<?) 〔詳細說明〕 在圖1中，參考數11係表示p型基底。（無論如何 >基底1 1亦可爲η型或本質型。）就大體而論，名辭" 基底#係指一材料，於其上可形成其它材料。它種合適的 基底係砷化鎵及其合金、氮化鎵等等。磷化銦及其合金亦 係合適的基底=在本實施例中1參考數1 3係指一厚度介 於2至15微米之選擇性ρ型外延材料層。在本實施例中 ，參考數1 5係指一厚度介於3 5 0至4 5 0埃之墊狀氧 化層。在本實施例中|將基底11放置於溫度約爲 1 0 0 Ot之氧化環境中，墊狀氧化層1 5即可形成。亦 可採用其它方法，並且這些方法皆爲熟習該項技術之人士 所知曉。參考數1 7係指一光致抗蝕劑，其藉由摹製以覆 蓋並保護一部分基底。 光致抗蝕劑1 7澱積之後，可選擇性淸除一部分曝露 的墊狀氧化層1 5 *以獲得淸潔的上氧化表面。在本實施 例中，使用電漿蝕刻除去5 0埃之墊狀氧化層1 5。 接下來，以一種或更多不同的η型物質執行離子植入 1 9 1。亦可選擇以分別兩次之方式，植入相同的η型物 質。在本實施例中，第一次植入時係使用磷且較淺，隨後 第二次植入時係使用砷且較深。在本實施例中，每一次植 入能量係介於0至3 0 0仟電子伏特之間，且劑量範圍係 介於每平方公分1 Ε 1 1至5 Ε 1 6之間。因應所設計之 電路類型，熟習該項技術之人士即可選擇適當的植入物質 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -6 - (請先閱讀背面之注意事項再填寫本頁) -f — i- --------線< 41043€ A7 -------B7__ 五、發明.說明（4 ) 、能量和劑量。 爹見圖2，外延層丨3內之11型植入物質係以參考數 2 3表示之。 (請先閲讀背面之注意事項再填寫本頁) 圖2顯示藉由上述之選擇性電漿蝕刻，係已減低一部 分覆蓋區域2 3之墊狀氧化層i 5。因著隨後退火處理’ 參考數2 3所代表的區域即可形成 繼之而來，.防護材料2 1主要澱積於已植入完成的^ 區域2 3上。有部分防護材料2 1亦會澱積於光致抗蝕劑 17之上表面1 9上。適當的防護材料係：自旋玻璃（ spin on glass)，聚醯亞胺（p〇iyimide)、#spin_〇n製程形 成之氮化駄、平面化低溫玻璃以及任何具有鈾刻率異於光 致抗触劑1 7之其它材料。選取防護材料2 1之厚度；使 材料2 1足夠保護η槽2 3免受後來的p型物質植入，此 Ρ型物質將於後面解釋之。 在本實施例中’係全面性澱積防護材料2 1 ，並且隨 後以化學-機械拋光（CMP)磨平整片晶圓，或者亦可 使用澱積-蝕刻-澱積等製程。 經濟部智慧財產局員工消費合作社印製 在區域2 3 (此區域經退火後將變成η槽）上已形成 防護材料2 1之後，藉由經微淨化蝕刻或c Μ Ρ等方法， 除去任何彤成於光致抗蝕劑1 7上表面1 9上之防護材料 2卜 參見圖3，光致抗蝕劑1 7係已除去。在適霄地淸潔 氧化層1 5之上表面2 5後，植入一種或兩種Ρ型摻雜物 質於外延層1 3內。在本實施例中’分別兩次將硼植入， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) ~ " A7 410 f B7 五、發明說明（5 ) 其中一次係深植入，另一次係淺植入，進而製成一 p區域 27。如圖上所繪，p區域27係較n區域23稍深，然 而此一需求並不必然總是正確。 爹見圖4 ’防護材料2 1係已除去。藉由檢視圖4 ， 將會注意到：當除去氧化層1 5時，n槽2 3上之表面 3 1與Ρ槽2 7之上表面2 9係相互共平面。 在這一點上，可繼續進行依據著標準方法的下一步製 程。Ρ區域2 7及一區域2 3可經退火而製成相應的ρ槽 及η槽。利用LOCOS或多晶緩衝LOCOS或其它公 知的製程技術’可製成場氧化層。然後製成閘極並且形成 電介質層和金屬噴鍍。 圖5至圖8說明本發明之另一實施例，其中場氧化物 係先於槽製成前形成。例如，在圖5中，參考數1 1表示 基底，而參考數1 3則表示選擇性外延層。參考數 1 1 5表示墊狀氧化層，而參考數1 1 6則表示場氧化層 。在本實施例中，以L 0 C 0 S製程或多晶緩衝 LOCOS製程形成場氧化層1 1 6。參考數1 7係指一 光致抗蝕劑’其已藉由摹製以致覆蓋並保護一部分基底。 再一次，可選擇性消除一部分曝露的墊狀氧化層1丨5。 隨後執行一種或更多不同植入物質之離子植入191。在 本實施例中，植入能量及劑量已於前面述及。參見圖6， 該植入物質形成區域1 2 3。繼之而來，澱積防護材料 1 2 1。可作爲防護材料1 2 1使用的適宜候選材料^於 前面述及。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)
-¾--------I 線' 經濟部智慧財產局員工消費合作社印製 -8 - A7 B7 410436五、發明說明（6 ) 在圖8中’光致抗蝕劑1 7與任何覆蓋材料係皆已— 起除去。然後植入一種或兩種摻雜物質1 9 2進而形成區 域1 2 7。在除去材料1 2 1又經適宜熱處理之後，區域 1 2 3及1 2 3可退火進而形成互補的雙槽=在一點上， 可繼續進行依據箸標準方法的下一步製程。製成閘極並且 形成電介質及金屬噴鍍。
Vi (請先閱讀背面之注意事項再填寫本頁) -------訂---- -----線'. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -9 -

Claims (1)

  1. 7 i'V a A8 4ι〇43β 1 六、申請專利範圍 丄·一種積體電路之製造方法，包含： 澱積一種覆蓋基底1 3之第一表面之第一材料1 7 ; 穿透該基底第二表面植入一種或更多之第一型物質. 19 1； 澱積一種覆蓋該基底2 3之該第二表面之第二材料 2 1: 除去該第一材料1 7 ;以及 穿透該基底2 3之該第一表面植入一種或更多之第二 型物質1 9 2。 2 ·如申請專利範圍第1項之積體電路製造方法，其 中該第一材料17係光致抗蝕劑。 3.如申請專利範圍第1項之積體電路製造方法，其 中該基底係矽2 3。 4 .如申請專利範圍第1項之積體電路製造方法，其 中該第二材料21係選自由旋玻璃、聚醯亞胺、氮化鈦及 平面化低溫玻璃中。 5 .如申請專利範圍第1項之積體電路製造方法，其 中該第一型物質1 9 1係一η型物質。 6 .如申請專利範圍第5項之積體電路製造方法’其 中該第二型物質1 9 2係一Ρ型物質。 -卜---.------------ {請先閱讀背面之注意事項再填寫本頁) --線. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -10-
TW086120081A 1996-12-31 1998-01-14 Integrated circuit with twin tub TW410438B (en)

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US08/775,490 US6017787A (en) 1996-12-31 1996-12-31 Integrated circuit with twin tub

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US (1) US6017787A (zh)
EP (1) EP0851468A3 (zh)
JP (1) JP3253908B2 (zh)
KR (1) KR100554648B1 (zh)
TW (1) TW410438B (zh)

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EP0851468A3 (en) 1998-08-05
EP0851468A2 (en) 1998-07-01
KR19980064838A (ko) 1998-10-07
KR100554648B1 (ko) 2006-04-21
JP3253908B2 (ja) 2002-02-04
US6017787A (en) 2000-01-25
JPH10209297A (ja) 1998-08-07

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