301769301769
經濟部中央橾準局Μ工消費合作社印製 五、發明説明（1 ) 本發明是有關於一種在半導體基底（a semiconductor substrate)形成雙井區（Twin-Tub Well)之製造方法’且特別 是有關於一種在半導體基底形成自動對準（seif-aHgned)且 只需一道光阻罩幕層的雙井區之製造方法’其可使該半導 體基底具有一平坦的表面。 雙井區技術可以在一淡摻雜的矽基底形成分別適用於 η-型電晶體和p-型電晶體的兩種井區，且該兩種井區之摻 雜分佈可以獨立地調控，因此η-Μ與Ρ-型電晶體皆可達到 最佳化。雙井區技術的主要優點是在不影響電晶體性能的 情況下，可以隨意地選擇矽基底的摻雜種類；另外，在高密 度電路應用中，η-型電晶體和ρ-型電晶體之距離也可以被 適當地縮減。更進一步而言，在次微米範圍內，η-型和ρ-型電晶體相似地工作，故提供對稱的η-型和ρ-型元件是有 意義的；而且摻雜濃度已被提高，故元件製作在矽基底或井 區之上已無多大區別。所以，在次微米尺寸下，雙井區互 補式金氧半導體（CMOS; Complementary Metal-Oxide-Semiconductor)製程便大行其道。 傳統雙井區技術的製作方法有兩種。一種方法是利用 兩道不同的光罩分別定義η-井區和ρ·井區。但此製程必須 要多一層光罩，製作成本較高，而且η_井區和井區之間 也無法自動對準，η-井區和ρ-井區之間的設計準則（Design Rules)也無法縮減。另一種方法是自動對準雙井區之製造方 法，示於第1A至1C圖。該製造方法是在^或卜型的矽基 底10上，形成一一執化砂層20以及〜氮化砂層3〇之n_井 本紙張尺度適用中國國家檍缴i rNS ) A4規格（210X297A^ • U9 -5 (請先閱讀背面之注意事項再填寫本頁)Printed by the Central Industry Bureau of the Ministry of Economic Affairs, M Industry and Consumer Cooperatives V. Description of the invention (1) The present invention relates to a manufacturing method of forming a twin-well area (a Twin-Tub Well) on a semiconductor substrate 'and in particular It is related to a method of manufacturing a double-well region that forms a self-aligned (seif-aHgned) on a semiconductor substrate and requires only one photoresist mask layer, which enables the semiconductor substrate to have a flat surface. The dual-well region technology can form two well regions suitable for η-type transistors and p-type transistors on a lightly doped silicon substrate, and the doping distribution of the two well regions can be independently adjusted, so η- Both Μ and Ρ-type transistors can be optimized. The main advantage of the dual-well technology is that the doping type of the silicon substrate can be arbitrarily selected without affecting the performance of the transistor; in addition, in high-density circuit applications, η-type transistors and ρ-type transistors The distance can also be reduced appropriately. Furthermore, in the sub-micron range, η-type and ρ-type transistors work similarly, so it makes sense to provide symmetric η-type and ρ-type elements; and the doping concentration has been increased, so the element It is not much different if it is made on silicon substrate or well area. Therefore, in the sub-micron size, the complementary metal oxide semiconductor (CMOS; Complementary Metal-Oxide-Semiconductor) process is popular. There are two methods of manufacturing traditional Shuangjing technology. One method is to use two different masks to define η-well area and ρ · well area respectively. However, this process requires an additional mask, and the manufacturing cost is higher, and the η_well area and the well area cannot be automatically aligned, and the design rules between the η-well area and the ρ-well area (Design Rules) also It cannot be reduced. The other method is a method of automatically aligning the double well area, shown in Figures 1A to 1C. The manufacturing method is to form a one-on-one sand layer 20 and a ~ nitride sand layer 30 on the silicon substrate 10 of ^ or Bu type. The size of this paper is applicable to the Chinese National Standard (ARS) A4 (210X297A ^ • U9 -5 (Please read the notes on the back before filling this page)
A7 B7 經濟部中央標準局工消t合作社印製 五、發明説明（2 ) 區罩幕層，並植入η型離子70於矽基底表層內，如第ιΑ 圖所示。接著，以一高溫氧化擴散步驟，驅入已植入之n 型離子80，形成η型井區12及一厚二氧化矽層22。然後， 去除掉氮化矽層3〇，再以該厚二氧化矽層22爲罩幕，施行 一 ρ型離子植入，將Ρ型離子72植入於矽基底表層內，如 第1Β圖所示。接著，再以另一高溫擴散步驟，驅入已植Λ 之Ρ型離子82，而形成Ρ型井區14。請參照第1C圖，去 除掉二氧化矽層20和厚二氧化矽層22之後，矽基底即具有 自動對準雙井區。上述的自動對準雙井區製造方法，最早 揭露於刊載在I982年出版的IEDM Tech. Dig.第706頁，篇 名爲“Twin-Tub CMOS Π : An advanced VLSI technology” 之文章上。然而，存在於井區交界處之步階，容易造成複 晶矽閘極的光阻曝光問題而影響了複晶矽線條的尺寸控 制，尤有甚者，更影響了後段製程的曝光成像焦距變異過 大的問題。因此，如何減少自動對準雙井區製程中形成於 井區交界處之步階的落差，即成爲吾人所面對的一項重要 課題。 緣此，本發明的一主要目的就是在提供一種在半導體 基底形成自動對準雙井區的製造方法，其所製成的半導體 基底具有一平坦的表面，以減少後續製程的曝光成像問 題。 依照本發明之一特點，一種在半導體基底形成自動對 準雙井區的製造方法包括下列步驟：a.在半導體基底上形 成一二氧化砂層;b.在該二氧化砂層上形成一犧牲層;c.定義 4 {靖先閱讀背面之注意事項再嗔寫本頁，> .裝 、βτ 線 本紙張尺度適用中國國家標隼（CNS ) A4規格（21〇χ297公釐） 經濟部中央標隼局員工消費合作社印製 301769 at B7 五、發明説明（3 ) (patterning)該犧牲層，以露出該二氧化砍層之一部份;d.植 入第一型離子，穿過該露出之二氣化矽層，以達到該半導 體基底之表層內；e.形成一平坦化層，並以化學機械式硏磨 法，硏磨掉該平坦化層位於該犧牲層上方的部份;f.去除該 犧牲層;g.植入第二型離子，穿過未被該平坦化層覆蓋住之 二氧化矽層，以達到該半導體基之表層內，其中，植入該 基底之該第一型離子和該第二型離子爲自動對準;以及h.執 行一高溫擴散步驟，以驅入該些植入之離子，形成自動對 準之第一型和第二型雙井區。 依照本發明的一較佳實施例，在平坦化層形成之後， 可更包括執行一高溫擴散步驟，以驅入該植入之第一型離 子，因此，第一型井區和第二型井區可以分開地調整。 爲讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉若干較佳實施例，並配合所附圖式，作詳 細說明如下。 圖示之簡單說明： 第1A至1C圖係一系列剖面圖，用以解釋習知的自動 對準雙井區製造方法。 第2A至2F圖係一系列剖面圖，用以解釋本發明的一 種在半導體基底形成自動對準雙井區之製造方法的第一較 佳實施例。 第3A至3F圖係一系列剖面圖，用以解釋本發明的一 種在半導體基底形成自動對準雙井區之製造方法的第二較 佳實施例。 5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） . 裝 訂 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 A7 B7 五、發明説明（4 ) 接著將參照第2A至2F圖，詳述本發明的一種在半導 體基底形成自動對準雙井區的製造方法之第一較佳實施 例。請參照第2A圖，首先在一牵導體基底10，例如一矽 基底（a silicon substrate)之表面形成一二氧化矽層24;該矽 基底可爲η-型基底或p-型基底，該二氧化矽層24可以用傳 統高溫爐管氧化技術來達成。接著，利用一低壓化學氣相 沈積法（Low Pressure Chemical Vapor Deposition;LPCVD)或 電篥增強式化學氣相沈積法（Plasma Enhanced Chemical Vapor Deposition，PECVD)，在二氧化砂層24的整個表面 上沈積一犧牲層32(a first sacrificial layer)，例如一氮化砂 層。在本較佳實施例中，該氮化矽層32之厚度，例如約在 1000至4000埃（Angstroms)之間;該二氧化砂層24之厚度， 例如約爲250至500埃之間。 請參照第2B圖，接著，以傳統的光罩製版 (photolithography)和蝕刻技術定義第一型井區。亦即，如第 2B圖所示，在氮化矽層34之上覆蓋一光阻層，並利用步進 機(stepper)曝光和顯影步驟，將第一型井區之圖案移轉至該 光阻層，而得到第一型并區之光阻罩幕層60。利用該光阻 罩幕層60爲蝕刻罩幕，以傳統活性離子蝕刻法(Reactive-I〇n Etching;RIE)進行非均向性触刻（Anisotropic Etching)，將未 被遮蔽的氮化矽層32去除掉，直至二氧化矽層24露出爲 止’而未被蝕刻去除掉的氮化矽層部份（記爲34)則位於光 阻罩幕層60之下方，且與該光阻罩幕層60爲相同之第一型 井區圖案。然後，利用離子佈植技術（Ion Implantation 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）. ^----------扣衣------1Τ------# (請先閲讀背面之注意事項再填寫本頁) A7 301769 B7 五、發明説明（5)A7 B7 Printed by the Cooperative Society of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of the invention (2) Zone cover curtain layer, and implant n-type ions 70 in the surface layer of the silicon substrate, as shown in Figure IA. Next, in a high temperature oxidation diffusion step, the implanted n-type ions 80 are driven to form the n-type well region 12 and a thick silicon dioxide layer 22. Then, the silicon nitride layer 30 is removed, and then the thick silicon dioxide layer 22 is used as a mask to perform a p-type ion implantation, and the p-type ion 72 is implanted into the surface layer of the silicon substrate, as shown in FIG. 1B Show. Then, in another high-temperature diffusion step, the p-type ions 82 implanted with Λ are driven to form the p-type well region 14. Referring to FIG. 1C, after the silicon dioxide layer 20 and the thick silicon dioxide layer 22 are removed, the silicon substrate is automatically aligned with the double-well region. The above-mentioned automatic alignment manufacturing method for Shuangjing District was first revealed in the article titled "Twin-Tub CMOS Π: An advanced VLSI technology" published on page 706 of IEDM Tech. Dig. Published in I982. However, the steps existing at the junction of the well area are likely to cause the photoresist exposure problem of the polycrystalline silicon gate and affect the size control of the polycrystalline silicon lines, especially, it also affects the exposure imaging focal length variation of the subsequent process Excessive problem. Therefore, how to reduce the gap between the steps formed at the junction of the wells in the process of automatically aligning the two wells has become an important issue facing us. Therefore, a main object of the present invention is to provide a manufacturing method for forming a self-aligned double-well region on a semiconductor substrate. The manufactured semiconductor substrate has a flat surface to reduce exposure imaging problems in subsequent processes. According to one feature of the present invention, a manufacturing method for forming a self-aligned double-well region on a semiconductor substrate includes the following steps: a. Forming a dioxide sand layer on the semiconductor substrate; b. Forming a sacrificial layer on the dioxide sand layer; c. Definition 4 {Jing first read the precautions on the back and then write this page, >. installed, βτ line paper size is applicable to China National Standard Falcon (CNS) A4 specifications (21〇 × 297 mm) Central Ministry of Economic Standard Falcon Printed 301769 at B7 by the Consumer Cooperative of the Bureau. 5. Description of the invention (3) (patterning) the sacrificial layer to expose a part of the chopped dioxide layer; d. Implanting the first type ions through the exposed second Vaporize the silicon layer to reach the surface layer of the semiconductor substrate; e. Form a planarization layer, and use chemical mechanical grinding to remove the planarization layer above the sacrificial layer; f. Remove The sacrificial layer; g. Implanted second type ions, through the silicon dioxide layer not covered by the planarization layer, to reach the surface layer of the semiconductor base, wherein the first type ions implanted on the substrate And the second type ion is automatically aligned; and h. A high temperature diffusion step to drive the implanted ions to form the self-aligned first-type and second-type double-well regions. According to a preferred embodiment of the present invention, after the planarization layer is formed, a high temperature diffusion step may be further included to drive the implanted first type ions, therefore, the first type well region and the second type well The zones can be adjusted separately. To make the above and other objects, features, and advantages of the present invention more comprehensible, several preferred embodiments are described below in conjunction with the accompanying drawings, which are described in detail below. Brief description of the figures: Figures 1A to 1C are a series of cross-sectional views to explain the conventional manufacturing method of automatic alignment in the double well area. Figures 2A to 2F are a series of cross-sectional views for explaining a first preferred embodiment of a manufacturing method for forming an automatic alignment double-well region on a semiconductor substrate of the present invention. Figures 3A to 3F are a series of cross-sectional views for explaining a second preferred embodiment of a manufacturing method for forming an automatic alignment double-well region on a semiconductor substrate of the present invention. 5 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm). Binding line (please read the precautions on the back before filling out this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs Description (4) Next, referring to FIGS. 2A to 2F, a first preferred embodiment of a manufacturing method for forming an automatic alignment double-well region on a semiconductor substrate of the present invention will be described in detail. Please refer to FIG. 2A. First, a silicon dioxide layer 24 is formed on the surface of a conductive substrate 10, such as a silicon substrate; the silicon substrate may be an n-type substrate or a p-type substrate. The silicon oxide layer 24 can be achieved using conventional high-temperature furnace tube oxidation technology. Next, a low-pressure chemical vapor deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD) is used to deposit one on the entire surface of the sand dioxide layer 24 A sacrificial layer 32 (a first sacrificial layer), such as a nitride sand layer. In the preferred embodiment, the thickness of the silicon nitride layer 32 is, for example, about 1000 to 4000 Angstroms (Angstroms); the thickness of the sand dioxide layer 24 is, for example, about 250 to 500 Angstroms. Please refer to FIG. 2B. Then, the first type well area is defined by conventional photolithography and etching techniques. That is, as shown in FIG. 2B, a photoresist layer is covered on the silicon nitride layer 34, and a stepper exposure and development steps are used to transfer the pattern of the first type well region to the light Resist layer to obtain the first type of parallel photoresist mask layer 60. Using the photoresist mask layer 60 as an etch mask, anisotropic etching (Anisotropic Etching) is performed by traditional reactive ion etching (RIE) to remove the unshielded silicon nitride layer 32 is removed until the silicon dioxide layer 24 is exposed, and the portion of the silicon nitride layer (denoted as 34) that has not been removed by etching is located below the photoresist mask layer 60 and is in contact with the photoresist mask layer 60 is the same type 1 well pattern. Then, the use of ion implantation technology (Ion Implantation 6 This paper standard applies to China National Standards (CNS) A4 specifications (210X 297 mm). ^ ---------- Clothing ----- 1T ------ # (Please read the precautions on the back before filling in this page) A7 301769 B7 5. Description of the invention (5)
Technique) ’施行第一型離子74之佈植，未有氮化矽罩幕 層34和光阻罩幕層60之部份，第一型離子74則穿透二氣 化砂層24 ’並植入於矽基底10之表層內，且記爲1〇1。在 此，氮化矽罩幕層34和光阻罩幕層60共同做爲第一型離子 植入時之罩幕層;若氮化矽罩幕層34即可提供足夠的罩幕 效果’則光阻罩幕層60亦可於第—型離子植入前，先行去 除。再者，第一型井區可爲η-型離子或p_型離子，爲說明 方便起見，在本較佳實施例中，第一型井區爲n_型井區， 第一型離子爲η型離子，例如爲磷離子（p3i)。 請參照第2C圖，在植入n型離子74和去除光阻罩幕 層6〇之後，接著利用LPCVD法莽PECVD法，沈積一平坦 化層50，例如一二氧化砂層。該平坦化層5〇均句覆蓋住氮 化矽罩幕層34和露出之二氧化矽層24之表面，其厚度可爲 氮化矽罩幕層34的厚度以上，例如約爲5000埃。 請參照第2D圖，接著利用化學機械式硏磨（Chemica丨 Mechanical Polish;CMP)技術，硏磨第2C圖結構的表面，並 以氮化砂罩幕層34爲硏磨飽刻終點，硏磨掉平坦化層5〇 位於氮化矽罩幕層34上方之部份，直至該氮化砂罩幕層34 之頂部露出爲止。在此步驟中’如第2D圖所示，剩j餘的平： 坦化層（記爲51)約與氮化砂罩幕層34等高，且其邊緣跑已 植入之η-型離子101之邊緣爲自動對準。 然後，如第2Ε圖所示，以傳統濕式蝕刻法（WetEtching) 或乾式電漿蝕刻（Plasma etching)技術，去除掉氮化砂罩幕 層34。該濕式蝕刻式法可爲溫度在160 °C〜180。(：之熱憐酸 7 本紙張尺度適用中國國家標準（CNS’）A4規格（210 X297公f~'----— ^ ^ 裝 訂 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作杜印製 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（6 ) 液，該乾式電漿蝕刻技術可爲含氟活性離子之氣體電漿。 接著，利用離子佈植技術，並以平坦化罩幕層51爲阻絕罩 幕層，施行第二型離子76之佈植。在未有平坦化罩幕層51 之部份，第二型離子76則穿透二氧化矽層24，並植入於矽 基底10之表層內，且記爲103。在此步驟中，該第二型離 子76，相對於第一型離子74，爲p-型離子，例如爲硼離 子(B11)。必須注意的是，第二型離子76以平坦化層51爲 罩幕，因此，植入於矽基底的離子之邊緣與該平坦化罩幕 層51切齊；亦即，已植入的第二型離子103與已植入的第一 型離子101爲自動對準。 接著，請參照第2F圖，以高溫擴散(Diffusion)技術， 在例如爲800 °C〜1200 °C氮氣環境下驅入已植入之離子，並 使已植入之第一型離子101和已植入之第二型離子1〇3分 別驅入一深度，而個別形成第一型井區102和第二型井區 104，且該第一型井區102與該第二型井區1〇4爲自動對 準。至此，自動對準雙井區於焉形成’並且該矽基底10之 表面未被氧化，故於平坦化罩幕層51和二氧化矽層24去除 之後，矽基底10之表面爲平坦的，亦即，在第一型井區102 和第二型井區104交界處沒有步階(step)存在’此如第2F 圖所示。 依照上述本發明的製造方法所製成的半導體基底可以 具有一平坦的表面，如此即可解決習知技術所遭遇的後續 製程的曝光成像問題。 在此較佳實施中，第一型井區爲n-型井區，而第二型 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） 扣衣 訂 線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印裝 Μ Β7 五、發明説明（7 ) 井區爲P-型井區；然而本發明並不限於此，該第一型井區亦 可爲P-型井區，而該第二型井區則爲η-型井區。第一型離 子與第二型離子亦然。另外，在此較佳實施例中，犧牲層 爲一氮化矽層，平坦化層爲一二氧矽層;然而根據本發明之 精神，該二層只要是不同材質即可，例如，犧牲層可爲一 二氧化矽層，平坦化層則爲一氮化矽層或一複晶矽層；或 者，犧牲層可爲一複晶矽層，平坦化層則爲一二氧化矽層 或一氮化矽層。 在上述第一較佳實施例中，第一型離子與第二型離子 在同一個高溫擴散步驟中，被驅入而形成第一型井區和第 二型井區。然而，本發明並不限於此，依據本發明之精神， 第一型離子與第二型離子可以分別被趨入，亦即，第一型 離子可以第一次高溫擴散步驟驅入，而第一、二型離子可 同時再以第二次高溫擴散步驟驅入。其中，第一次高溫擴 散步驟可於平坦化層沈積前執行，也可於平坦化層沈積後 執行;下一個較佳實施例即將描述第一次高溫擴散步驟於平 坦化層沈積前執行之製造方法。 接著將參照第3Α至3F圖，詳述本發明的一種在半導 體基底形成自動對準雙井區的製造方法之第二較佳實施 例。本較佳實施例係以第2Β圖所示的較佳實施例之結構爲 基礎，再以不同的製程製作類似結構的自動對準雙井區。 在第3Α至3F圖中，與第2Β圖相似的部份係以相同的編號 標示。 請參照第3Α和2Β圖，第二較佳實施例進行至植入第 9 ----------^------1Τ------^ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） 經濟部中央標準局員工消費合作社印裝 A7 __B7 . _ 五、發明説明（8 ) 一型離子而形成第一型植入離子101之步驟爲止，與第一 較佳實施例之步驟是相同的。接著去除掉光阻罩層60，並 施行一第一次高溫擴散步驟，來驅入第一型植入離子層 101，而形成第一型井區105，如第3B圖所示。該第一次 高溫擴散步驟可以例如爲800 °C〜1200 °C之氮氣環境來完 成。 請參照第3C圖，接著利用LPCVD法或PECVD法，沈 積一平坦化層50，例如一二氧化矽層。該平坦化層50均勻 覆蓋住氮化矽罩幕層34和露出之;二氧化矽層24之表面，其 厚度可爲氮化矽罩幕層34的厚度以上。 請參照第3D圖，接著利用化學機械式硏磨技術，硏磨 第3C圖結構的表面，並以氮化矽罩幕層35爲硏磨蝕刻終 點，硏磨掉該平坦化層50位於該氮化砂罩幕層34上方之部 份，直至該氮化矽罩幕層34之頂部露出爲止。在此步驟中， 如第3D圖所示，剩餘的平坦化層（記爲51)約與氮化矽罩幕 層34等高。 然後，如第3E圖所示，以傳統濕式蝕刻法或乾式電漿 触刻技術，去除掉氮化砂罩幕層34。接著，利用離子佈植 技術，並以平坦化罩幕層51爲阻絕罩層，施行第二型離子 76之佈植，未有平坦化罩幕層51之部份，第二型離子76 則穿透二氧化矽層24，並植入於矽基底10之表層內，且記 爲103。在此步驟中，該第二型離子76爲例如硼離子2p_ 型離子。 接著，請參照第3F圖，以一第二次高溫擴散步驟，在 i I I I I 裝— 訂 n I 線 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（2!〇><297公釐〉 301769 A7 B7 五、發明説明（9 ) 例如爲800 °C〜1200 °C氮氣環境下驅入已植入之第一、二型 離子105及103，而分別形成第一、二型井區107及106。 至此，自動對準雙井區於焉形成。去除掉平坦化罩幕層51 和二氧化矽層24之後，矽基底10即可進行後續的製程。同 樣的，如第一較佳實施例所述，形成雙井區之後的矽基底 10表面仍爲平坦的。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 ^ 种衣 訂 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 11 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）Technique) 'Implementation of the first type ion 74 without the silicon nitride mask layer 34 and the photoresist mask layer 60, the first type ion 74 penetrates the second gasification sand layer 24' and implants in In the surface layer of the silicon substrate 10, it is denoted as 101. Here, the silicon nitride mask layer 34 and the photoresist mask layer 60 are used together as the mask layer when the first type of ion implantation; if the silicon nitride mask layer 34 can provide sufficient mask effect The barrier mask layer 60 can also be removed before the first-type ion implantation. Furthermore, the first type well region may be η-type ion or p_ type ion. For convenience of description, in the preferred embodiment, the first type well region is n_ type well region, and the first type ion It is an n-type ion, for example, a phosphorus ion (p3i). Referring to FIG. 2C, after implanting n-type ions 74 and removing the photoresist mask layer 60, a planarization layer 50, such as a sand dioxide layer, is deposited by LPCVD and PECVD. The planarization layer 50 covers the surface of the silicon nitride mask layer 34 and the exposed silicon dioxide layer 24, and its thickness may be more than the thickness of the silicon nitride mask layer 34, for example, about 5000 angstroms. Please refer to Figure 2D, and then use the chemical mechanical polishing (Chemica 丨 Mechanical Polish; CMP) technology to polish the surface of the structure of Figure 2C, and use the nitrided sand cover curtain layer 34 as the end point of the polishing, the polishing The portion of the planarization layer 50 above the silicon nitride mask layer 34 is removed until the top of the sand nitride mask layer 34 is exposed. In this step, as shown in Fig. 2D, there are more than j flat: the flattened layer (marked as 51) is about the same height as the nitrided sand mask curtain layer 34, and its edge runs with the implanted η-type ions The edge of 101 is automatically aligned. Then, as shown in FIG. 2E, the nitride sand mask layer 34 is removed by conventional wet etching (WetEtching) or dry plasma etching (Plasma etching) techniques. The wet etching method may be at a temperature of 160 ° C ~ 180. (： The heat of acid 7 This paper scale is applicable to the Chinese National Standard (CNS ') A4 specification (210 X297 male f ~' ------ ^ ^ binding line (please read the precautions on the back before filling this page) Economy Ministry of Central Standard Falcon Bureau Employee Consumption Cooperation Du Printed A7 B7 printed by Employee Consumer Cooperative of Central Standard Bureau of Ministry of Economy V. Invention description (6) Liquid, the dry plasma etching technology can be a gas plasma containing fluorine active ions. , Using ion implantation technology, and using the flattened mask curtain layer 51 as the blocking mask layer, to implement the implantation of the second type ion 76. In the part without the flattened mask curtain layer 51, the second type ion 76 is It penetrates the silicon dioxide layer 24 and is implanted in the surface layer of the silicon substrate 10, and is referred to as 103. In this step, the second type ion 76 is a p-type ion relative to the first type ion 74, For example, boron ions (B11). It must be noted that the second type ions 76 use the planarization layer 51 as a mask, so the edges of the ions implanted in the silicon substrate are aligned with the planarization mask layer 51; That is, the implanted second-type ions 103 and the implanted first-type ions 101 are automatically aligned. Please refer to Figure 2F, using high temperature diffusion (Diffusion) technology, for example, 800 ° C ~ 1200 ° C nitrogen environment to drive the implanted ions, and make the implanted first type ions 101 and has The implanted second-type ions 103 are driven to a depth, and the first-type well region 102 and the second-type well region 104 are formed separately, and the first-type well region 102 and the second-type well region 10 are formed. 4 is auto-alignment. So far, the auto-alignment double-well area is formed, and the surface of the silicon substrate 10 is not oxidized. Therefore, after the planarization mask layer 51 and the silicon dioxide layer 24 are removed, the silicon substrate 10 The surface is flat, that is, no step exists at the junction of the first type well area 102 and the second type well area 104, as shown in FIG. 2F. It is made according to the manufacturing method of the present invention described above The semiconductor substrate can have a flat surface, so that it can solve the exposure imaging problem of subsequent processes encountered in the conventional technology. In this preferred implementation, the first type well area is an n-type well area, and the second type well area The size of this paper is applicable to China National Standard (CNS) Α4 specification (210Χ 297mm). Please read the precautions on the back before filling out this page) Printed by the Ministry of Economic Affairs, Central Standard Falcon Bureau Employee Consumer Cooperative Μ Β7 5. Invention Description (7) The well area is a P-type well area; however, the invention is not limited to this, the The first type well area can also be a P-type well area, and the second type well area is an η-type well area. The same is true for the first type ions and the second type ions. In addition, in this preferred embodiment The sacrificial layer is a silicon nitride layer and the planarization layer is a silicon dioxide layer; however, according to the spirit of the present invention, the two layers need only be of different materials, for example, the sacrificial layer may be a silicon dioxide layer, flat The chemical conversion layer is a silicon nitride layer or a polycrystalline silicon layer; alternatively, the sacrificial layer may be a polycrystalline silicon layer, and the planarization layer is a silicon dioxide layer or a silicon nitride layer. In the first preferred embodiment described above, the first type ions and the second type ions are driven into the first type well area and the second type well area in the same high temperature diffusion step. However, the present invention is not limited to this. According to the spirit of the present invention, the first type ions and the second type ions can be drawn in separately, that is, the first type ions can be driven in the first high temperature diffusion step, and the first 2. The second type ion can be driven in at the same time by the second high temperature diffusion step. Among them, the first high temperature diffusion step can be performed before the deposition of the planarization layer, or after the deposition of the planarization layer; the next preferred embodiment will describe the manufacturing of the first high temperature diffusion step performed before the deposition of the planarization layer method. Next, referring to FIGS. 3A to 3F, a second preferred embodiment of a manufacturing method for forming an automatic alignment double-well region on a semiconductor substrate of the present invention will be described in detail. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2B, and then uses different processes to make a similar structure of the automatic alignment double-well area. In Figs. 3A to 3F, the parts similar to those in Fig. 2B are marked with the same numbers. Please refer to Figures 3Α and 2B, the second preferred embodiment proceeds to the 9th implantation ---------- ^ ------ 1Τ ------ ^ (please read the back Please pay attention to this page and then fill out this page) This paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ 297 mm) Printed by A7 __B7. _ 5. Description of the invention (8) Type I ion The steps up to the formation of the first type implanted ion 101 are the same as those of the first preferred embodiment. Next, the photoresist mask layer 60 is removed, and a first high-temperature diffusion step is performed to drive the first-type implanted ion layer 101 to form the first-type well region 105, as shown in FIG. 3B. This first high temperature diffusion step can be completed, for example, in a nitrogen atmosphere at 800 ° C to 1200 ° C. Please refer to FIG. 3C, and then use LPCVD or PECVD to deposit a planarization layer 50, such as a silicon dioxide layer. The planarization layer 50 uniformly covers and exposes the silicon nitride mask layer 34; the thickness of the surface of the silicon dioxide layer 24 can be more than the thickness of the silicon nitride mask layer 34. Please refer to FIG. 3D, and then use the chemical mechanical grinding technology to grind the surface of the structure in FIG. 3C, and use the silicon nitride mask layer 35 as the grinding etching end point, grinding away the planarization layer 50 located in the nitrogen The portion above the sand mask layer 34 is exposed until the top of the silicon nitride mask layer 34 is exposed. In this step, as shown in FIG. 3D, the remaining planarization layer (denoted as 51) is about the same height as the silicon nitride mask layer 34. Then, as shown in Fig. 3E, the nitride sand mask layer 34 is removed by a conventional wet etching method or dry plasma contact etching technique. Then, using the ion implantation technique, and using the flattening mask layer 51 as the blocking layer, the second type ion 76 is implanted, and there is no part of the flattening mask layer 51, the second type ion 76 is worn The silicon dioxide layer 24 is penetrated and implanted in the surface layer of the silicon substrate 10, and is designated 103. In this step, the second type ion 76 is, for example, boron ion 2p_ type ion. Next, please refer to Figure 3F, in a second high temperature diffusion step, install in i IIII-order n I line (please read the precautions on the back before filling in this page) This paper size is applicable to China National Standard (CNS) A4 Specifications (2! 〇 < 297mm> 301769 A7 B7 V. Description of the invention (9) For example, drive the implanted first and second type ions 105 and 103 in a nitrogen atmosphere at 800 ° C ~ 1200 ° C And form the first and second type well regions 107 and 106 respectively. So far, the double well regions are automatically aligned and formed. After removing the planarization mask layer 51 and the silicon dioxide layer 24, the silicon substrate 10 can be followed up In the same way, as described in the first preferred embodiment, the surface of the silicon substrate 10 after the formation of the double-well region is still flat. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. The invention, any person who is familiar with this skill, can make some changes and modifications without departing from the spirit and scope of the present invention, so the scope of protection of the present invention shall be deemed to be defined by the scope of the attached patent application. ^ Species Clothesline (please read the notes on the back first Then fill out this page) Ministry of Economic Affairs Bureau of Standards 11 employees consumer cooperatives printed paper scale applicable to Chinese National Standard (CNS) A4 size (210X297 mm)