TW410393B - Method of manufacture of single transistor ferroelectric memory cell using chemical-mechanical polishing - Google Patents
Method of manufacture of single transistor ferroelectric memory cell using chemical-mechanical polishing Download PDFInfo
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- TW410393B TW410393B TW087115190A TW87115190A TW410393B TW 410393 B TW410393 B TW 410393B TW 087115190 A TW087115190 A TW 087115190A TW 87115190 A TW87115190 A TW 87115190A TW 410393 B TW410393 B TW 410393B
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000005498 polishing Methods 0.000 title abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000010276 construction Methods 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract 4
- 239000010703 silicon Substances 0.000 claims abstract 4
- 230000004888 barrier function Effects 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 5
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000005553 drilling Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 7
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- -1 pt / TU Chemical compound 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Formation Of Insulating Films (AREA)
Description
410393 五、發明說明（i) 相關應用 下列申請案/專利與本發明相關：單電晶體鐵電記憶 單元及其製造方法，Serial N0· 08/81 2,759，1 997年3月 9曰申請；雙電晶體鐵電記憶單元及其製造方法，Serial No. 08/870，161 ’ 1997年6月6日申請.；淺接合鐵電記憶單 元及其製造方法，Serial No, 08/ 86 9,534，1 997年6月6 曰申請；具側面延伸pn-接合之淺接合鐵電記憶單元及其 製造方法 ’ Serial No. 08/834, 499，1 997 年4 月 4 日申 請；VLSI RAM用鐵電記憶單元及其製造方法，se.rial No. 08/870, 375 ’ 1997年6月6日申請；及其非對稱性鐵電 極性化之單電晶體鐵電記憶單元及其製造方法，Seriai
No. 08/905, 380, 1997 年4 月 4 日申請。 發明領域 本發明係關於使用於非揮發性記憶體之鐵電薄膜，特別 是使用化學-機械研磨製造該類記憶體之製程。 發明背景 已知的鐵電隨機存取記憶體（FRAM)使用單一電晶體及單 一電容來建造。電容一般是以兩導電電極夾住一薄鐵電膜 製成’該電極通常使用釭或合金。此類記憶體電路配置之 讀/寫順序類似於傳統動態隨機存取記憶體，但FRAM不需 資料更新。然而’已知的心龍於鐵電電容會發生疲勞問 題’疲勞是因可轉換極性化（儲存非揮發性電荷）會隨著轉 換擔環次數的增加而減少所導致，在本發明中，"轉換循 環"為記憶體中消除與寫入脈衝之總和。
C:\Program F iIes\Patent\54957. ptd 第5頁 410393 五、發明說明（2) -- 上述美國專利可解決上述問題，然而，當時之專利使用 包含傳統钱刻與研磨的冗記憶單元之製造方法，雖然依此 種方法所製造的記憶裝置較當時已知技藝所製造者為佳， 但會因電容的·導通·電極所殘留金.屬微魆污染FE材料與周圍 物—造產生問題。此外H薄遍;之乾式^刻會 造成該薄膜之特性的劣化。由屬微粒會造^成短路問題，必 須將明1上枚裹j間隔開來並且維持一定的尺寸，為能使 其中的電容尺寸夠大，本發明提供一消除上述問題的方 法0 發明概述 本發明之建造單電晶體鐵電記億（FEM)單元方法包含： 準備建造FEM閘極單元之晶圓；&晶圓上形成閉極、源極 ，汲極區域’·於結構上以等於FEM閘極單元之底部電極特 疋厚度的預設厚度形成氮化物層；於結樽上形成第一絕緣 層；化學-機械研磨第一絕緣層至其頂部表面與氮化物層 之頂部平整；形成FEM單元之底部電極；及化學-機械研磨 底部電極至其頂部表面與第一絕緣層之頂部表面平整。依 照FEM單το之特定最終配置，形成附加層並予以研磨。 本發明的目的之一為製造一沒有因殘留金屬微粒導致短 路疑慮的FEM單元。 本發明的另一目的為提供—不具因乾蝕刻而造成電氣特 性劣化之FEM單元。 本發明尚有一目的為提供一具非常小型電容之FEM單 元。
C:\Program Files\Patent\54957.ptd 第6頁 五、發明說明（3) 與說明而變為 上述以及其他$ s 顯而易見。 目的經由後續的參考圖例 π , 圖例說明 圖1-8表示根據本發明 連續步驟。 货月之形成早電晶體鐵電記憶單元的 圖9 -12表示根據本發明 步驟。 我月之形成FEM早兀另一方法的連續 圖13-16表示根據本發明之形成剛單元的第三種方法。 u 較佳具體實施例詳述 (FEM)單參亓考-基材2〇為於其上欲形成電晶體鐵電記憶 方法已揭示於前：專述並C單元製造 化學氣相沈積(CVD)以及附生方法之規格。夕不同的摻雜、 在較佳具體實施例中，基材2◦為p型，以離子植入 散形成p型井，該裝置以區域氧化（L〇c〇s)方法 溝、 離方法予以隔離，然後全面平坦化。閥值電壓以適孓的： 子植入，以調整，一傳統11型通道記憶電晶體需要丨〇1? ions/cm3至10ls i〇ns/cm3量級的通道摻雜物，而p型基 穆雜猶度非常低* 為1 015 i ons/cm3量級。 較佳具體實知例之下一步驟為閘極氧化，其中於將成為 閘極區域2 2上熱成長二氧化矽（S i 〇2)之薄層2 3至小於 1 Onm的厚度’然後沈積一多晶矽層24，並摻雜所需的極 性’於本具體實施例中為n+型。蝕刻多晶矽層24成所需的
C:\Prograra Files\Patent\54957. ptd 第7頁 410393 五、發明說明（4) --：— 形狀，、並形成Si〇2閘極側壁26，植入適當的離子以形成源 極區域28與汲極區域3〇，該離子對於這些區域提供適當的 電氣特性。 由現在參照圖2，沈積一氮化物層32到達1〇_至3〇111〇的厚 义，厚度等於之後成為FEM單元之底部電極的特定厚度， 氮化物矽（SisN4)或氮化硼（BN)皆可用於此一步驟。如圖中 第一絕緣層34之Si〇2層，沈積至其厚度大於多晶矽層24的 厚度。第一絕緣層34 ’如TE0S，可以CVD方法沈積。 現在參照圖3，化學-機械研磨（CMP)該結構以除去第一 絕緣層t所有高於氮化—物層的部份，並形成如圖3之結 構’其中第一絕緣層與氮化物層為平整。CMP使晶圓的整 體表面平坦度在5 %的均一性以内’而使殘留微粒不會停留 於不希望有微粒停留之結構的部份β 早方向银刻位於多晶石夕層24上的氮化物層（圖4)以露出 多晶石夕，沈積於薄層36之材料最終會形成FEM單元的底部 電極’該材料可為鉑（pt)，障壁層上有鉑，如：pt/TU、 Pt/TaSiN、Pt/TiSiN、或Pt/Ir02。對圖4 之結構實施cjjfp 製程’而除去薄層36位於第一絕緣層與氮化物層上的部 份，形成FEM底部電極38.。如前所述’底部電極的厚度由 沈積於多晶矽層24上的氮化物層34厚度所控制。 使用CMP製程對於製作單電晶體MFM0S非揮發性記憶單元 特別有利，因為CMP製程可整平底部M0S結構，使鐵電部份 與頂部電極部份形成非常平坦的表面。因此，凝朦、迴旋 所製成的鐵電薄膜可用於建造該裝置，可使鐵電薄膜能連
C:\ProgramFiles\Patent\54957.ptd 第 8 頁 410393 五、發明說明（5) 續地覆蓋於整個晶圓。MFM電容區域則定義為僅有FEM單元 之頂部電極而去除個別裝置的尺寸限制。 為瞭.解熟知此項技藝者所習知的CMP製程，於該製造程 中使用研磨平台，該研磨平台包含迴轉墊及由迴轉墊上方 的支持架所支撐不同建造狀態之晶圓。將晶圓帶向迴轉墊 時’庄入一般為銘基或發基毁液的研磨介質。當製程的機 械部份磨平表面時，漿液與晶圓的化學反應使得二氧化矽 軟化。使用CMP製造程一般可使空白晶圓獲得5 %均一性， 而對於部份建造晶圓亦可達到5%均一性，而部份建造晶圓 可製造較有效率的裝置，並且有較少不良裝置的製造成 果。 現在參照圖6，沈積一 F E層4 0，因為底部電極經過化學一 機械研磨後，結構變得平坦，鐵電薄膜可用任何常用的技 術來製作，如：CVD、濺射、凝膠迴旋塗布等。沈積一最 終形成FEM頂部電極之薄層42，該材料與使用於底部電極 者相同或類似，並可使用與底部電極相同的方法沈積。 如圖7，蝕刻薄層42形成於頂部電極44，此—特別蝕刻製 程可為乾蝕刻，因為此處沒有因薄層42保持於"層4〇頂 所帶來的外來微粒問題或困擾。 ' ° 如圖8所示之最終裝置包含一般以s丨&形成之第二絕 層46，當安置第二絕緣層46後，形成適當的孔洞穿·過第一 絕緣層與第二絕緣層以及FE層，以金屬化包含源極電極 48、閘極電極5〇、汲極電極52之完成結構。 形成上述裝置的另一種方法為於多晶矽層24摻雜後，沈
C:\Program F i1es\Patent\54957, ptd 第 Θ 頁
410393 五、發明說明（6) 積底部電極用金屬，且可附或不附有障壁金屬，此一情況 下，可同時蝕刻底部電極與多晶矽，而消除部份中間 驟。 現在參照圖9說明前述方法之變化，此一特殊變化由圖5 所示之結構開始，於結構中加入一内擴散障壁層6 〇，然後 予以银刻以露出底部電極3 8。可於第一絕緣層3 4上用C V I) 沈積障壁層60，並使用如Ti02或丁％05之材料，另外，可放 置遮罩於底部彙極38之上再置入内擴散障壁層，然後剝除 遮罩。 現在參照圖10 ’如前所述先沈積FE層62，然後沈積薄層 64於最終會形成頂部電極的⑽層“之上。 現在參照圖11 ’為經CMP製程後之結構及連續f e層62與 頂部電極6 6，再參照圖1 2，沈積第二絕緣層8 8，然後於結 構中形成適當的孔洞容許結構之金屬化，藉以形成源極電 極48、閘極電極50、沒極電極52 ,此一建造提供FE電容部 伤與Μ 0 S閘極部份不同比例。 本發明之第三具體實施例亦由圖5所示之結構開始，但 包含較厚的第一絕緣層70 ’該層沈積至使得頂部表面7〇a 的厚度到達F EM單元頂部電極之上表面的頂點特定高度， 再置入絕緣層，並利用CMP使表面磨平至所需的厚度，蝕 刻底部電極上方的區域，或可遮蔽底部電極，置入絕緣 層，研磨，然後剝除遮罩。 現在參照圖14，沈積F E層7 2，然後沈積將形成頂部電極 之薄層74 ’如圖1 5所示，.利用CMP研磨結構至頂部電極7 6
C:\Program Files\Patent\54957. ptd 第10頁 410393 發明說明C7) 之上表 連續地 然後於 形成源 應當 裝置積 用鐵電 以上 必須瞭 圍之精 面的水平面 覆蓋整個晶 結構中形成 極電極48、 認知本發明 體電路製作 材料為電容 說明本發明 解有許多修 神與範疇。 。在此特殊具體實施例中，ρ» E層7 2並非 圓’再參照圖1 6 ’沈積第二絕緣層7 8， 適冨的孔/同以容許結構之金屬化，藉以 閘極電極5 0、汲極電極5 2。 為形成非揮發性記憶體或其他可程式化 方法的一部份’本發明可適用於任何使 或其他裝置之半導體材料技術。 之具體實施例以及其中許多變化，然而 正與變化並不會脫離之後的申請專利範
C:\Program Fi1es\Patent\54957' ptd
第11頁
Claims (1)
- 410393 六、申請專利範圍 1. 一種製作單電晶體鐵電記憶（FEM)單元之方法，包 括： 準備供製作FEM閘極單元用矽基材； 在基材上形成閘極S i 〇2層以形成閘極區域； 在閘極S i 〇2層上形成多晶石夕層； 將多晶石夕層摻雜成至所需極性； 蝕刻多晶矽層以形成閘極電極； 形成Si 02閘極侧壁； 於石夕基材中植入源極區域及汲極區域所需之離子； 擴散破基材中之植入離子以形成源極區域及汲極區 域； 於結構上形成氮化物層至預設厚度，該厚度相當於 FEM閘極單元之底部電極的特定厚度； 於結構上形成第一 S i 〇2絕緣層； 化學-機械研磨第一Si〇2絕緣層，使其頂部表面與氮 化物層之頂部平整； 遮蔽並蝕刻閘極區域上的氮化物層； 形成FEM單元之底部電極； 化學-機械研磨底部電極，使其頂部表面與第—Si 絕緣層之頂部表面平整β J.Λ?專利範圍第1項之方法’進-步包括：形成覆 =結構頂部之FE層；於肫層之上形成頂部電極；於問極 Si側：=_項部電極；於結構上形成第二叫 、a ' 細鑽孔形成源極電極、閘極電極與汲極C:\Program Files\Patent\54957. ptd 第12頁410393 六、申請專利範圍 電極用孔洞，對結構實施金屬化以形成源極電極、閘極電 極與汲極電極。 3. 如申請專利範圍苐1項之方法，進一步包括：於第一 絕緣層上沈積一内擴散障壁層；蝕刻内擴散障壁層以露出 底部FEM單元電極；形成FE層；於^層上形成頂部電極； 化學-機械研磨頂部電極’使其頂部表面與？£層之頂部表 面平整；於結構上形成第二絕緣層；對結構實施鑽孔形成 源極電極、、閘極電極舆汲極電極用孔洞；及對結構實施金 屬化以形成源極電極、閘極電極與汲極電極。 4. 如申請專利範圍第丨項之方法，其一步包括：於第一 絕緣層上沈積一内擴散障壁層；蝕刻内擴散障壁層以露出 底部FEM單元電極；形成FE層；於冗層上形成頂部電極； 化學-機械研磨頂部電極與FE層，使其頂部表面與内擴散 障壁層之頂部表面平整；於結構上形成第二絕緣層；對結 構實施鑽孔形成源極電極、閘極電極與汲極電極用孔洞； 及對結構實施金屬化以形成源極電極、閘極電極與汲極 極。 5. —種製作單電晶體鐵電記憶（FEM)單元之方法， 括： 準備供製作FEM閘極單元用矽基材； 在石夕基材上形成閘極、源極及汲極區域； 於結構上形成氮化物層至預設厚度，該厚度相當於 FEM閘極單元之底部電極的特定厚度； 、 於結構上形成第一絕緣層；C:\Program Files\Patent\54957. ptd 第13頁 410393 六、申請專利範圍 化學-機械研磨第-絕緣層，使其頂 層之頂部平整； 回-、氮化物 形成FEM單元之底部電極； 化學-機械研磨底部電極，使其頂部表面盥 層之頂部表面平整》 田/、第-'絕緣 6.如申請專利範圍第5項之方法，進—步 於結構頂部之FE層，於FE層之上形成 :成越 =第二絕緣層4結構實施鑽孔形成源】J極=構上 ，及極電極两孔洞；對結構實施金屬化 ：極電 極、閘極電極與汲極電極。 源極電 如申請專利範圍第5項之.方法，進—步包 絕緣層上沈積一内擴散障壁層；蝕刻内 ；第一 底聰Μ單元電極；形成FE層；㈣層上形散^頂壁層以露出 化學-機械研磨頂部電極，使其頂部表面與fe芦卩， 面平整；於結構上形成第二絕緣層；對处構H之頂4表 源極電極、開極電極與汲極電極用孔洞；a 形成 屬化以形成源極電極、閘極電極與汲極電極。’、只施金 8.如申請專利範圍第5項之方法，進—步包括· 絕緣層上沈積一内擴散障壁層；蝕刻内擴散壁/第^一 底部F料元電極；形成FE層；刪層上形成曰以路出 :學-機械研磨頂部電極與心層，使 ：二散 障壁層之頂部表面平整；於結構上形成第二絕緣層内= 電極、閘極電極與w極用孔洞了 及對、“薄…屬化以形成源極電極、間極電極與沒極電C:\ProgramFiles\Patent\54957.ptd 苐 14 頁 410393 六、申請專利範圍 極。 画__:11丨 C:\Program Files\Patent\54957. ptd 第15頁
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|---|---|---|---|
| US08/984,789 US5907762A (en) | 1997-12-04 | 1997-12-04 | Method of manufacture of single transistor ferroelectric memory cell using chemical-mechanical polishing |
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| US (1) | US5907762A (zh) |
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| KR (1) | KR100277307B1 (zh) |
| DE (1) | DE69822593T2 (zh) |
| TW (1) | TW410393B (zh) |
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| US7608926B2 (en) * | 2004-01-29 | 2009-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nonvolatile semiconductor memory device |
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| US6093575A (en) * | 1996-09-04 | 2000-07-25 | Nippon Steel Corporation | Semiconductor device and production method of a semiconductor device having a capacitor |
| US6191441B1 (en) * | 1997-10-28 | 2001-02-20 | Fujitsu Limited | Ferroelectric memory device and its drive method |
| US6072711A (en) * | 1997-12-12 | 2000-06-06 | Lg Semicon Co., Ltd. | Ferroelectric memory device without a separate cell plate line and method of making the same |
| US5998225A (en) * | 1997-12-17 | 1999-12-07 | Texas Instruments Incorporated | Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K DRAMs using disposable-oxide processing |
| JP2000349249A (ja) * | 1999-06-08 | 2000-12-15 | Oki Electric Ind Co Ltd | 半導体記憶装置の製造方法 |
| US6603161B2 (en) * | 2000-03-10 | 2003-08-05 | Kabushiki Kaisha Toshiba | Semiconductor device having ferroelectric capacitor and method for manufacturing the same |
| JP4938921B2 (ja) * | 2000-03-16 | 2012-05-23 | 康夫 垂井 | トランジスタ型強誘電体不揮発性記憶素子 |
| JP4523115B2 (ja) * | 2000-05-02 | 2010-08-11 | 富士通株式会社 | 強誘電体メモリ装置及びその製造方法 |
| US20020109166A1 (en) * | 2001-02-13 | 2002-08-15 | Hsu Sheng Teng | MFMOS/MFMS non-volatile memory transistors and method of making same |
| US6566148B2 (en) * | 2001-08-13 | 2003-05-20 | Sharp Laboratories Of America, Inc. | Method of making a ferroelectric memory transistor |
| US6673664B2 (en) * | 2001-10-16 | 2004-01-06 | Sharp Laboratories Of America, Inc. | Method of making a self-aligned ferroelectric memory transistor |
| US6531325B1 (en) * | 2002-06-04 | 2003-03-11 | Sharp Laboratories Of America, Inc. | Memory transistor and method of fabricating same |
| US6716691B1 (en) | 2003-06-25 | 2004-04-06 | Sharp Laboratories Of America, Inc. | Self-aligned shallow trench isolation process having improved polysilicon gate thickness control |
| GB2408644B (en) * | 2003-11-26 | 2007-04-25 | Wolfson Ltd | Amplifier |
| KR100605584B1 (ko) * | 2004-12-28 | 2006-07-31 | 주식회사 하이닉스반도체 | 스크래치가 방지되는 반도체장치의 제조 방법 |
| US10050143B2 (en) * | 2016-09-13 | 2018-08-14 | International Business Machines Corporation | Integrated ferroelectric capacitor/ field effect transistor structure |
| US10937783B2 (en) | 2016-11-29 | 2021-03-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US10229921B2 (en) * | 2017-02-03 | 2019-03-12 | International Business Machines Corporation | Structure featuring ferroelectric capacitance in interconnect level for steep sub-threshold complementary metal oxide semiconductor transistors |
| US11901400B2 (en) * | 2019-03-29 | 2024-02-13 | Intel Corporation | MFM capacitor and process for forming such |
| US11342343B2 (en) * | 2020-01-09 | 2022-05-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method for manufacturing the same |
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| US3832700A (en) * | 1973-04-24 | 1974-08-27 | Westinghouse Electric Corp | Ferroelectric memory device |
| US4419809A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Fabrication process of sub-micrometer channel length MOSFETs |
| US5192704A (en) * | 1989-06-30 | 1993-03-09 | Texas Instruments Incorporated | Method and apparatus for a filament channel pass gate ferroelectric capacitor memory cell |
| US5070029A (en) * | 1989-10-30 | 1991-12-03 | Motorola, Inc. | Semiconductor process using selective deposition |
| JP2723386B2 (ja) * | 1991-07-02 | 1998-03-09 | シャープ株式会社 | 不揮発性ランダムアクセスメモリ |
| US5384729A (en) * | 1991-10-28 | 1995-01-24 | Rohm Co., Ltd. | Semiconductor storage device having ferroelectric film |
| JP3207227B2 (ja) * | 1991-11-08 | 2001-09-10 | ローム株式会社 | 不揮発性半導体記憶装置 |
| US5303182A (en) * | 1991-11-08 | 1994-04-12 | Rohm Co., Ltd. | Nonvolatile semiconductor memory utilizing a ferroelectric film |
| JP3264506B2 (ja) * | 1991-11-18 | 2002-03-11 | ローム株式会社 | 強誘電体不揮発性記憶装置 |
| FR2688090B1 (fr) * | 1992-02-27 | 1994-04-08 | Commissariat A Energie Atomique | Cellule memoire non volatile du type metal-ferroelectrique semi-conducteur. |
| US5431958A (en) * | 1992-03-09 | 1995-07-11 | Sharp Kabushiki Kaisha | Metalorganic chemical vapor deposition of ferroelectric thin films |
| JP2921812B2 (ja) * | 1992-12-24 | 1999-07-19 | シャープ株式会社 | 不揮発性半導体記憶装置 |
| US5392189A (en) * | 1993-04-02 | 1995-02-21 | Micron Semiconductor, Inc. | Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same |
| JP3113173B2 (ja) * | 1995-06-05 | 2000-11-27 | シャープ株式会社 | 不揮発性ランダムアクセスメモリ及びその製造方法 |
| JP3281839B2 (ja) * | 1997-06-16 | 2002-05-13 | 三洋電機株式会社 | 誘電体メモリおよびその製造方法 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7608926B2 (en) * | 2004-01-29 | 2009-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nonvolatile semiconductor memory device |
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|---|---|
| EP0923117A1 (en) | 1999-06-16 |
| DE69822593T2 (de) | 2005-02-03 |
| KR19990062530A (ko) | 1999-07-26 |
| US5907762A (en) | 1999-05-25 |
| KR100277307B1 (ko) | 2001-02-01 |
| EP0923117B1 (en) | 2004-03-24 |
| DE69822593D1 (de) | 2004-04-29 |
| JP3664467B2 (ja) | 2005-06-29 |
| JPH11317502A (ja) | 1999-11-16 |
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