TW468274B - Manufacturing method of bottom storage node - Google Patents

Abstract

The present invention provides a kind of method for manufacturing bottom storage node, in which the manufacturing method contains the followings: (1) providing a substrate, in which at least one of the first conducting layer is contained on the substrate surface; (2) forming a dielectric layer on the substrate to completely cover the conducting layer; (3) forming a contact hole in the dielectric layer to reach the conducting layer; (4) forming the second conducting layer on the dielectric layer surface so as to fill up the contact hole; (5) sequentially forming a metal silicide layer and the third conducting layer on the second conducting layer; (6) forming a patterned photoresist layer on the surface of the third conducting layer so as to define the pattern and position of the bottom storage node; (7) etching the third conducting layer, the metal silicide layer and the second conducting layer, which are not covered by the photoresist layer, until reaching the dielectric layer surface; (8) removing the photoresist layer; and (9) wet etching the metal silicide layer to complete the manufacture of fin-shaped bottom storage node.

Description

468 274 V. Description of the invention (1) Field of the invention The present invention provides a method for making the surface area of a lower layer storage electrode on the surface of a semiconductor wafer, and particularly a method and method that can increase the surface area of the lower layer storage electrode. -— Background Description Dynamic random access memory (DRAM) is an e DRAM that consists of a large number of memory cells. Each memory cell contains a metal oxide half. A metal oxide semiconductor field effect transistor (MOSFET) is used as a pass transistor and a capacitor to store charge. The capacitor is electrically connected to the conductive material in the node contact through the lower storage node and a one-bit access path to the drain of the MOSFET. When voltage is applied to one of the electrode layers, the other electrode layer can sense a corresponding charge value, thereby achieving the purpose of memorizing or outputting data. Capacitors are important components used by dynamic random access memory to store signals. The more charge a DRAM capacitor can store, the less likely it is to be affected when reading data from the sense amplifier, resulting in defects such as soft errors, and it can also significantly reduce the recharge of charges on it.

Page 4 274 V. Description of the invention (2) Supplementary frequency. At present, the ability to increase the charge storage capacity of a capacitor is generally developed in two main directions. The first is to improve the capacitor dielectric layer of the capacitor element between the storage node below the capacitor element and the upper field electrode. The second is to increase the area of the electric container, especially the surface area of the lower storage electrode and the upper field electrode, to increase the amount of charge stored in the capacitor. Capacitor Is dielectrics are mostly made of 0N0 (oxide / nitride / oxide) composite structures. 'This composite structure not only effectively reduces the thickness of the single cell dielectric layer (only about 5nm), but also provides a Good dielectric constant, which in turn increases the number of stored charges per unit surface area of the capacitor. "This application is a technique for increasing the surface area of a capacitor. Please refer to FIG. 1 to FIG. 3 ′. FIG. 1 to FIG. 3 are schematic cross-sectional flow diagrams of a conventional process for fabricating a DRAM stacked capacitor (STC) single cell (ceii) element. As shown in FIG. 1, a conventional method for manufacturing a stacked capacitor cell is to first form a field oxide 14 on a silicon substrate 12 on the surface of a semiconductor wafer 10 by using a local oxidation of silicon (LOCOS) method. Then, an insulating layer 16 is deposited to cover the field oxide layer 14, and the insulating layer 16 further includes a pair of correspondingly doped poly-silicon bit lines 18. Next, a non-doped neutral silicate glass (NSG) layer 20 is deposited on the insulating layer 16 for isolation protection. Subsequently, a photoresist layer 22 is coated on the NSG layer 20, and a circular hole 23 is etched in the photoresist layer 22 to reach the surface of the NSG layer 20 under the photoresist layer 22.

4 6 8 27 4 5 'Explanation (3) plane to define the position of a contact hole 24. Then, as shown in FIG. 2, a contact hole 24 is vertically etched on the surface of the semiconductor wafer 10 by using an anisotropic name, and then the photoresist layer * 2 2 is removed, and a chemical vapor deposition method ( Ch ^ emica 1 va ρ οr deposition (CVD) and etch back method will form a silicon dioxide sidewall 26 with a thickness of about 1000 A on the sidewall surface of the contact hole 24. At this time, the thickness of the NSG layer 20 is also reduced to about 1,000 A from the first 2300 A deposited with the reaction such as etch back. Subsequently, as shown in FIG. 3, a polycrystalline silicon layer (not shown) is deposited on the surface of the semiconductor wafer 10 by the CVD method again, and phosphorus ions are doped into the polycrystalline silicon layer as the polycrystalline silicon layer deposition reaction proceeds. In order to uniformly form a doped polycrystalline silicon layer over the contact hole 24 and the NSG layer 20. Then, the unnecessary doped polycrystalline silicon layer is removed by lithography and etching to form a mushroom-shaped lower storage electrode 28. In addition, the doped polycrystalline silicon layer can be formed by implanting dopants such as phosphorus into the polycrystalline silicon layer using an ion implantation method. Finally, a single cell dielectric layer 30 of a 0N0 composite structure and an upper field electrode 32 are sequentially formed on the surface of the lower storage electrode 28. First, a CVD method is used to directly deposit a nitride layer (not shown) with a thickness of about 5 nm on the surface of the lower storage electrode 28. Then, a high-temperature vapor of 920 t is passed into the nitride layer for one time.

468 274 V. Description of the invention (4) The re-oxidized reaction causes the surface reaction of the nitrided layer to form an oxide layer with a thickness of about 2 nro. This is what is added to the surface of the polycrystalline silicon layer of the original lower storage electrode 28. A layer of original gasification layer (native 〇xide), a single cell dielectric layer go β of a composite structure of 10N0 can be obtained, and then a polycrystalline silicon layer is deposited again by CVD method as an upper field electrode 3 2 to complete the preparation A typical stacked capacitor unit cell. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for manufacturing a new storage electrode under a capacitor element. Another object of the present invention is to provide a method for manufacturing a fin-type lower storage electrode, which can effectively increase the surface of the lower storage electrode, so that the 0 N0 dielectric layer and the upper field electrode that are subsequently deposited are also the same. The ground has a large surface area to accumulate charges. The method for manufacturing a lower storage node according to the present invention includes the following steps: (1) providing a substrate 'and the surface of the substrate including at least a first conductive layer' (2) forming a dielectric on the substrate Layer and completely covering the conductive layer, (3) performing a yellow light and money engraving process to form a contact hole in the dielectric layer to reach the conductive surface; (4) forming a surface on the surface of the dielectric surface; The second conductive layer fills the contact hole. (5) A metal silicide layer and a third conductive layer are sequentially formed on the second conductive layer. (6)

4 6 8 274 V. Description of the invention (5) A patterned photoresist layer is formed on the surface of the third conductive layer to define the pattern and position of the underlying storage electrode, and (7) the etching is not covered by the photoresist layer. The third conductive layer, the metal silicide layer, and the second conductive layer up to the surface of the dielectric layer, (8) remove the photoresist layer and (9) wet metal etch the metal formation layer to complete the -fin-shaped lower layer storage Fabrication of electrodes. -Because the present invention uses the RC A standard cleaning solution to selectively etch the underlying storage electrode structure formed by stacking the doped polycrystalline silicon layer and the metal silicide layer alternately, thereby forming a fin-type underlying storage In addition, the surface of the lower storage electrode can be further subjected to an HSG process to effectively increase the surface area of the lower storage electrode, increase the capacitance of the STC unit cell, and then significantly reduce the replenishment frequency of the STC unit cell. Detailed description of the invention Please refer to FIG. 4 to FIG. 7, which are schematic cross-sectional views of manufacturing a fin-stacked lower storage electrode element according to the present invention. First, as shown in FIG. 4, a field oxide layer 44 and a doped region 60 isolated by the field oxide layer 44 are sequentially formed on the silicon substrate 42 on the surface of the semiconductor wafer 50. The doped region 60 may be a drain or a source of an M 0S transistor. In another embodiment of the present invention, the stone evening substrate 42 may be a silicon-on-insulator (SOI) substrate. A dielectric layer 46 having a thickness of several thousands angstroms is then deposited on the surface of the silicon substrate 42 to completely cover the doped region 60. The dielectric layer 46 may be silicon dioxide, borophosphosilicate glass (BPSG), or stone-filled glass.

468274 V. Description of the invention (6) Glass (phosphosilicate glass, PSG) or other similar low dielectric constant materials. After the deposition of the dielectric layer 46, a chemical mechanical polishing process (CMP) can be optionally performed to obtain a flattened surface profile. Then, a yellow light and money engraving process is performed to form a contact hole 55 in the dielectric layer 46 to reach the surface of the doped region 6-0. Next, a low-pressure chemical vapor deposition (LPCVD) process is performed to uniformly deposit a polysilicon (Polysilicon) layer 62 on the dielectric layer 46 with a thickness of about 1000 A. The conditions of the LPCVD process are as follows: silane (Si H4) is used as the reaction gas, the temperature is set between 575 and 650 ° C, and the pressure is about 0.3 to 0.6 Torr. Since the resistivity (r e s s t i v i t y) of the polycrystalline silicon layer 62 deposited by the LPCVD * method is high ', a doping process must be performed on the polycrystalline silicon layer 62 to reduce its resistivity. The doping method is to introduce a dopant-containing reaction gas, such as phosphine (PH3), into the CVD reactor, so that while depositing the polycrystalline silicon layer 62, the impurity can be changed in-situ. ° Note that the polycrystalline stone layer 6 2 needs to fill the contact hole 5 5. Subsequently, a silicide CVD process is performed to deposit a silicide metal layer 64 on the surface of the polycrystalline silicon layer 62 with a thickness of about 1500 to 2000 people. The silicide metal layer 64 may be a silicide town, titanium sulfide, molybdenum silicide, tantalum silicide, or cobalt silicide, etc. Among them, tungsten silicide is preferred. Compared with other metal silicides, the silicide town has the following advantages ’

4 6 8 274 V. Description of the invention (7) Tungsten silicide is selected in the preferred embodiment of the present invention: (1) the bonding force with the polycrystalline silicon surface is better '(2) the problem of no peeling occurs, and ( 3) The reaction temperature is low in the formation of tungsten carbide. The typical tungsten chemical vapor deposition process of Shixihua uses tungsten hexafluoride (WF6) and silyl-alkane as reaction gases. At a temperature of about 300-400 ° C, The pressure is carried out at about 0,3 to l.OTorr. Then, the same L PC VD process as that of the deposited polycrystalline silicon layer 62 is performed to deposit a doped polycrystalline silicon layer 66 with a thickness of about 1000 A on the surface of the tungsten silicide layer 64. Then, as shown in FIG. 5, a photoresist layer 68 is formed on the surface of the doped polycrystalline silicon layer 66 after exposure and development to define the pattern and position of the lower storage electrode. Next, a dry etching process is performed, and the photoresist layer 68 is used as an etching mask, and the polycrystalline silicon layer 66, the petrified metal layer 64, and the polycrystalline silicon layer 62 are etched to the last name until the surface of the dielectric layer 46. Then, the photoresist layer 68 'is removed to form a stacked structure 70. In order to reduce the resistivity of the silicided metal layer 64, a rapid thermal annealing (RTA) process can be optionally performed at this time to reduce the resistivity of the petrified metal layer 64 to about 70 / zQ-cm or less. It should be noted that 'in order to avoid affecting the junction depth of the doped region 60', the heating rate and heating temperature of the rapid tempering process must be strictly controlled. Next, as shown in Figure 6, the silicon is silicified. The layer 64 is subjected to a wet-axis engraving process to form a groove 71 in the stacked structure 70 and a fin-shaped stacked structure 72. Method for wet etching metal silicide layer 64 can use RCA standard

Page 10 46 8 274 V. Description of the invention (8) Cleaning solution, or other similar cleaning solution that can selectively etch metal silicide layer 64. More specifically, 'when this wet etching process is performed, the semiconductor wafer 50 is immersed in a mixed solution of HC 1: H 2 02: H 20 volume ratio = 1: 1: 6 (also commonly referred to as SC-2 solution), Perform immersion cleaning for about several seconds to several minutes at a temperature of about 25 to 70 ° C to form a fin-like stacked structure 72. Then, an LPCVD process is further performed to deposit an amorphous silicon layer 73 on the surface of the fin-like stacked structure 72 with a thickness of about 500 A. The conditions of the LPCVD process are as follows: silicon dioxide (si lane, Si is used as the reaction gas, the temperature is set between 575 and 650 ° C, and the pressure is about 0.3 to 0.6 T 〇rr 〇 followed by As shown in FIG. 7, the amorphous silicon layer 73 is removed from the surface of the dielectric layer 46 except for the fin-like stacked structure 7 2. The method of removing the amorphous silicon layer 73 from the surface of the dielectric layer 46 is to use a dry etching. The process directly removes the amorphous silicon layer 7 3 on the surface of the dielectric layer 46. Then, an ultra high vacuum chemical vapor deposition (UHV CVD) process is performed, using a Kishiyuin (Si H4) And dichlorosilane (SiH2Cl2) is a reactive gas, which is uniformly deposited on the amorphous stone layer at a pressure of less than 1 Torr and a temperature of 5500 to 800 ° C. 73 A polycrystalline silicon layer 75 having a hemi-spherical grain (HSG) structure is formed on the surface of the surface, and a fin-shaped stacked lower storage electrode 74 is completed. The thickness of the polycrystalline silicon layer 75 is about 500 A. Then Perform an annealing process to make the lower storage electrode in an inert environment Atoms in the South Concentration Wall in 74 diffuse into the polycrystalline stone layer 75 and store the lower layer

Page 11 468274 V. Description of the invention (9) The amorphous material of the electrode 74 is converted into a polycrystalline silicon material. Please refer to FIG. 8, which is a schematic cross-sectional view of another embodiment of the present invention. As shown in FIG. 8, the fin-shaped stacked lower storage electrode 74 of the present invention may also be composed of a three-layer doped polycrystalline silicon layer 6 2, 6 6, 8 2 and two metal silicide layers 6 4 a, 6 4 b. However, the present invention is not limited to the above-mentioned embodiments, and a plurality of metal silicide layers and a plurality of layers of doped polycrystalline silicon layers are alternately stacked to form the fin-like lower storage electrodes of the present invention. Compared with the conventional manufacturing process of the lower storage electrode, the present invention uses the RCA standard cleaning solution to selectively etch the lower storage electrode structure alternately stacked from the doped polycrystalline silicon layer and the metal silicide layer to form a fin-like structure. (Fin-type) lower storage electrode. In addition, the surface of the lower storage electrode can be implemented with a standard HSG process to effectively increase the surface area of the lower storage electrode, increase the capacitance of the STC cell element, and then significantly reduce the STC cell element. Replenishment frequency. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 12 i 6 8 27 4 Brief description of the diagrams Brief description of the diagrams Figures 1 to 3 are schematic cross-sectional views of the manufacturing method of a conventional DRAM stacked capacitor unit cell. 4 to 7 are schematic cross-sectional views illustrating a method for manufacturing a fin-shaped stacked capacitor unit cell according to the present invention. FIG. 8 is a schematic cross-sectional view of another embodiment of the present invention. Symbols of the drawings 10 semiconductor wafer 14 field oxide layer 18 bit lines 2 2 photoresist layer 24 contact hole 28 lower storage electricity 3 2 upper field electrode 44 field oxide layer 5 semiconductor wafer 60 doped regions 64, 64a, 64b Jin Guangshi Xihua layer 68 Photoresist layer 71 Groove 7 3 Amorphous silicon layer 12 Silicon substrate 16 Insulation layer 20 NSG layer 2 3 Hole 26 Side wall sub-electrode 30 Cell dielectric layer 42 Silicon substrate 46 Dielectric layer 5 5 Contact Hole 6 2 polycrystalline silicon layer 66 doped polycrystalline silicon layer 70 stacked structure 7 2 fin-like stacked structure 7 4 fin-like stacked lower storage electrode

P. 13 ^ G 8 274

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Claims (1)

6 8 274 Amendment and Supplementary VI. Patent Application Scope 1. A method for manufacturing a lower storage electrode, the method includes the following steps: / Provide a substrate, the surface of which comprises at least a first conductive layer; 1 on the substrate Forming a dielectric layer, and the dielectric layer completely covering the conductive layer; performing a yellow light and etching process, forming a contact hole in the dielectric layer, and the contact hole reaching the conductive layer; and in the dielectric A second conductive layer is formed on the surface of the layer, and the second conductive layer fills the contact hole; a metal silicide layer and a third conductive layer are sequentially formed on the second conductive layer; A photoresist layer is formed on the surface of the third conductive layer, and the photoresist layer defines the pattern and position of the underlying storage electrode: the third conductive layer, the metal silicide layer, and the first storage layer are not covered by the photoresist layer. Two conductive layers up to the surface of the dielectric layer; removing the photoresist layer; and engraving the metal petrified layer to form a fin-like (fi η -1 ype) lower layer. The storage electrode. 2. The manufacturing method according to item 1 of the patent application scope, wherein the first conductive layer is a drain or a source of a MOS transistor. _ 3. The manufacturing method of item 1 in the scope of patent application, wherein the metal is silicified I Circle Page 15 -8 27 4 6. Scope of Patent Application The layer system is composed of tungsten silicide (WSung) or titanium silicide (TiSix). =, If the scope of the patent application is poor ^ ^ 3 method, wherein the thickness of the metal silicide layer is between about 1500 and 2000 angstroms (angstrom, A). t is the eleventh of the scope of application of the invention-manufacturing-a method, wherein the second conductive ', doped polycrystalline silicon (doped ρο 1 ys i 1 i con) is composed. The layer system is the method of applying the scope m, in which the third conductive heteropolycrystalline stone is used. The layer is manufactured according to the first item of the scope of patent application 'wherein the second conductive y >,' w ------ / & The thickness of the third conductive layer is all 100 Å wet-etched the metal · # tThe method of making a patent application scope item 1, wherein the method of the dagger layer uses an RCA standard solution. The method of claim 1 in the scope of the patent application, where the substrate is a ^ 〇y μn substrate or a silicon-on-insulator (SOI) substrate __Patent application Fangu_The manufacturing method of item 1 'wherein the dielectric layer is a dielectric layer subjected to ~ chemical mechanical polishing (chemical mechanical □ 8 274) 6. The scope of patent application pol ishing (CMP). 11. If the scope of the patent application is poor _13 ^, the manufacturing method, wherein after the wet etching of the metal stone layer, the method further includes the following steps: forming an amorphous stone layer on the surface of the Zhao-shaped lower storage electrode (am. rph〇US si 1 i con) layer: and a hemi-sphericai grain (HSG) process is performed to uniformly form a polycrystalline shredded layer with a hemispherical grain (HSG) structure on the surface of the amorphous sand layer . 12. A method on a substrate, which includes the following MOS transistor on the substrate; a hole is made, and the conductive layer is connected to the dielectric doped silicon layer and filled in the photoresist layer Steps on the bottom surface: The bottom shape 9 yellow light and the contact hole current-carrying layer are stacked on top of each other. The contact hole is defined as a stacked lower storage electrode on the light surface which contains at least one M0S power. Crystal, the method forms a dielectric layer, and the dielectric layer completely covers the post-etching process, forming a source or drain contacting the MOS transistor in the dielectric layer; forming a silicidation by a plurality of metals Layer and a plurality of conductive stacks with a contact hole; a photoresist layer is formed on the surface of the conductive layer, and the patterns and positions of the storage electrodes are stored in the lower layer; the conductive layer covered by the resist layer until the Table of Dielectric Layers Page 17 46 8 274 6. Apply for a patent to remove the photoresist layer; and wet etch the plurality of metal silicide layers to form a fin-like stacked lower storage electrode. I 1 3. The method according to item 12 of the patent application, wherein each metal silicide layer in the conductive layer is composed of tungsten silicide (WSix) or titanium silicide (Ti Six). 14. The method according to item 13 of the scope of the patent application, wherein the thickness of each metal silicide layer in the conductive layer is between about 15 and 200 Angstroms. 15. The method according to item 12 of the scope of the patent application, wherein the thickness of each doped silicon layer in the conductive layer is about 1000 Angstroms (U). 16. The method according to item 12 of the patent application scope, wherein the substrate is a silicon substrate or a silicon-on-insulator (SO I) substrate. 1 7. The method according to item 12 of the patent application, wherein the method of wet etching the plurality of metal silicide layers uses an RCA standard solution. 18. The method according to item 12 of the patent application scope, wherein the dielectric layer is a dielectric layer subjected to a chemical mechanical polishing (CMP). »1 9. The method according to item 12 of the patent application range, wherein the plural numbers are wet-etched Page 18 4 6 8 274 6. After applying for a patented metal silicide layer, the method further includes the following steps: forming an amorphous silicon layer on the surface of the fin-like lower storage electrode; and performing hemispherical grains ( (HSG) process to uniformly form a polysilicon layer with a hemispherical grain (HSG) structure on the surface of the amorphous silicon layer. Page 19