TW399309B - Cavity-down package structure with thermal via - Google Patents

Cavity-down package structure with thermal via Download PDF

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Publication number
TW399309B
TW399309B TW087116231A TW87116231A TW399309B TW 399309 B TW399309 B TW 399309B TW 087116231 A TW087116231 A TW 087116231A TW 87116231 A TW87116231 A TW 87116231A TW 399309 B TW399309 B TW 399309B
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Taiwan
Prior art keywords
heat sink
substrate
package structure
heat
die
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TW087116231A
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English (en)
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Tz-Jang Tzeng
Jen-Hua Jeng
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World Wiser Electronics Inc
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Priority to TW087116231A priority Critical patent/TW399309B/zh
Priority to JP01062199A priority patent/JP3895880B2/ja
Priority to US09/267,885 priority patent/US6175497B1/en
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Publication of TW399309B publication Critical patent/TW399309B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

3088twfl .doc/002 第87 1 1 623 1號說明書修正頁 五、發明説明（（7 ) 言’基材200中央具有一中空凹穴212,用以容納晶粒2〇5 及連接基材200之導線214。中空凹穴212的周緣的印刷 電路被2〇4.呈階梯狀’並暴露出多個銲墊216，藉由導線 21 4與晶粒2〇5上之銲墊（未繪示於圖中）耦接。基材200之 一側還配置有多個銲球218，待封裝完成後整個IC封裝將 透過這些驛球218與公板(Mother Board，未繪示於圖中） 耦接。因此晶粒205之訊號或電源的輸入輸出，將透過晶 粒上的銲墊、導線、銲墊、金屬層、貫孔及銲球而與公板 連接。 與習知封裝結構不同的是，基材200周緣配置有多個 導熱孔220(Thermal Via)，其型態類似貫孔（through hole)， 只是其爲貫穿整個基材200。導熱孔220之形成依照不同 型態之基材而有不同方法，若基材爲傳統多層電路板基 材’則可利用一般鑽孔的方法，若採用高密度基板(High-
Density Interconnection Board) ， 則可利 用微孔（Micro Via) 技術’如雷射鑽孔(Laser via) '微影鑽孔（Photo Via)、電 漿鑽孔（Plasma Via)等方法來形成導熱孔220。之後導熱孔 22〇需經電鍍及導熱性高分子塞孔（Epoxy Plug)，或用金屬 膠(Metal Paste)塞孔，並加熱硬化。導熱孔220之一側配 置有金屬墊222，用來與散熱片202接合，而另一側則配 置一銲球218用來與基板連接。 ' 請同時參照第4圖，其繪示散熱片202的詳細視圖。 散熱片202的材料可採用金屬（如銅Cu、鋁A1或其合金）、 陶瓷(如氧化鋁Al2〇3、氧化鎂MgO、氮化鋁A1N、碳化矽 » 8 本紙張尺錢if]巾_料辦.Γ^ΓΓ^^Χ_297“ )-- -- (讀先閱讀背面之注意事項再填寫本頁)
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3088tw f.duc/O OS A7 B7 五、發明説明（丨） 本發明τη有關h —種具有導熱孔（thermal Via)且晶穴 朝下型（Cavity-Down)之封裝結構，且特別是有關於一種具 有超高效率熱導結橇之導熱孔式晶穴朝下型封裝結構。 在個包括至少一個積體電路（Integrated Circuit，1C) 的模組(Module)中，由於大量的導線由IC晶片中釋出做爲 訊號或電源的輸入及輸出，因此需要數以百計的連接導體 來形成完整的線路。過去’有許多種不同的線路晶粒封裝 方式。最常見的封裝方式爲平面包裝，密封及塑膠晶粒承 載器（Hermetic and Piastic Chip Carrier)，格式陣列封裝 (Grid Array Package)。 在傳統而普遍使用的f C晶片封裝中，使用導線架(L e a d Frame)以電性連接半導體晶粒及封裝的外接導線。然而， 由於積體電路越加精密及複雜的發展，雖然封裝的體積保 持原狀或減小，其所需的導線卻大量增加。傳統的導線架 製程技藝已不敷使用，因此，需要發展新的包裝方式，以 容納及連接更多的導線，完成更複雜的線路。 一種可容納及連接高導線數量的封裝方式爲球格陣列 (BGA)。BGA封裝通常爲一方形的封裝，其中導線端點以 銲球（Solder Ball)的型式形成對外之接點。這些端點的設 計，是用以與印刷線路板（Printed Wire Board,印刷線路板 or Printed Circuit Board,印刷線路板）事其他適當元件表 面的銲墊（Bonding Pad)做電性連接。 實際上’傳統的BGA的基材（substrate)爲一小型的雙 面板或多層（multi-layer)的印刷線路板，而積體電路晶粒經 (請先閱讀背面之注意事項再填寫本頁) r 本紙张尺度適州中國®家標冷(（、NS ) Λ4規格（210Χ297公釐） 3 088twr.doc/〇 〇,s A7 B7 五、發明説明（）） 由不同的導電途徑與基材電性及實體相連接。基材中導電 層之間的連接，則透過貫通孔（Through Hole)電鍍或金屬塞 孔來實施。 請參照第1圖，在由LSI Logic Corporation所提出的 美國專利案號5,357,672中，即爲一種晶穴朝下的BGA封 裝結構，其利用多層印刷線路板100、102、104(Printed Wire Board,印刷線路板）及黏膠1〇6、1〇8、110(prepreg)壓合之 結構形成基材，並在基材中形成一晶穴（Cavity)，如第1圖 所示。將晶粒1 12裝置於晶穴中央，在晶穴週圍是由印刷 線路板100、102、104切成階梯結構，此階梯邊緣有銲墊 (Bonding Pad)l 14、1 16設計，晶粒112之內部信號由晶粒 112周緣的銲墊1 18，藉由打線(Bond Wire) 12〇接至印刷線 路板階梯邊緣上的銲墊114、116，再由印刷線路板之線路 透過貫孔（Through Hole)122傳至凸塊(Bump)124，最後.， 傳至主基板（Main Board)。而散熱片130(heat sink)係與晶 粒112背面接合，用以做爲晶粒散熱之途徑。 此專利利用印刷線路板及黏膠壓合作爲基材，且將晶 粒裝置於基材中的晶穴內，因此，使得晶粒與凸塊裝置在 基材的同一面上，與一般晶粒與凸塊配置在基材兩側的 BGA封裝方式比較，省略了兩片導電層的使用。 在傳統之晶穴朝下的BGA、PG今或多晶粒模組 (Multi-Chip Module, MCM)封裝中，基材至少需要兩層或兩 層以上之金屬層壓合在基材中印刷線路板的兩個表面上 (如第1圖的導電層126及128)，且由印刷線路板疊合形成 4 本紙張尺度適州中國围家標肀（（、NS ) Λ4規格（210Χ297公嫠） (請先閱讀背面之注意事項再填寫本頁)
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30XXtwl.d oc/OOS A7 B7 五、發明说明（3 ) 晶穴。由於一般晶粒的厚度與銲接球之高度相當或較高’ 習知晶穴朝下的BGA、PGA或MCM封裝，歸接球及晶粒 係配置在基材的同一側上，在封裝中打導線（bonding)及灌 膠（molding)時，會有高度過高的問題，會阻礙將來銲接球 與主機板的接觸。因此習知技藝中使用此種晶穴朝下型封 裝時’晶粒（chip)通常需要經過硏磨（grinding)，使其厚度 變薄(約1〇〜25 mil)。然而晶圓（wafer)在硏磨、切割時容易 破裂，造成製造成本損失。 此外’目前對於晶穴朝下型BGA、PGA及MCM的散 熱設計，僅利用晶粒背面接合一平板式散熱片（如第1圖之 130) ’而此種設計在未來高積集度、高速率的元件上，由 於其發熱量很大且元件對於溫度十分敏感，因此習知的散 熱設計可能不敷使用。 因此’本發明之主要目的，在提供一種具有導熱孔 (thermal V1a)設1十之晶穴朝下型封裝結構，其中，晶粒放置 塾」Chip Mount Pad)用銀膠直接與金屬或熱導性質陶瓷 或高分子(⑽叫材料製成之散熱片（_驗湘連，形 成粒最直接且最接近的導熱途徑。此 外’可奉曰由^布在成熱片上的導熱孔將部分的熱能有效的 胃'銲楚銲球傳導至此基板所銲接的公 板PCB上’進-步提高散熱效果。 基’切明之另—主要目的，在提供— Ϊ二t十之晶穴朝下型封裝結構，其中，散熱片 可配S曰曰粒享又，與基材厚度而設計成凹狀，有利於打金
f、紙張尺度ϋ中國囤家標率（（'NS (請先閲讀背面之注意事項再填寫本頁) 訂 1 Οχ 29 7公漦） 3 088l\\ I'.doc/O0<S A7 B7 五、發明説明（K ) 屬導線及灌膠製程。此種結構可適用於BGA、PGA(Pin-Grid Array)、CSP(Chip Scale Package)及 MCM。 根據上述及其他的目的，應用本發明，提出一種具有 導熱孔設計之晶穴朝下型封裝結構，由基材、散熱片及接 合基材與散熱片的黏著層所構成。其中基材係由多層印刷 電路板壓合而成，中央具有中空凹穴，且周緣配置多個導 熱孔。散熱片具有晶粒黏著區及散熱孔接合區。晶粒黏著 區是用以承載晶粒放置墊，使得晶粒藉由晶粒放置墊與散 熱片相連，而散熱孔接合區與導熱孔耦接，形成短路或近 乎短路之接點。黏膠層則配置於散熱片及基材之間，用以 使得基材與散熱片接合。藉由本發明之結構晶粒操作中所 產生之熱能除了可藉由散熱片直接散熱，亦可由散熱片透 過導熱孔傳導至基板而散熱。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一實施例，並配合所附圖式，作詳細說 明如下。 圖式之簡單說明： 第1圖所繪示爲一種習知BGA封裝結構。 第2圖所繪示爲依照本發明較佳實施例的一種具有導 熱孔之晶穴朝下型封裝結構。 第3圖所繪示爲對應於第2圖中基材之詳細視圖。 第4圖所繪示爲對應於第2圖中散熱片之詳細視圖。 實施例 應用本發明，提出一種具直接或近乎直接之導熱途徑 6 本紙張適/11+國®家標净((、NS ) Λ4規格（210 X 297公釐) ~ (讀先閱讀背面之注意事項再填寫本頁)
¾¾—部中央標卑局Η消於合作社印^ 3088tu f'.d〇c/0〇S A7 ______ B7 五、發明説明（ί ) 的印刷電路板的熱導結構，在日趨精密的電子產品中，電 子產品要求更加的輕薄短小的體積，且需要良好的散熱途 徑。因此，本發明與習知技藝不同之處，在於本發明利用 具不規則表面，亦即凹凸圖案結構表面之散熱片的形成， 使得承載晶粒之放置墊直接或近乎直接地與散熱片相連， 因而縮短了散熱途徑’提高了散熱效果。另外可藉由散熱 片及導熱孔將熱能傳導至基板’提供另一散熱途徑。並且 配合散熱片之凹凸圖案可改善打導線及灌膠製程，並提高 生產良率。 請參照第2圖’其所繪示爲依照本發明較佳實施例的 一種具有導熱孔之晶穴朝下型封裝結構。本發明之封裝結 構主要是由基材（substrate)200、散熱片（heat sink)202及晶 粒(chip)2〇4所組成。请同時參照第3圖，其繪示基材的詳 細視圖。基材200 —般是由多層印刷電路板2〇4壓合而構 成’而印刷電路板2〇4係由金屬層2〇6(比如銅）及樹脂 2〇8(Epoxy)所構成。而印刷電路板204間的接合是由黏膠 層(Prepreg，圖中未繪示）來達成’黏膠層的材料可選用， 例如，Fr_4，F1.-5，雙馬來醯亞胺二氣雜苯化合物黏膠 (Bismalemide Ti’iazine，BT-Prepreg) ’ 或聚亞苯基酸 (Polyphenylene Ether, PPE)。金屬層206之間的稱接則是由 印刷電路板2〇4上多個貫孔(through hol、e)，經過電鍍塡入 導電之塞孔材質（如圖中210所示）來達成。本實施例之示 意圖中雖然僅繪示二層印刷電路板，然而多層印刷電路板 壓合而成之基材亦爲相似結構。對晶穴朝下型的封裝而 7 本紙張尺如则，關丨料(CNS ) Λ4規格（210,297公嫠) -- (讀先閱讀背面之注意事項再填寫本頁)
3088twfl .doc/002 第87 1 1 623 1號說明書修正頁 五、發明説明（（7 ) 言’基材200中央具有一中空凹穴212,用以容納晶粒2〇5 及連接基材200之導線214。中空凹穴212的周緣的印刷 電路被2〇4.呈階梯狀’並暴露出多個銲墊216，藉由導線 21 4與晶粒2〇5上之銲墊（未繪示於圖中）耦接。基材200之 一側還配置有多個銲球218，待封裝完成後整個IC封裝將 透過這些驛球218與公板(Mother Board，未繪示於圖中） 耦接。因此晶粒205之訊號或電源的輸入輸出，將透過晶 粒上的銲墊、導線、銲墊、金屬層、貫孔及銲球而與公板 連接。 與習知封裝結構不同的是，基材200周緣配置有多個 導熱孔220(Thermal Via)，其型態類似貫孔（through hole)， 只是其爲貫穿整個基材200。導熱孔220之形成依照不同 型態之基材而有不同方法，若基材爲傳統多層電路板基 材’則可利用一般鑽孔的方法，若採用高密度基板(High-
Density Interconnection Board) ， 則可利 用微孔（Micro Via) 技術’如雷射鑽孔(Laser via) '微影鑽孔（Photo Via)、電 漿鑽孔（Plasma Via)等方法來形成導熱孔220。之後導熱孔 22〇需經電鍍及導熱性高分子塞孔（Epoxy Plug)，或用金屬 膠(Metal Paste)塞孔，並加熱硬化。導熱孔220之一側配 置有金屬墊222，用來與散熱片202接合，而另一側則配 置一銲球218用來與基板連接。 ' 請同時參照第4圖，其繪示散熱片202的詳細視圖。 散熱片202的材料可採用金屬（如銅Cu、鋁A1或其合金）、 陶瓷(如氧化鋁Al2〇3、氧化鎂MgO、氮化鋁A1N、碳化矽 » 8 本紙張尺錢if]巾_料辦.Γ^ΓΓ^^Χ_297“ )-- -- (讀先閱讀背面之注意事項再填寫本頁)
，1T 3088twfl .doc/002 A7 B7 五、發明説明（/| )
SiC等）、或高分子導熱材料。散熱片202之厚度h約 6〜60mil ’主要區分爲晶粒黏著區224(Chip Mount Area)及 導熱扎接合區226，導熱孔接合區226配置有多個島形突 起228，其高度dl約0.2〜3_0 mil，對應於的導熱孔（第2、 3圖之220) ’用來與導熱孔接合。而依照需求，爲配合晶 粒204厚度及基材200厚度，在晶粒黏著區224中可適當 地形成一凹狀230，其深度d2可達40mil，用以承載晶粒 205 ’可利於打導線及灌膠製程，且晶粒2〇5亦無須硏磨或 僅稍事硏磨’可提高生產良率。散熱片202的凹狀結構230 可承載一晶粒放置墊(如第2圖之232)，使晶粒204與之接 合。 散熱片202島形突起228及凹狀23〇結構可透過微影 餓刻（Photolithography plus chemical etch method)、灌模法 (Molding)或射出成型法（Extrusi〇n)來達成。接著，必須經 過去脂 '淸潔再磨刷或用化學蝕刻法使其表面粗糙。而此 粗糖之表面能提供較佳之接合性，將有利於後續晶粒2〇4 以晶粒放置墊232黏著於凹狀結構23〇，或者透過銀膠層 (Silver Paste，第2圖之幻^使散熱片2〇2與基材2〇〇接合。 黏膠層234的材料可選用，例如，Fr_4，Fr_5，雙馬來 醯亞胺二氮雜苯化合物黏膠（Bismalemide Triazine，BT-Prepreg) ’芳香族聚醯胺纖維（Aramid)或聚亞苯基醚 (PolyPhenylene EtheF，PpE)。將前述多層印刷電路板構成之 基材200及散熱片202以前述的黏膠層234疊合(Lay-up) 經局溫筒壓黏著，或在真空腔（Vacuum Chamber)中高溫高 9 本紙张尺度適川中國围家標率（rNS ) A4^^#T2T〇^297"^t ) (誚先閱讀背面之注意事項再填寫本頁) 裝·
.1T 3 08 81w f1 doc/002 A7 B7 五、發明説明（孓） 壓真空壓合。之後，再經過晶粒205黏著、打導線、灌封 膝材料 240(Encapsulation)及植銲球（Solder Ball Placement) 製程Φ可獲得如第2圖之封裝結構。 在實際的應用上，散熱片202之島型突起228與印刷 電路板200的導熱墊222經由黏膠層234(prepreg or adhesive)形成短路或近乎短路，形成良好的熱導途徑。透 過導熱孔220、導熱墊222及銲球218可有效的將熱能傳 導至公板，提供另一良好散熱途徑。 此外，由於晶粒205是直接粘著於散熱片202，而散 熱片202可以彈性地形成一凹型結構以承載晶粒，具有調 整晶粒粘著區深度的能力，可免除晶粒硏磨製程或僅稍事 硏磨，採用較厚之晶粒。不但增加生產之彈性，簡化製程， 可提高製程良率並使產品電性性能較好。而本發明之結構 可應用於晶穴朝下型之BGA ' PGA、MCM、CSP等封裝。 雖然本發明之實施例如上所揭露，然其並非用以限定 本發明，任何熟習此技藝者，在不脫離本發明之精神和範 圍內，當可作各種之更動與潤飾。 (誚先閱讀背面之注意事項再填寫本頁) 訂 ii.>vi.部屮消 φίΑεϊίΓίι-印 本紙張尺度適用中國國家標埤（CNS ) Λ4規格（2丨ΟΧ25»7公釐）

Claims (1)

  1. 3088twf.doc M93〇' A8 B8 C8 D8 申請專利範圍 1.一種具有導熱孔之晶穴朝下型封裝結構，應用於一晶 粒之封裝，該封裝結構包括： 一基材，該基材係由複數層印刷電路板壓合而成，該 基材中央具有一中空凹穴，且周緣具有複數個導熱孔，該 中空凹穴周緣具有複數個銲墊用以與該晶粒電性耦接； 散熱片，該散熱片具有一晶粒黏著區及一導熱孔接 合區，該晶粒黏著區用以承載一晶粒放置墊，使得該晶粒 藉由該晶粒放置墊與該散熱片相連，該導熱孔接合區與該 些導熱孔耦接，形成短路或近乎短路；以及 一黏膠層，配置於該散熱片及該基材之間，用以使得 該基材與該散熱片接合。 2. 如申請專利範圍第1項所述之封裝結構，其中該些 導熱孔中塡充有導熱樹脂。 3. 如申請專利範圍第1項所述之封裝結構，其中該些 導熱孔中塡充有金屬膠。 其中該散 4. 如申請專利範圍第1項所述之封裝結構 熱片之該導熱孔接合區具有複數個島型結構，分別藉由該 黏膠層與該些導熱孔連接。 經濟部中央標準局負工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 5. 如申請專利範圍第1項所述之封裝結構，其中該散 熱片之該晶粒黏著區呈一凹狀。 6. 如申請專利範圍第1項所述之封裝結構，其中每一 該些導熱孔之一側分別具有一金屬墊，用以藉由該黏膠層 與該散熱片之該導熱孔接合區連接，且每一該些導熱孔之 另一側配置有一銲球，用以與一基板連接。 本紙張尺度適用中國囤家標準（CNS ) A4规格（210X297公釐） 經濟部中央標準局貝工消費合作社印製 3993UG as 3 08 8twf.doc/00 8 C8 D8 六、申請專利範圍 7. 如申請專利範圍第1項所述之封裝結構，其中該散 熱片係由一高導熱材料所構成。 8. 如申請專利範圍第7項所述之封裝結構，其中構成 該散熱片之該高導熱材料至少包括：氧化鋁、氧化鎂、氮 化鋁以及碳化矽。 9. 如申請專利範圍第1項所述之封裝結構，其中該散 熱片之材質係選自於由銅、鋁、銅合金、鋁合金、氧化鋁、 氧化鎂、氮化鋁、碳化矽所組成之導熱型材料族群。 (請先閲讀背面之注^事項再填寫本頁)
    本紙張尺度適用中國囷家揉準（CNS ) Α4規格（210X297公釐）
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