TW396459B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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TW396459B
TW396459B TW087120779A TW87120779A TW396459B TW 396459 B TW396459 B TW 396459B TW 087120779 A TW087120779 A TW 087120779A TW 87120779 A TW87120779 A TW 87120779A TW 396459 B TW396459 B TW 396459B
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semiconductor device
patent application
layer
scope
transistor
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TW087120779A
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Hideaki Onishi
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Nippon Electric Co
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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Description

五、發明說明（1) 2明是有關於-種半導體裝置’且更特別的是 於一種SOI半導體裝置。
Sj I裝置吸引更多人注意的地方是因為其可便利地用 來隔離70件，且其具有latch_up free的特徵，因此可 低源極/汲極接面電容。然而，當一金氧半（M0S)元件形 於一厚度為10〇nm或者更薄之S0I膜上時，源極厂沒極之電 阻將會顯著地增加。因此，一種可降低源極/汲極電阻之 技術是必須的。一種使用鈦或具有高熔點之類似金屬之技 術便可用來克服上述製程之缺點。 通4，在一SO I膜上形成一具有矽化鈦之M0S元件的半 導體裝置之構型是根據1 995年10月IEEE世界SOI研討會所 教導的製程進行。揭示於此文獻中的構型所遭遇的問題是 當矽化金屬預備形成於一位在單晶矽内的源極/汲極上時 ，磷和砷等摻植物將會抑制矽化金屬反應，且特別是在 NM0S中。因此，矽化金屬的電阻將會隨著源極/汲極的寬 度減小而迅速地增加，也就是所謂的窄線寬效應。此類矽 化金屬電阻之增加’應用於次微米和後續之大型積體電路 時將會造成必要的影響。 本發明有關之技術亦揭示於日本專利La id-〇pen公開 號No. 6-140428 以及VMIC Conference 1995 ISMIC-104 /98/0640(Ishigami et al.， June 27-29， 1995， ”Α ΤΙ -SALICIDE PROCESS UTILIZING LOW PRESSURE N2 RTA")。
第4頁
發明概要： 本發明之一特徵是揭示一種半導體.裝置，其可在不需 複雜結構和對元件特性造成負面影響下，抑制S0丨元件之 源極/没極上的石夕化金屬因為窄線寬效應而導致電阻增加 的現象。 本發明之半導體裝置包括有一淺薄的絕緣膜，以及_ 形成於SOI基底上之M0S電晶體。此M0S電晶體具有一第_ 導電型通道區、一擴散至薄絕緣膜之第二導電型源極/汲 極區、一覆蓋部分源極/汲極區之高熔點矽化金屬以及— 形成於矽化金屬和薄絕緣膜間的複晶矽層。 圖式之簡單說明： 為使根據本發明之上述優點和特徵更清楚可f a 以根據本發明之較佳杂谕彻:行伋更滑楚叮見，玆并 下，其中. 敉佳只施例，以及相關圖式，詳細說明士 第1圖顯示的是翌左n ^ ^ 第+ +導體裝置的剖面圖； 第2圖顯不的是習知的本道^ 第3圖顯示的是！:艮=::裝置的窄線寬效應圖； ; 據本發明之互補式金氧半（CMOS) 第4圖顯示的是根墙 第5A〜5F圖顯示的0搞減\之實施例的窄線寬效應； 程；且 、疋根據本發明以製造CMOS的剖面製 第6圖顯示的 在該些圖中 疋根據本發明之另一實施例。 相同的符號代表的是相同的結構單元 〇
第5頁 五、發明說明（3) 實施例： 沾主更好了解本發日月，在此將先簡短地回顧-種習知 、導體裝置。如第1圖所示，一矽化鈦是形成於一位在 膜上的M0S元件表面。此類半導體裝置是根據1 99 5年 10月IEEE世界SOI研討會所教導的製程進行。如·圖所示， 半導體裝置是由一矽基底1、一埋入式氧化膜2、一場氧化 膜3、一構成NM0S通道區之p型層4、一構成pM〇s通道區之^ 型層5、一構成NM0S源極/汲極之N+層以及一構成pM〇s源極 /汲極之P+層11所構成。此外，第】圖中也顯示有一閘極氧 化層6、一複晶矽閘極7、一邊牆8以及一矽化鈦。 通常，N+層10和P+層均形成於一單晶矽層上，以避免 接面漏電和其他問題。特別是因為NM〇s之源極/汲極的注 入，一般均認為磷是較適合用來防止源極/汲極變成完全 地非晶發化。 上述構型所遭遇的問題是當矽化金屬預備形成於固定 ，皁晶矽基底上之源極/汲極表面時，磷和砷等摻雜物 抑制矽化金屬反應，且特別是在關⑽中。因此•圖 紗化金屬之電阻將會隨源極/汲極之線寬^減少而 =速地增加，也就是所謂的窄線寬效應。此類石夕化金屬電 之增加，應用於次微米和後續之大型積體電路時將會造 成必要的影響。 接著，請參閱第3圖，其顯示的是根據本發明之一實 施例。如圖所示，此半導體裝置包括有一N+複晶矽層12，
第6頁 五、發明說明（4) 以及一形成於N+型複晶咬層12表面上之矽化鈦層14。N+型 ，晶砍層1 2是位在NMOS之源極/汲極區之石夕化鈦預定形成 處之區域。 在N Μ 0 S之矽化金屬預定形成區域中，N +複晶矽層丨2 成一層。複晶矽與單晶矽不同的是在於顆粒界面是存 的，並且可促進導致擴散的矽化金屬反應，因此可成功地 抑制習知線寬縮小所引起的窄線寬效應。因此，如第4圖 所示，即使在線寬大小是次微米層次時，也可形成低電阻 的矽化金屬。此外，在所揭示的實施例中，一鄰接通道區 的Ν+層10是維持在單晶的狀態，故可避免影響接面漏電和 其他會對元件性質造成影響的因素發生。 通常，SOI電晶體所遭遇的問題是在運作時，汲極電 場所產生的電洞會使通道部位的電位升高。此升高的電位 將會導致寄生雙戴子效應，例如造成電晶體之汲極電流至 汲極電壓性質的錯亂以及汲極電壓的降低。相對地，在第 3圖所示之結構中，在源極底下的矽部位將可作為將汲極 電場產生之電洞彈回的中心，進而促進其吸附電洞的效率 。因此，如上所揭示的實施例可用來抑制寄生雙載子效應
接著’請繼續參照第5A〜5F圖，其顯示的是製造如第 3圓所示之半導體裝置的剖面製程。首先，如第5A圖所示 ’將一包括在SOI基底1内的矽層削薄至想要的厚度，例如 50mm。然後’利用LOCOS(石夕區域氧化法）或者類似的習知 方法形成一場氧化層3以隔離元件。接著，將硼或磷分別
第7頁 五、發明說明（5) 佈植至濃度約10ncm-3至1〇18cm-3。其中，在佈值時，光阻是 被當作罩幕來使用。然後，便可形成一p_層和一n_層5。 如第5B圖所示，利用熱氧化法形成一閘極氧化膜，苴 厚度例如為7nm。然後，利用化學氣相沉積法在閘極氧化〃 膜上沉積一厚度約150nffl的複晶矽層。接著，利用微影程 序和非等向性蝕刻技術將此複晶矽層定義成一複晶矽閘極 7。然後，再利用化學氣相沉積法以及蝕刻法形成一厚度 lOOnm厚的氧化物邊牆。 ^如第5C圖所示，定義出一用以形成NM0S源極/汲極之 光阻13 :然後再利用離子佈植法將能量約50keV之砷或具 有大質量的類似摻雜物摻雜至基底内，以形成一最終雜質 濃度為5 X 1 〇2〇cm-3的非晶矽層。然後，便可形成一含有高 濃度?^形雜質的非晶發層9。 如第5D圖所示，在形成pM〇s的光阻13定義出來後將 能量30keV的BF2佈植到基底内.，使其最終濃度為5 X 1 020cm_3。 如第5E圖所示’在1 000 t：環境中進行為時1〇秒的熱退 火處理以活化該些雜質’使NM〇s中的非晶矽層形成N+複晶 矽層12、。此外，在⑽〇S中，與形成N+層10(單晶矽層）之p-層4通道區接觸的部位，其中的雜質將會水平地擴散，而 固體層，纟w B曰的成長將會由通道部位之單晶矽層開始。在 PM0S中’因為缺乏非晶矽層，而使整個源極/汲極區形成 P+層11 (單晶矽層）。 如第5F圖所示，矽化鈦1 4是利用習知的方法形成於源
第8頁 五、發明說明（6) 極/没極和閘極上。為了形成石夕化鈦’必須先滅鑛一厚度 20nm的鈦層，然後再於溫度7〇〇 °C的氮氣環境中進行快速 熱退火，以形成一晶向為C4 9的矽化鈦。然後，利用氨水 、雙氧水以及水所構成之混合溶液選擇性地蝕刻掉所產生 的氮化鈦，接著再於溫度800 °C的氮氣環境中進行快速熱 退火處理，以形成一低電阻的C54晶相的矽化鈦14。 第5F圖所示之步驟結束後，再利用習知方法形成一導 線。 第6圖顯示的是根據本發明之另一實施例。如圖所示 ，此實施例與先前之實施例類似，除在PMOS中預定形成發 化金屬之區域的P+層是利用一P+複晶矽層15來完成。更精 確地說，在第5B圖之步驟中，砷例如是在未使用罩幕的情 況下，以能量約50keV佈植至濃度為1 X i〇2〇cm-3。因此，使 得NMOS和PMOS之源極/汲極區變成非晶矽化。然後，再繼 續以前面實施例所述之方法進行後續的製程。 要主意的是在第6圖中’摻植於PMOS内的珅需以加 以驅除，以形成源極/汲極。雖然PM〇s原本遭遇的窄線2 效應較NMOS來得低，在線寬縮小時電阻的增加現象不如 NMOS來得明顯，然其矽化金屬的電阻也可在 植後而被進一步地降低。 旳離子佈
第9頁 適二上ί的！施例所關注的是梦化鈦，然本發明也可 錄、或者其他具有高溶點之類似梦化金 。 總而言之，本發明所提供的半導體裝置 二 種優點： 卜所返之各 五、發明說明（7) U )因為矽化金屬是形成於複晶矽上，故可在薄S〇I 膜上形成了可抑制窄線寬效應的低電阻矽化金屬。 (2)薄SOI臈裝置上的源極/汲極之電阻 不需要複雜的結構或者製程。 孤降低而 曰狀態(3)ίΪ道區接觸的源極/汲極區部位是固定在-單 曰日狀態，因此牙杜^ 早 影響。 件的性質不會焚到接面漏電和其他因素的 (4)S0I電晶體之寄生雙 雖然本發明已以較佳實施V揭應如可，抑制。 限定本發明，任何熟習此技蓺者， ’然其並非用以 和範圍内’所作之各種更動；：：：離本發明之精神 臾因此本發明之專利保護範始、、在本發明之範圍内 界定者為準。 田視後附之申請專利範圍所 第10頁

Claims (1)

  1. 六、 申請專利範圍 1. 一種半導體裝置’其包括： 一具有淺薄絕緣膜之S 0 I (石夕在絕緣物上）基底；以及 一形成於該SOI基底上之MOS電晶體，· 該M0S電晶體包括有： 一第一導電型通道區； 一第二導電型源極/没極’擴散至該薄絕緣膜； 一具有高熔點之矽化金屬覆蓋部分該源極/汲極區； 以及 一複晶石夕層介於該石夕化令Μ知兮# ^化金屬押孩溥絕緣膜之間。 申第1項所述之牟導體裝置，其中該 s〇I基底^包括有一/夕基底，該薄絕緣膜是形成於該矽基底 上，且一薄石夕膜疋形成於該薄絕緣膜上。 其中該 其中該 其中該 〇 其中形 3. 如申請專利範圍第2項所述之半導 複晶矽層是利用離子佈植和高溫退火而形成。 4. 如申請專利範圍第3項所述之半 5 ^ 電晶體和— NM〇S電晶體， 5·如申印專利範圍第4項所述之半 曰曰：ί Ϊ ί :成於該NM〇S電晶體之-元件區内 成於該薄範圍Γ項所述之半導體裝置，其中形 金屬和該複、晶矽層之該’矽膜的-部份是被轉變成該矽化 複晶矽Ϊ = 項所述之半導體裝置’其中該 8.如申請專利範圍第U所述之半導體成裝置，其中該
    第11頁 六、申請專利範圍 MOS電晶體包括有一PMOS電晶體和一 NMOS電晶體。 9. 如申請專利範圍第4項所述之半導體裝置，其中該 複晶矽層是僅形成於該NMOS電晶體之一元件區内。 10. 如申請專利範圍第1項所述之半導體裝置，其中該 MOS電晶體包括有一PMOS電晶體和一 NMOS電晶體。 11. 如申請專利範圍第1 0項所述之半導體裝'置，其中 該複晶矽層是僅形成於該NMOS電晶體之一元件區内。 12. 如申請專利範圍第1項所述之半導體裝置，其中該 複晶矽層是僅形成於該NMOS電晶體之一元件區内。 13. 如申請專利範圍第1項所述之半導體裝置，其中形 成於該薄絕緣膜上之該薄矽膜的一部份是被轉變成該矽化 金屬和該複晶石夕層。 14. 如申請專利範圍第1項所述之半導體裝置，其中更 包括有一單晶石夕層形成於該電晶體之該複晶石夕層和該通道 區間。
    第12頁
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