CN1220496A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN1220496A
CN1220496A CN98123350A CN98123350A CN1220496A CN 1220496 A CN1220496 A CN 1220496A CN 98123350 A CN98123350 A CN 98123350A CN 98123350 A CN98123350 A CN 98123350A CN 1220496 A CN1220496 A CN 1220496A
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semiconductor device
polysilicon layer
transistor
nmos pass
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大西秀明
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Abstract

一种MOS(金属氧化物半导体)器件,包括硅基片,形成在基片上的绝缘膜及形成在绝缘膜上的薄硅膜。MOS器件具有第一导电型的沟道区,扩散到绝缘膜的第二导电型的源/漏区,及具有高熔点的金属硅化物。通过多晶硅层形成金属硅化物与绝缘膜之间的薄硅膜。在不使器件结构复杂化及影响其性能的情况下可抑制由于窄线效应导致的硅化物电阻的降低。

Description

半导体器件
本发明涉及半导体器件，尤其涉及SOI(绝缘体基外延硅)的半导体器件。
SOI器件由于其利于器件的隔离，而越来越引起人们的注意，其具有非锁定的特点，从而可降低源/漏区的结电容然而，当在100纳米或更薄的SOI膜上形成MOS(金属氧化物半导体)时，源/漏区电阻会明显的增大，在此情况下，很需要用于减少源/漏区电阻的技术。使用钛或类似高熔点金属的硅化技术对于实现上述目的很具实用性。
在1995年的电子工程师国际SOI会议的前言中对在薄SOI膜上的MOS器件上所形成的具有硅化钛的半导体器件结构进行了描述。在此文件中对这种结构所提出的问题在于当在被保持为单晶硅状态的源/漏区上要形成硅化物时，作为搀杂物的磷或砷会抑制硅化，尤其是在NMOS中。其结果，硅化物的电阻会随着源/漏区的线宽度的减小而增大。将此结果称为窄线效应。此种硅化物电阻的增大对于半-微米生产或连续生产的LSI(大规模集成电路)而言，会大大的影响其工作速度。
在日本专利公开No.6-140428及在1995 ISMIC-1C4/95/0640,1995VMIC会议(June 27-29)由Ishigami等所发表的“使用低压N2 RTA的硅化钛工艺”中对与本发明有关的技术进行了描述。
本发明的目的时提供一种SOI半导体器件，在不影响结构及性能的情况下可抑制造成窄线效应的源/漏区上的硅化物电阻的增大。
本发明的半导体器件包含：具有超薄绝缘膜的SOI基片，及形成在SOI基片上的MOS晶体管。MOS具有第一导电型的沟道区，扩散到薄绝缘膜中的第二导电型的源极漏极区，具有高熔点并覆盖部分源/漏区区的金属硅化物，及形成在金属硅化物与薄绝缘膜之间的多晶硅层。
通过下面结合相应附图的描述会对本发明的以上及其他目的，特点及优点有更清楚的了解。其中：
图1为传统半导体器件的截面示意图；
图2为对于传统半导体器件的窄线效应的示意图；
图3为体现本发明的CMOS(互补金属氧化物半导体)器件的截面示意图；
图4为对于所述实施例的窄线效应的示意图；
图5A-5F为用于制造所述实施例的制造步骤的截面示意图；及
图6为本发明另一实施例的截面示意图。
在附图中，同样的标号表示相同的元件。
为了更好的理解本发明，对图1中所示的传统半导体器件进行描述，其中硅化钛形成在薄SOI膜上的MOS器件上。此种半导体器件在前面所述的1995年的电子工程师会议的前言中进行了描述。如其所示，半导体器件包含：硅基片1，掩埋的氧化膜2，场氧化膜3，构成NMOS的沟道部分的P层4，构成PMOS的沟道部分的N层5，构成NMOS的源极/漏极的N+层，及构成PMOS的源极/漏极的P+层11。图1中同样示出栅氧化层6，多晶硅栅极7，侧壁8，及硅化钛(TiSi2)。
一般而言，所形成的每个N+层10和P+层都保留在一单晶硅层内，从而避免结漏及其它问题。特别是对于NMOS的源/漏区离子的注入，最好用磷，以防止整个的源/漏区变为非晶态。
上述常规结构的问题在于，当硅化物将要形成在处于单晶状态的源/漏区上时，作为掺杂离子的磷和砷可抑制硅化反应，尤其是在NMOS中。其结果，如图5所示，硅化物的电阻随着源/漏区的线宽度的降低而陡然升高。将此结果称为窄线效应。此种硅化物电阻的增大在半微米的及其后发展的大规模集成电路的生产中会对工作速度造成很严重的影响。参考图3，将对本发明的半导体器件进行描述。如图中所示，半导体器件包括N+多晶硅层12及形成于其上的TiSi2 14。N+多晶硅层12位于将要形成NMOS的源/漏区的硅化钛的地方。
在NMOS的将要形成硅化物的地方，N+多晶硅层12构成N+层。多晶硅与单晶硅的区别在于其存在晶界并由于扩散产生硅化反应。这可大大抑制传统的线宽的降低。其结果，如图4中所示，即使在线宽处于半微米量级时也可形成低电阻的硅化物。另外，在所述实施例中，进入沟道区的N+层10处于其单晶状态。避免了结漏及其它在晶件特性方面的影响。
一般而言，SOI晶体管存在的问题是，在工作期间由漏极电场产生的空穴增大了沟道部分的电势。增大的电势易于产生寄生双极效应，即晶体管电流一电压特性的扭折及漏电压降低。相反地，在图3所示的结构中，源极硅化物下面的硅部分作为在漏电场中产生的空穴再结合的中心，从而促进了对空穴的有效吸收。结果是，所述实施例可以抑制寄生双极效应。
下面将参考图5A-5F对生产图3的半导体器件的具体工序进行描述。首先，如图5A中所示，包含在SOI基片1内的Si层被薄到所需的厚度(如50nm)。然后，通过LOCOS(硅的局部氧化)或类似的传统方法形成场氧化层3从而隔离器件。然后，分别注入浓度为大约1,017cm-3到1,018cm-3的硼和磷。为了进行注入，用光刻膜作为掩膜。其结果，形成了P-层及N-层5。
如图5B所示，通过场热氧化形成例如7nm厚的栅氧化膜。然后，用CVD(化学气相沉积)在栅氧化膜上沉积大约150nm厚的多晶硅。对多晶硅进行光刻和各向异性蚀刻从而形成多晶硅栅极7。接着，用CVD法形成100nm厚的氧化膜然后进行腐蚀以形成侧壁。
如图5C中所示，对用于形成NMOS的源/漏区的光刻胶13进行加工图形。然后，用大约50kev的能量注入大约5×1,020cm-3浓度的砷或类似的掺杂离子，它们通过离子注入易于形成非晶层并且有大的质量。其结果，形成掺有高浓度N型杂质的非晶层9。
如图5D中所示，在对由于形成PMOS的光刻胶13进行加工后，用30kev的能量植入大约浓度为5×1.020cm-3的BF2。
如图5E中所示，在1000埃进行10秒钟的RTA用于激活杂质。结果是，在NMOS中，非晶层形成N+多晶硅层12。同样，在NMOS中，接触沟道的P-层4的部分由于掺杂离子的水平扩散及从沟道部分的单晶硅层的固体层外延生长而形成N+层10(单晶硅层)。在PMOS中，整个源/漏区由于缺少非晶层而形成P+层11(单晶硅层)。
如图5F中所示，用传统方法在源/漏区及多晶硅栅极上形成TiSi214。为形成硅化钛，还需通过将Ti溅射到20nm厚的步骤，在氮气氛中在700℃进行RTA以形成TiSi2(C49)相。用诸如NH4OH、H2O2及H2O溶液选择蚀刻所形成的构成绝缘膜的TiN，通过在氮气氛中在800℃进行RTA从而形成C54相的低电阻TiSi214。
在图5F中所示的步骤后，用传统方法进行布线。
图6示出了本发明的另一实施例。如图中所示，此实施例与前述的实施例基本相同，其区别在于通过P+多晶硅层15形成PMOS的硅化物形成区内的P+层。尤其是，在图5B所示的步骤如，不使用掩膜，通过用50kev的能量植入浓度1×1,020cm-3的砷。其结果，NMOS及PMOS的源/漏区变为非晶态。以后的步骤与前述实施例相同。
需注意的是，注入图6的PMOS中的砷被用于形成源/漏区的BF2所排斥。虽然最初PMOS的窄线效应比NMOS低。因此不会象NMOS那样电阻会很明显地降低，通过另外的离子植入而可降低硅化物电阻。
虽然所述实施例针对的是硅化钛，本发明对于具有高熔点的钴、镍或类似金属的硅化物也适用。
简而言之，本发明的半导体器件具有如下的很优异的特点：
(1)由于硅化物形成在多晶硅上，从而即使在薄的SOI膜上也可形成可抑制窄线效应的低电阻硅化物。
(2)在不借助结构及制造过程改变的情况下可以降低薄SOI膜器件的源/漏区电阻。
(3)与沟道部分接触的源/漏区部分被保持为单晶状态，从而不会产生结漏或其它的影响器件的问题。
(4)可抑制SOI晶体管的寄生双极效应。
对本领域技术人员所作的各种修改都不脱离本发明的范围。

Claims (13)

1．一种半导体器件，其特征在于包含：
一具有超薄绝缘膜的SOI(绝缘体基外延硅)基片；及
形成在所述SOI基片上的MOS(金属氧化物半导体)晶体管；
所述MOS晶体管包括：
第一导电型沟道区；
扩散到所述薄绝缘膜的第二导电型源/漏区；
具有高熔点并覆盖所述一部分源/漏区的金属硅化物；及插在所述金属硅化物与所述薄绝缘膜之间的多晶硅层。
2．根据权利要求1所述的半导体器件，其特征在于所述SOI基片包含一硅基片，形成在所述硅基片上的所述薄绝缘膜，及形成在所述薄绝缘膜上的薄硅膜。
3．根据权利要求2所述的半导体器件，其特征在于所述通过离子植入及高温退火形成所述多晶硅层。
4．根据权利要求2所述的半导体器件，其特征在于所述MOS晶体管包含PMOS晶体管及NMOS晶体管。
5．根据权利要求4所述的半导体器件，其特征在于仅在所述NMOS晶体管的器件区内形成所述多晶硅层。
6．根据权利要求2所述的半导体器件，其特征在于形成在所述薄绝缘膜上的所述薄硅膜被转化为所述金属硅化物及所述多晶硅层。7．根据权利要求1所述的半导体器件，其特征在于通过离子植入及高温退火形成所述多晶硅层。
8．根据权利要求7所述的半导体器件，其特征在于所述MOS晶体管包含PMOS晶体管及NMOS晶体管。
9．根据权利要求8所述的半导体器件，其特征在于仅在所述NMOS晶体管的器件区内形成所述多晶硅层。
10．根据权利要求1所述的半导体器件，其特征在于所述MOS晶体管包含PMOS晶体管及NMOS晶体管。
11．根据权利要求10所述的半导体器件，其特征在于仅在所述NMOS晶体管的器件区内形成所述多晶硅层。
12．根据权利要求1所述的半导体器件，其特征在于仅在所述NMOS晶体管的器件区内形成所述多晶硅层。
13．根据权利要求1所述的半导体器件，其特征在于形成在所述薄绝缘膜上的所述部分薄硅膜被转换为所述金属硅化物及所述多晶硅层。
14．根据权利要求1所述的半导体器件，其特征在于还包含形成在所述多晶硅层和所述晶体管沟道区之间的单晶硅层。
CN98123350A 1997-12-15 1998-12-14 半导体器件 Pending CN1220496A (zh)

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