TW393753B - Improved multi-level conductive structure and method therefor - Google Patents

Improved multi-level conductive structure and method therefor Download PDF

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Publication number
TW393753B
TW393753B TW087112836A TW87112836A TW393753B TW 393753 B TW393753 B TW 393753B TW 087112836 A TW087112836 A TW 087112836A TW 87112836 A TW87112836 A TW 87112836A TW 393753 B TW393753 B TW 393753B
Authority
TW
Taiwan
Prior art keywords
layer
low temperature
low
conductive
dielectric layer
Prior art date
Application number
TW087112836A
Other languages
English (en)
Chinese (zh)
Inventor
Dirk Tobben
Peter Weigand
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of TW393753B publication Critical patent/TW393753B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
TW087112836A 1997-09-29 1998-08-04 Improved multi-level conductive structure and method therefor TW393753B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/939,208 US5977635A (en) 1997-09-29 1997-09-29 Multi-level conductive structure including low capacitance material

Publications (1)

Publication Number Publication Date
TW393753B true TW393753B (en) 2000-06-11

Family

ID=25472743

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087112836A TW393753B (en) 1997-09-29 1998-08-04 Improved multi-level conductive structure and method therefor

Country Status (6)

Country Link
US (1) US5977635A (enExample)
EP (1) EP0905778A3 (enExample)
JP (1) JPH11163142A (enExample)
KR (1) KR100544030B1 (enExample)
CN (1) CN1134837C (enExample)
TW (1) TW393753B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI714657B (zh) * 2015-12-09 2021-01-01 美商英特爾公司 介電緩衝層

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6627539B1 (en) * 1998-05-29 2003-09-30 Newport Fab, Llc Method of forming dual-damascene interconnect structures employing low-k dielectric materials
US6153512A (en) * 1999-10-12 2000-11-28 Taiwan Semiconductor Manufacturing Company Process to improve adhesion of HSQ to underlying materials
US6780783B2 (en) * 2001-08-29 2004-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of wet etching low dielectric constant materials
US20050070103A1 (en) * 2003-09-29 2005-03-31 Applied Materials, Inc. Method and apparatus for endpoint detection during an etch process
DE102005045059B4 (de) 2005-09-21 2011-05-19 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Spule sowie Verfahren zur Herstellung
DE102005045056B4 (de) 2005-09-21 2007-06-21 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Kondensator

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3074713B2 (ja) * 1990-09-18 2000-08-07 日本電気株式会社 半導体装置の製造方法
US5310700A (en) * 1993-03-26 1994-05-10 Integrated Device Technology, Inc. Conductor capacitance reduction in integrated circuits
KR950034755A (enExample) * 1994-05-27 1995-12-28
US5548159A (en) * 1994-05-27 1996-08-20 Texas Instruments Incorporated Porous insulator for line-to-line capacitance reduction
DE69535488T2 (de) * 1994-08-31 2008-01-03 Texas Instruments Inc., Dallas Verfahren zur Isolierung von Leitungen unter Verwendung von Materialien mit niedriger dielektrischer Konstante und damit hergestellte Strukturen
US5559055A (en) * 1994-12-21 1996-09-24 Advanced Micro Devices, Inc. Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance
US5691573A (en) * 1995-06-07 1997-11-25 Advanced Micro Devices, Inc. Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines
US5847464A (en) * 1995-09-27 1998-12-08 Sgs-Thomson Microelectronics, Inc. Method for forming controlled voids in interlevel dielectric

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI714657B (zh) * 2015-12-09 2021-01-01 美商英特爾公司 介電緩衝層

Also Published As

Publication number Publication date
EP0905778A3 (en) 2001-02-07
JPH11163142A (ja) 1999-06-18
US5977635A (en) 1999-11-02
KR19990030133A (ko) 1999-04-26
EP0905778A2 (en) 1999-03-31
CN1213170A (zh) 1999-04-07
CN1134837C (zh) 2004-01-14
KR100544030B1 (ko) 2007-03-02

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MM4A Annulment or lapse of patent due to non-payment of fees