KR100544030B1 - 다중-레벨도전구조물및그의제조방법 - Google Patents

다중-레벨도전구조물및그의제조방법 Download PDF

Info

Publication number
KR100544030B1
KR100544030B1 KR1019980039852A KR19980039852A KR100544030B1 KR 100544030 B1 KR100544030 B1 KR 100544030B1 KR 1019980039852 A KR1019980039852 A KR 1019980039852A KR 19980039852 A KR19980039852 A KR 19980039852A KR 100544030 B1 KR100544030 B1 KR 100544030B1
Authority
KR
South Korea
Prior art keywords
layer
conductive
dielectric
low capacitance
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019980039852A
Other languages
English (en)
Korean (ko)
Other versions
KR19990030133A (ko
Inventor
디르크 토벤
페터 바이간트
Original Assignee
지멘스 악티엔게젤샤프트
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 지멘스 악티엔게젤샤프트 filed Critical 지멘스 악티엔게젤샤프트
Publication of KR19990030133A publication Critical patent/KR19990030133A/ko
Application granted granted Critical
Publication of KR100544030B1 publication Critical patent/KR100544030B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
KR1019980039852A 1997-09-29 1998-09-25 다중-레벨도전구조물및그의제조방법 Expired - Fee Related KR100544030B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/939,208 US5977635A (en) 1997-09-29 1997-09-29 Multi-level conductive structure including low capacitance material
US8/939,208 1997-09-29
US08/939,208 1997-09-29

Publications (2)

Publication Number Publication Date
KR19990030133A KR19990030133A (ko) 1999-04-26
KR100544030B1 true KR100544030B1 (ko) 2007-03-02

Family

ID=25472743

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980039852A Expired - Fee Related KR100544030B1 (ko) 1997-09-29 1998-09-25 다중-레벨도전구조물및그의제조방법

Country Status (6)

Country Link
US (1) US5977635A (enExample)
EP (1) EP0905778A3 (enExample)
JP (1) JPH11163142A (enExample)
KR (1) KR100544030B1 (enExample)
CN (1) CN1134837C (enExample)
TW (1) TW393753B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6627539B1 (en) * 1998-05-29 2003-09-30 Newport Fab, Llc Method of forming dual-damascene interconnect structures employing low-k dielectric materials
US6153512A (en) * 1999-10-12 2000-11-28 Taiwan Semiconductor Manufacturing Company Process to improve adhesion of HSQ to underlying materials
US6780783B2 (en) * 2001-08-29 2004-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of wet etching low dielectric constant materials
US20050070103A1 (en) * 2003-09-29 2005-03-31 Applied Materials, Inc. Method and apparatus for endpoint detection during an etch process
DE102005045059B4 (de) 2005-09-21 2011-05-19 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Spule sowie Verfahren zur Herstellung
DE102005045056B4 (de) 2005-09-21 2007-06-21 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Kondensator
WO2017099736A1 (en) * 2015-12-09 2017-06-15 Intel Corporation Dielectric buffer layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0476625A2 (en) * 1990-09-18 1992-03-25 Nec Corporation A semiconductor device comprising interconnections
EP0703611A1 (en) * 1994-08-31 1996-03-27 Texas Instruments Incorporated Method for insulating metal leads using a low dielectric constant material, and structures formed therewith

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5310700A (en) * 1993-03-26 1994-05-10 Integrated Device Technology, Inc. Conductor capacitance reduction in integrated circuits
DE69531571T2 (de) * 1994-05-27 2004-04-08 Texas Instruments Inc., Dallas Verbesserungen in Bezug auf Halbleitervorrichtungen
US5548159A (en) * 1994-05-27 1996-08-20 Texas Instruments Incorporated Porous insulator for line-to-line capacitance reduction
US5559055A (en) * 1994-12-21 1996-09-24 Advanced Micro Devices, Inc. Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance
US5691573A (en) * 1995-06-07 1997-11-25 Advanced Micro Devices, Inc. Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines
US5847464A (en) * 1995-09-27 1998-12-08 Sgs-Thomson Microelectronics, Inc. Method for forming controlled voids in interlevel dielectric

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0476625A2 (en) * 1990-09-18 1992-03-25 Nec Corporation A semiconductor device comprising interconnections
EP0703611A1 (en) * 1994-08-31 1996-03-27 Texas Instruments Incorporated Method for insulating metal leads using a low dielectric constant material, and structures formed therewith

Also Published As

Publication number Publication date
CN1134837C (zh) 2004-01-14
TW393753B (en) 2000-06-11
EP0905778A2 (en) 1999-03-31
CN1213170A (zh) 1999-04-07
EP0905778A3 (en) 2001-02-07
KR19990030133A (ko) 1999-04-26
JPH11163142A (ja) 1999-06-18
US5977635A (en) 1999-11-02

Similar Documents

Publication Publication Date Title
EP2264758B1 (en) Interconnection structure in semiconductor device
KR100564064B1 (ko) 선택적으로배치된낮은-k유전격리를갖는이중인레이드집적회로구조및형성방법
US5851903A (en) Method of forming closely pitched polysilicon fuses
JP5558662B2 (ja) デバイス、方法（ｍｉｍキャパシタおよびその製造方法）
KR100567976B1 (ko) 퓨즈 구조에 단자 비아를 형성하는 방법 및 금속 퓨즈 구조
US6040628A (en) Interconnect structure using a combination of hard dielectric and polymer as interlayer dielectrics
US6495448B1 (en) Dual damascene process
US6858937B2 (en) Backend metallization method and device obtained therefrom
JP3902507B2 (ja) 半導体素子のリペアヒューズ開口方法
KR100544030B1 (ko) 다중-레벨도전구조물및그의제조방법
US6992392B2 (en) Semiconductor device and method for manufacturing the same
US7041574B2 (en) Composite intermetal dielectric structure including low-k dielectric material
US20010055840A1 (en) Method for fabricating narrow metal interconnects in an integrated circuit using heat and pressure to extrude a metal layer into a lead trench and via/contact
US6974770B2 (en) Self-aligned mask to reduce cell layout area
KR19990063300A (ko) 집적 회로 소자내의 상호 접속부
US6472697B2 (en) Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
CN110867444B (zh) 半导体装置及其制造方法
WO2007027762A2 (en) Metal interconnect structure for integrated ciruits and a design rule therefor
HK1017774A (en) Improved multi-level conductive structure and methods therefor
US8426973B2 (en) Integrated circuit of decreased size
KR100341248B1 (ko) 반도체소자의 저장전극 형성방법
KR100450244B1 (ko) 반도체 소자 및 그 제조 방법
KR20010113520A (ko) 이중 상감 구조 및 커패시터를 가진 집적회로의 제조 공정
KR20020085578A (ko) Ｍｉｍ형 커패시터 제조방법
KR20050002092A (ko) 반도체 소자의 금속배선 형성 방법

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

FPAY Annual fee payment

Payment date: 20130104

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

FPAY Annual fee payment

Payment date: 20140102

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

FPAY Annual fee payment

Payment date: 20141231

Year of fee payment: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

FPAY Annual fee payment

Payment date: 20151217

Year of fee payment: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

FPAY Annual fee payment

Payment date: 20161220

Year of fee payment: 12

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 12

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20180112

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20180112

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000