447041 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（1 ) 本發明係有關一種防止護層損傷之方法，特別有 關於一種預先注入光阻材料於護層之孔隙中，以防止護 層於蝕刻製程發生損傷之方法。 在積體電路（ICs)的應用上，導體、半導體及絕緣 層等材料已被廣泛使用’其中藉由薄膜沈積技術（丁hil] Film Deposition) ’即可將上述各材料分層沈積於待製晶 圓（wafer)表面，以形成半導體元件如電晶體或電容等。 其中為了避免各元件或金屬導體因直接接觸而發 生短路，故必須選擇介電材料或絕緣層以之隔離，而僅 以接觸窗（contact)或介層窗（via)連接。 而在深次微米製程中，由於積體電路積集度 (integration)增加’製作電晶體或電容之基底面積則需 不斷減少以提高密度，因此目前大多採用多層金屬内連 線（multi-level interconnects)之立體架構方式，而另以 内金屬介電層（IMD . Inter-Metal Dielectrics)來作為隔 離各金屬内連線之介電材料，以掩埋式動態隨機存取記 憶體（embedded DRAM)為例，即需要約4至5層之金屬 内連線以進行連接，如第1-4圖所示。 依據第1圖，其顯示一具有多層内連線之半導體結 構剖面圖。該步驟首先為依傳統半導體製程在—石夕基底 表面完成電晶體或電容主體之積體電路結構，如掩埋式 動態隨機存取記憶體100後，接續形成複數層具有輪廟 (topography)深度之金屬線，各層並形成介電層予以隔 離（未顯示），其中最上層金屬線為120，其間則形成複 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公始） {請先閱讀背面之注意事項再填寫本頁) ，袈.447041 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) The present invention relates to a method for preventing damage to the protective layer, and particularly to a method of pre-injecting a photoresist material into the pores of the protective layer to prevent Method for damage to the protective layer during the etching process. In the application of integrated circuits (ICs), materials such as conductors, semiconductors, and insulation layers have been widely used. 'These materials can be deposited in layers by means of thin film deposition technology' The surface of a wafer to form a semiconductor element such as a transistor or a capacitor. Among them, in order to avoid short circuit of each component or metal conductor due to direct contact, a dielectric material or an insulating layer must be selected for isolation, and only connected by a contact or via. In deep sub-micron processes, multi-level interconnects (multi-level interconnects) are currently used due to the increase in integration of integrated circuits. The area of the substrate for making transistors or capacitors needs to be continuously reduced to increase density. ) Three-dimensional architecture, and the inner metal dielectric layer (IMD. Inter-Metal Dielectrics) is used as a dielectric material to isolate the metal interconnects. Take embedded dynamic random access memory (embedded DRAM) as an example. That is, about 4 to 5 layers of metal interconnects are required for connection, as shown in Figures 1-4. According to Fig. 1, there is shown a cross-sectional view of a semiconductor structure having a plurality of interconnects. The first step is to complete the integrated circuit structure of the transistor or the capacitor body on the surface of the Shi Xi substrate according to the traditional semiconductor process. After the buried dynamic random access memory 100, a plurality of layers having a depth of topography are formed. Metal wires, each layer forming a dielectric layer to isolate (not shown), the uppermost metal wire is 120, and a duplicate paper size is formed in the middle of this paper. Applicable to China National Standard (CNS) A4 specification (210X 297). {Please read the back first (Please fill in this page again), 本页.
-IT 4470 4 1 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（2 ) 數個溝槽121。 其次，依據第2圖，為填補該些溝槽121以形成平 坦化’一種低介電係數之介電材料’例如旋塗式玻璃 (SOG)即常被予以採用。 然而有時在多層金屬内連線架構中，最上層金屬 線120具有極長之長度，加以寬窄不一之溝槽121，形 成類似之毛細現象’使液態之旋塗式玻璃（S〇G)14〇被 吸入長溝槽121内而難以填滿。 接續’依據第3圖，在完成上述局部平坦化步驟 後’為避免水氣、鹼金屬離子的侵入或機械性刮傷，必 須另沈積一護層16〇(passivation layer)以保護積體電路 結構。 然而，由於溝槽121並未被旋塗式玻璃140填滿， 連帶導致沈積之護層160產生缺陷，例如形成孔隙 (voids)或鑰匙孔（keyhole)162、164、166。 最後依據第4圖，當完成積體電路結構如掩埋式動 態隨機存取辉憶體並以護層160隔離後，另必須於既定 位置如金屬銲塾（bonding pad)區域及溶絲（fuse)區域（未 顯示），以蝕刻步驟挖開護層，以便進行後續晶片構裝 製程（package)，因此，如圖所示，本步驟為先塗佈一光 阻材料180以覆蓋護層160，接著以曝光顯影製程定義 該光阻材料之圖案，以對所暴露之護層區域進行蝕刻。 其中，由於部份光阻材料注入護層16 0之孔隙 (voids)或鑰匙孔（keyhole)162、164、166，導致光阻 本紙張尺度適用中國國家標孳< CNS > A4規格（2丨0X297公漦) (讀先閲讀背面之注意事項再填寫本頁) .、裝 訂 447041 經濟部中央標準局員工消費合作社印製 A7 ^~~ -__ B7 1五、發明説明（3 ) 材料180表面形成塌陷或傾斜區182、184 ’尤其在塗 佈，阻材料後之軟烤過程（s〇ft-ba㈣將使場陷情形更 為嚴重’再加上多層内連線之架構使護層、各層金屬線 B間’1電層之間的厚度極厚，因此餘刻護層至炼絲區 域所需時間甚長，故形成塌陷或傾斜182、184之光阻 材料180無法作為有效之罩幕㈣叫，導致底下覆蓋之 護層160於蝕刻步驟受到嚴重之損傷。 有鑑於此’本發明之目的即在於預先注入光阻材 料於護層之孔隙中，再塗佈另一層新的光阻材料，以防 止護層於蝕刻製程發生損傷之方法。 為達成上述目的，本發明提供一種防止護層損傷之 方法，包括下列步驟：（a)提供一基底，該基底表面則 形成有複數條金屬内連線及其間之溝槽，·（1>)塗佈一旋 塗式玻璃層（SOG)，以填入該些溝槽；（c)形成一護層以 覆蓋該些金屬内連線、旋塗式玻璃層及基底；（d)塗佈 一光阻材料以覆蓋該護層，且當該護層形成有孔隙時， 部份該光阻材料將注入該些孔隙；及（e)除去位於該護 層表面之光阻材料。 另一種防止護層於蝕刻製程發生損傷之方法，包括 下列步驟：（a)提供一基底，該基底表面則形成有複數 條金屬内連線及其間之溝槽，·（b)塗佈一旋塗式玫璃層 (SOG) ’以填入該些溝槽；（c)形成一護層以覆蓋該些金 屬内連線、旋塗式玻璃層及基底；（d)塗佈一第一光阻 材料以覆蓋該護層，且當該護層形成有孔隙時，部份該 5 本紙張尺度適用中國國家標準（CNS >, Μ規格（2丨0X297公趁） (諳先閱讀背面之注意事項再填寫本頁) .裝----- 訂-IT 4470 4 1 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (2) Several grooves 121. Secondly, according to Fig. 2, to fill the trenches 121 to form a flattened 'a low-dielectric constant dielectric material' such as spin-on-glass (SOG) is often used. However, sometimes in the multilayer metal interconnect structure, the uppermost metal wire 120 has an extremely long length, and wide and narrow grooves 121 are formed to form a similar capillary phenomenon 'making the liquid spin-on glass (SOG) 140 is sucked into the long groove 121 and is difficult to fill. Continuing 'According to Figure 3, after completing the above-mentioned local planarization step', in order to avoid the invasion of water vapor, alkali metal ions or mechanical scratches, a passivation layer 16 must be deposited to protect the integrated circuit structure . However, since the trench 121 is not filled with the spin-on glass 140, defects such as voids or keyholes 162, 164, and 166 are formed in the deposited protective layer 160. Finally, according to Figure 4, when the integrated circuit structure such as buried dynamic random access DRAM is completed and isolated by the protective layer 160, it must also be in a predetermined location such as a metal pad (bonding pad) area and fuse. Area (not shown), the protective layer is excavated by an etching step for subsequent wafer packaging processes. Therefore, as shown in the figure, a photoresist material 180 is first coated to cover the protective layer 160, and then The pattern of the photoresist material is defined by an exposure development process to etch the exposed protective layer area. Among them, part of the photoresist material is injected into the voids or keyholes 162, 164, and 166 of the protective layer 160, which results in the photoresist. This paper is compliant with China National Standards < CNS > A4 specifications (2丨 0X297 Gong) (Read the precautions on the back before filling in this page). Binding 447041 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 ^ ~~ -__ B7 1 5. Description of the invention (3) Material 180 surface Formation of collapsed or inclined areas 182, 184 'especially after coating, resisting the soft baking process after the material (sft-ba㈣ will make the field depression situation more serious') coupled with the structure of the multilayer interconnections to make the protective layer, each layer The thickness between the '1 electrical layers between the metal wires B is extremely thick, so the time required for the protective layer to reach the silk-making area is very long. Therefore, the formation of the collapsed or inclined 182, 184 photoresist material 180 cannot be used as an effective mask. Therefore, the underlying protective layer 160 is severely damaged during the etching step. In view of this, the purpose of the present invention is to inject a photoresist material into the pores of the protective layer before coating another layer of new photoresist material. In order to prevent the protective layer from being damaged during the etching process, In order to achieve the above object, the present invention provides a method for preventing damage to a protective layer, which includes the following steps: (a) providing a substrate, the surface of the substrate is formed with a plurality of metal interconnections and grooves therebetween, (1) ;) Apply a spin-on glass layer (SOG) to fill the grooves; (c) form a protective layer to cover the metal interconnects, the spin-on glass layer and the substrate; (d) apply Place a photoresist material to cover the protective layer, and when the protective layer has pores, part of the photoresist material will be injected into the pores; and (e) remove the photoresist material on the surface of the protective layer. A method for preventing damage to the protective layer during the etching process includes the following steps: (a) providing a substrate, the surface of the substrate is formed with a plurality of metal interconnects and grooves therebetween; (b) applying a spin coating method Rose glass layer (SOG) to fill the trenches; (c) forming a protective layer to cover the metal interconnects, spin-on glass layers and substrate; (d) coating a first photoresist material To cover the protective layer, and when the protective layer has pores, some of the 5 paper sizes are applicable National Standards (CNS >, Μ specifications (2 丨 0X297)) (谙 Please read the precautions on the back before filling this page).
， - - - —^1 I 4470 4 經濟部中央標準局員工消費合作社印裝 A7 B7 五、發明説明（4 ) -- 第一光阻材料將注人該些孔隙；⑷除去㈣該護層表 面之光阻材料；（f)塗佈一第二光阻材料以覆蓋該護 層；及（g)以曝光顯影製程定義該第二光阻材料:圖 案’對該護層進行蝕刻。 為讓本發明之上述和其他目的、特徵、和優點能 更明顯易懂，下文特舉-較佳實施例，並配合所附圖 式，作詳細說明如下： 圖式之簡單說明： 第1至4圖係顯示於護層蝕刻步驟中，塗佈一次光 阻材料以作為罩幕之先前技術之剖面圖。 第5至10圖係顯示於護層蝕刻步驟中，先預注入 光阻材料於護層孔隙中，再塗佈一次光阻材料以作為罩 幕之本發明實施例之剖面圖。 符號說明 100〜基底；120〜上層金屬線；121〜溝槽； 140〜SOG ; 160〜護層；162，164 166〜孔隙；18〇〜光阻 材料；182，184〜光阻塌陷區；2〇〇〜基底；22〇〜上層金 屬線；221〜溝槽；240〜SOG ; 260〜護層； 262,264,266〜孔隙；280〜光阻材料；282,284〜光阻塌陷 區；281〜注入孔隙之光阻材料；3〇〇〜光阻材料。 實施例 請參閱第5至1 〇圖，其顯示本發明之實施例。首 先依據第5圖，其為一具有多層内連線之半導體結構剖 面圖。例如首先為依傳統半導體製程在一基底表面完成 本紙張尺度朝中關家標準（CNS >祕巧（2⑷x29?公楚-)— (請先閱讀背面之注$項再填寫本頁) .广裝· 訂 U704 1 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（5) 電晶體或電容主體之積體電路結構2〇〇，其中基底為一 半導體材貧’如矽（silicon )，為方便說明，在此以 一梦基底為例’接著在石夕基底表面形成一半導體元件 200。如先以淺溝槽（sti : shaUowtrenchis〇Iati〇n)或 區域氧化法（LOCOS)形成之場絕緣層（field insulator )來隔離出主動區（active area )，在主動區 上再另以半導體製程如沈積、微影製程、和離子植入來 形成一具有輪廓（topography)深度之半導體元件2〇〇(未 顯示）’如掩埋式動態隨機存取記憶體（embeded DRAM)。 接續形成複數層具有輪廓（topography)深度之金屬 線’各層並形成介電層予以隔離（未顯示），其中最上層 金屬線為220，其間則形成複數個溝槽221。 其次，依據第6圖，為填補該些溝槽221以形成平 坦化’ 一種低介電係數之介電材料，例如旋塗式玻璃 (SOG)即常被予以採用，由於其以液態旋塗（spinc〇ating) 於晶圓表面，因此具有絕佳之溝填能力（gap fill)，其可 以避免孔洞問題（voids)，並達到局部平坦化之效果β舉 例而言’其可於基底200上方表面先塗一液 態旋塗式玻璃（SOG) ’然後以熱處理方式於400至450 C下之熱爐管中施以固化（curing)，使液態旋塗式玻璃 轉換成低溶劑含量之固態氧化層。 然而，有時在多層金屬内連線架構中，最上層金 屬線220具有極長之長度，加以寬窄不一之溝槽221， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公楚） (諳先閱讀背面之注意事項再填寫本頁) —>-.敢. 訂 147041 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（6 ) 一'' 形成類似之毛細現象’使液態之旋塗式玻璃（§〇(})24〇 被吸入長溝槽221内而難以填滿，如圖所示。 接續’依據第7圖’在完成上述局部平坦化步驟 後’為避免水氣、鹼金屬離子的侵入或機械性刮傷，必 須另沈積一護層260(passivation layer)以保護積體電路 結構’其中由於氮化矽（SiNx)或氮氧化梦（SiOxNy)對水 氣和雜質具有較理想之阻擋能力’因此適合作為護層材 料’另為降低其拉伸應力（tensile stress)及避免沈積時 之反應溫度太高’一般係以電衆化學氣相沈積法 (PECVD)形成。 然而’於溝槽221未被旋塗式玻璃240填滿的場合 中，將可能導致沈積之護層260產生缺陷，例如形成孔 隙（voids)或鑰匙孔（keyhole)262、264、266。 因此依據第8圖，本發明之實施例，係先塗佈一光 阻材料280以覆蓋該護層260，當該護層260形成有孔 隙（voids)或鑰匙孔（key hole)262、264、266 時，部份 光阻材料將注入該些孔隙。此時，光阻材料280之表面 雖因此而產生塌陷或傾斜區282、284，但護層260之 缺陷如孔隙（voids)或錄匙孔（key hole)262、264、266 已為光阻材料所填補。 接著，依據第9圖，除去位於該護層260表面之光 阻材料280，其中，去光阻之方式一般可採用乾式和濕 式去光阻，例如先以氧電漿來剝除光阻，再以有機溶液 去除殘存之光阻或雜質，僅留下填補於護層孔隙262、 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29?公釐） (讀先閱讀背面之注意事項再填寫本頁} .、裝_ -訂_ 44704) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（7) 264、266之剩餘光阻材料28丨，完成防止護層損傷之 結構。 最後’依據第10圖，當完成積體電路結構如掩埋 式動態隨機存取記憶體並以護層260隔離後，另必須於 既定位置如金屬銲墊（bonding pad)區域及熔絲（fuse)區 域（未顯示）’以蝕刻步驟挖開護層，以便進行後續晶片 構裝製程（package)，因此，如圖所示，本步驟於完成防 止護層損傷之結構後’再塗佈一光阻材料3〇〇以覆蓋護 層260 ’接著以曝光顯影製程定義該光阻材料之圖案， 以對暴露之護層區域進行姓刻。 其中，由於部份光阻材料281已預注入護層260之 孔隙（voids)或錄匙孔（keyhole)262、264、266，因此 光阻材料300表面即使在軟烤過程（s〇ft_bake)也不會形 成塌陷或傾斜，故光阻材料300可形成有效之罩幕 (mask)，能忍受長時間之姓刻，達到保護底下覆蓋之護· 層260的效果。 本發明中所應用之物質材料’並不限於實施例所 引述者，其能由各種具恰當特性之物質和形成方法所置 換，且本發明之結構空間亦不限於實施例引用之尺寸大 小° 雖然本發明已以一較佳實施例揭露如下，然其並 非用以限定本發明，任何熟習此技藝者，在不脫離本發 明之精神和範圍内，當可做些許之更動與潤飾，因此本 發明之保護範圍當視後附之申請專利範圍所界定者為 準。 本紙张尺度適用中國國家標準（CNS ) Λ4規格（2I0X297公釐） (請先聞讀背面之注項再填寫本頁) 1-° r'..,---— ^ 1 I 4470 4 A7 B7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (4)-The first photoresist material will be injected into these pores; A photoresist material; (f) coating a second photoresist material to cover the protective layer; and (g) defining the second photoresist material by an exposure and development process: the pattern is used to etch the protective layer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a detailed description is given below in conjunction with the preferred embodiments and the accompanying drawings as follows: Brief description of the drawings: FIG. 4 is a cross-sectional view of the prior art in which a photoresist material is applied once as a mask during the protective layer etching step. Figures 5 to 10 are cross-sectional views of an embodiment of the present invention in which a photoresist material is pre-injected into the pores of the cover layer during the etching step of the cover layer, and then a photoresist material is applied as a mask. Symbol description 100 ~ substrate; 120 ~ upper metal line; 121 ~ trench; 140 ~ SOG; 160 ~ protective layer; 162, 164 166 ~ porosity; 18 ~ photoresist material; 182, 184 ~ photoresistive collapse area; 2 〇〇 ～ Substrate; 22〇 ~ Upper metal wire; 221 ~ Trench; 240 ~ SOG; 260 ~ Cover layer; 262,264,266 ~ Aperture; 280 ~ Photoresistive material; 282,284 ~ Photoresistive slump area; 281 ~ Photoresistor implanted into pores Material; 300 ~ photoresist material. Examples Please refer to Figs. 5 to 10, which show examples of the present invention. First, FIG. 5 is a cross-sectional view of a semiconductor structure having multiple layers of interconnects. For example, the paper standard is first completed on the surface of a substrate according to the traditional semiconductor manufacturing process (CNS > Secret (2⑷x29? Gongchu-)-(Please read the note on the back before filling out this page). Assembling and ordering U704 1 Printed by A7 B7, Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (5) Integrated circuit structure of transistor or capacitor body 200, where the substrate is a semiconductor material such as silicon (such as silicon ( silicon), for convenience of explanation, a dream substrate is taken as an example here, and then a semiconductor element 200 is formed on the surface of the Shixi substrate. For example, a shallow trench (sti: shaUowtrenchis〇Iati〇n) or a local oxidation method (LOCOS) is used. A field insulator is formed to isolate the active area. On the active area, another semiconductor process such as deposition, lithography, and ion implantation is used to form a semiconductor with topography depth. The device 200 (not shown) is like a buried dynamic random access memory (embeded DRAM). A plurality of layers of metal lines having a topography depth are successively formed, and a dielectric layer is formed to separate the layers. (Not shown), in which the uppermost metal line is 220, and a plurality of trenches 221 are formed therebetween. Second, according to FIG. 6, in order to fill the trenches 221 to form a flattening, a low dielectric constant dielectric material For example, spin-on-glass (SOG) is often used. Since it is liquid-coated on the wafer surface, it has excellent gap fill ability, which can avoid hole problems ( voids), and achieve the effect of partial flattening. For example, 'it can be coated with a liquid spin-on glass (SOG) on the upper surface of the substrate 200' and then heat-treated in a hot furnace tube at 400 to 450 C. Curing converts the liquid spin-on glass to a solid oxide layer with a low solvent content. However, sometimes in the multilayer metal interconnect structure, the uppermost metal wire 220 has an extremely long length, which varies in width and width. The groove 221, this paper size applies Chinese National Standard (CNS) A4 specification (210X 297 Gongchu) (谙 Please read the notes on the back before filling in this page) — >-. Dare. Order 147041 Central Standards Bureau of the Ministry of Economic Affairs Shellfish Consumption A7 B7 printed by the company V. Description of the invention (6) A `` formation of a similar capillary phenomenon '' causes the liquid spin-on glass (§〇 (}) 24〇 to be sucked into the long groove 221 and difficult to fill, as shown in the figure In order to avoid the invasion of water vapor, alkali metal ions or mechanical scratches after the completion of the above-mentioned local planarization step according to FIG. 7, a passivation layer 260 must be deposited to protect the integrated circuit. Structure 'wherein silicon nitride (SiNx) or oxynitride (SiOxNy) has an ideal barrier to moisture and impurities', so it is suitable as a coating material' In addition to reduce its tensile stress and avoid deposition When the reaction temperature is too high, it is usually formed by PECVD. However, where the trench 221 is not filled with the spin-on-glass 240, it may cause defects in the deposited protective layer 260, such as the formation of voids or keyholes 262, 264, and 266. Therefore, according to FIG. 8, in the embodiment of the present invention, a photoresist material 280 is first coated to cover the protective layer 260. When the protective layer 260 is formed with voids or key holes 262, 264, At 266, some photoresist material will be injected into these pores. At this time, although the surface of the photoresistive material 280 has collapsed or inclined areas 282, 284, the defects of the protective layer 260 such as voids or key holes 262, 264, and 266 are already photoresistive materials. To be filled. Next, according to FIG. 9, the photoresist material 280 on the surface of the protective layer 260 is removed. Generally, dry and wet photoresist can be used to remove the photoresist. For example, an oxygen plasma is used to strip the photoresist. The organic solution is used to remove the remaining photoresist or impurities, leaving only the pores of the protective layer 262. This paper size applies the Chinese National Standard (CNS) A4 specification (210X29? Mm) (Read the precautions on the back before filling This page}., Installation _-order_ 44704) A7 B7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (7) Residual photoresist material 28 of 264, 266, to complete the structure to prevent damage to the protective layer. Finally, according to Figure 10, after the integrated circuit structure such as buried dynamic random access memory is completed and isolated by the protective layer 260, it must also be in a predetermined position such as a metal bonding pad area and a fuse. Area (not shown) 'The protective layer is excavated in an etching step for subsequent wafer packaging processes. Therefore, as shown in the figure, a photoresist is applied after the structure to prevent damage to the protective layer is completed. The material 300 is used to cover the protective layer 260 ′, and then the pattern of the photoresist material is defined by an exposure and development process to engrav the exposed protective layer area. Among them, since a part of the photoresist material 281 has been pre-injected into the voids or keyholes 262, 264, and 266 of the protective layer 260, the surface of the photoresist material 300 even during the soft baking process (sft_bake). No collapse or tilt will be formed, so the photoresist material 300 can form an effective mask, which can endure long-lasting engraving and achieve the effect of protecting the protective layer 260 underneath. The material materials used in the present invention are not limited to those cited in the examples, they can be replaced by various materials and forming methods with appropriate characteristics, and the structure space of the present invention is not limited to the dimensions cited in the examples. The present invention has been disclosed as follows in a preferred embodiment, but it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. This paper size applies Chinese National Standard (CNS) Λ4 specification (2I0X297mm) (Please read the note on the back before filling this page)