TW388945B - Filp-chip connecting method, filp-chip connected structure and electronic device using the same - Google Patents

Filp-chip connecting method, filp-chip connected structure and electronic device using the same Download PDF

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Publication number
TW388945B
TW388945B TW087111695A TW87111695A TW388945B TW 388945 B TW388945 B TW 388945B TW 087111695 A TW087111695 A TW 087111695A TW 87111695 A TW87111695 A TW 87111695A TW 388945 B TW388945 B TW 388945B
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TW
Taiwan
Prior art keywords
electrode
connection structure
flip
item
patent application
Prior art date
Application number
TW087111695A
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English (en)
Inventor
Naoya Isada
Toyoki Asada
Yoshio Ozeki
Yasuo Amano
Kunio Matsumoto
Original Assignee
Hitachi Ltd
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Publication of TW388945B publication Critical patent/TW388945B/zh

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Description

A7 B7 五、發明説明（1 )
發明背景 I 發明領域 本發明相關於半導體積體電路（I C )晶片面朝下地 直接安裝在電路基體上以達成電連接的結構/方法，以及 使用此結構/方法的電子裝置。更明確地說，本發明相關 於甩來提供基體（例如印刷電路板）與倒裝晶片I C之間 的連接的獨特及新穎的電連接結構/方法。 相關技術的敘述 雖然軟焊料經常用電子裝置的組裝，但是在I C封裝 尺寸減小之下，I C封裝上的連接端子量增加。結果， IC封裝的端子的節距或間隙已減小至軟焊技術無法對精 細電極精確地提供軟焊的程度（例如1 3 0 (微米） )，使得藉著軟焊的組裝變得非常困難且/或就產品良率 而言不可靠》 因此，已開發出將半導體1C直接安裝在基體上的另 一種連接技術。更明確地說，已證明將半導體I C以其主 動側面朝下地安裝在基體上的倒裝晶片安裝方法爲增進電 特性及安裝密度的有效結構/方法》例如，日本專利^告 第He i 6 — 6 6 3 5 5號揭示凸出電極形成在半導體 1 C晶片的端子電極上且導電黏著劑被置於接觸點與基體 上的電極之間的方法。另外，日本專利公告第He i 8 — 2 5 7 4 3 6 9號揭示藉著充塡在倒裝晶片連接結構的半 導體I C晶片與電路基體之間的樹脂的硬化及收縮而加強 導電粒子之間的導電性的方法。 ·- ^Γ· .^1 L— . t婧先背面之注項再填寫本頁) -裝-
•1T -線 經濟部中央標隼局貝工消费合作社印^ 本紙張尺度適/Π中國國家標绛（C'NS ) Λ4現格（210X297公羞） 4- 經濟部中央標準局員工消費合作社印製 A7 B7_ 五、發明説明（2 ) 但是，上述的使用導電粒子的電連接所具有的嚴重問 題爲半導體IC裝置的凸出電極與有機電路基體之間的電 連接電阻W變化。因此，每一連接點的可靠程度也有變化 ，因而此種結構不適用於數目增多的端子及/或許多應用 〇 連接電阻的變化被認爲有一部份是由於半導體IC裝 置所具有的凸出電極的高度的變化所造成，亦即由於有變 化的高度，凸出電極對基體的電極具有有變化的接觸壓力 。如此，即使導電糊被置於凸出電極與基體電極之間，也 不能獲得充分的連接可靠性。因此，爲抑制連接電阻的變 化，抑制或補償凸出電極的高度變化很重要。此在未設置 導電糊時也相同。 至於抑制凸出電極的高度變化的方法，有在半導體 I C裝置安裝在基體上時施加壓力以使凸出電極，基體， 及/或基體電極變形的方法，如此嘗試使任何變化由變形 來吸收或補償，例如日本未審査專利申請案第H e i 8 — 111437號（下文稱爲>437號案）中所揭示。但 是，爲以上述方式變形，需要5 0 g/p i η (克脚 )的壓力，使得當設置的插腳越多時，所需的整體壓力越 大。如此，半導體I C裝置及電路基體受損的可能性增加 。例如，當安裝具有2 0 0支插腳的半導體I C裝置時， 需要50x200g = 10kg (公斤）的壓力。現有的 產品無法可靠地承受此壓力，因此從’4 3 7號案所得的結 果傾向於不使用壓力。對於相當易於變形的例如使用·線凸 本紙張尺度適用中國國家標準（CNS )Λ4規格（210X297公嫠） ---------¢------1T------Φ 1{請先閲讀背面之注意Ϋ項再填寫本頁) -5 - 經濟部中央標準局貞工消费合作社印製 A7 B7 五、發明説明（3 ) 塊（wire bump V結構的產品也是如此。 以下也爲相關的背景資料，包括日本專利公告第 He i 7^5 0726號，日本未審査專利申請案第 He i9 — 107003 號，Yusuke Wada 在 1 9 9 5 年的 I CEMCM第 5 9 至 6 4 頁的「A New Circuit Substrate For MCM-L」，T. Kusagaya等人在 1 9 9 3 年的 I CEMM 年報第 238 至 246 頁的「Flip Chip Mounting Using Stud Bumps And Adhesives For Encapsulation 」，Y. Tomura·等人在 1 9 9 3 年 4 月的 National Technical Report Vol. 39，No· 2第 9 0 至 9 7 頁的「Chip-On-Board Mounting Technology Using Stud-Bump-Bonding Technique」 ，Y. Nakamura 等人在 1 9 9 5 年的 I CEMCM 第 302 至 3 0 7 頁的「Advanced LSI Package Using Stud-Bump-Bonding Technology <CSP(Chip Size Package)〉」 ，K. Matsuda 等人在 1 9 9 7 年的 International Conference On Multichip Modules第 9 2 至 9 7 頁的「Simple Method For Flip-Chip Bonding On A Resin Substrate」，K. Tanaka 等人在 1 9 9 6 年 I CEMCM 年報第 3 6 9 至 374 頁的「A Fine-Pitch Lead-Less-Chip Assembly Technology With The Built-Up PCB 」，J.G. Aday等人在1996年ICEMCM年報第239 至 244 頁的「A Comparative Analysis Of High Density PWB Technologies」。 發明槪說 - 本紙張尺度通用中國國家標率（CNS ) Λ4規格（210X297公藿） ---------¢------ir------^ (請先閲讀背面之注意事項再填寫本頁) -6- A7 B7 五、發明説明（4 ) 本發明的目的爲解決習知技術的問題，亦即提供具有 用來吸收或補償凸出電極的高度的任何變化的獨特及新穎 的結構的倒裝晶片連接結構/方法，以及提供使用此結構 /方法的電子裝置。 本發明之上述目的之達成是經由一種倒裝晶片連接結 構，包含半導體稹體電路（I C )裝置，具有第一電極； 電路基體，具有相應於第一電極的第二電極；及導電糊， 設置在第一電極的至少一部份與第二電極的至少一部份之 間以及相鄰於第一及第二電極設置，導電糊內具有用來增 進第一電極與第二電極之間的電連接的導電粒子，其中在 設置在第一電極與第二電極之間的導電糊內的導電粒子的 密度大於在相鄰於第一及第二電極設置的導電糊內的導電 粒子的密度。 . 經滴部中次梯準局貝工消费合作社印裝 _(請先聞讀背面之注意Ϋ項再填寫本頁) 本發明之上述目的之達成是另外經由一種倒裝晶片連 接結構，包含半導雔積體電路（I C)裝置，具有第一電 極；電路基體，具有相應於第一電極的第二電極；及導電 糊，在第一電極的至少一部份與第二電極的至少一部份上 ，且其內具有用來增進第一電極與第二電極之間的電連接 的導電粒子，其中導電糊在直接設置在第一電極與第二電 極之間的區域所具有的導電粒子密度比在第一電極及第二 電極的其他部份所具有的導電粒子密度高。 本發明之上述目的之達成也藉著用來將具有凸出電極 的半導體IC裝置安裝在具有絕緣層及電極的電路基體上 的倒裝晶片連接方法，此方法包含藉著加熱軟化絕緣·層且 本紙張尺度適用中國围家標淨·（ CNS ) Λ4規格（210X297公釐） 經滴部中央標隼扃貝工消費合作社印$!. A7 B7_ 五、發明説明（5 ) 藉著加壓使電極及軟化的絕緣層變形的步驟。 另外，本發明之上述目的之達成是藉著用來將具有凸 出電極的平導體IC裝置經由具有導電粒子及熱塑性樹脂 的導電糊而安裝在電路基體上的倒裝晶片連接方法，此方 法包含藉著加熱軟化導電糊且藉著加壓使軟化的導電糊所 具有的熱塑性樹脂繞凸出電極移動的步驟》 另外，本發明之上述目的之達成是藉著用來將具有凸 出電極的半導體IC裝置經由具有導電粒子及熱塑性樹脂 的導電糊而安裝在具有絕緣層及電極的電路基體上的倒裝 晶片連接方法，此方法包含的步驟爲藉著加熱軟化導電層 及導電糊，藉著加壓使電極及軟化的導電層變形，以及藉 著加壓使軟化的導電糊所具有的熱塑性樹脂繞凸出電極移 動' - 藉著加熱，電路基體所具有的絕緣層軟化，而藉著加 壓，絕緣層及電極變形，因而吸收或適應凸出電極的髙度 的任何變化，並且因而抑制連接電阻的變化。 另外，藉著加熱，導電糊中的熱塑性樹脂軟化，而藉 著加壓，軟化的熱塑性樹脂藉著被擠出而繞凸塊移動。如 此，在設置在基體上的每一電極與凸塊之間的導電糊中， 導電粒子以髙密度存在，使得導電粒子濃密存在的部份可 補償半導體I C裝置所具有的凸出電極的高度變化。因此 ，相應於凸出電極的高度，可調整導電粒子濃密存在的部 份的高度。更具體地說，此揭示中所用的術語「濃密存在 」.指的是每單位體稹的導電糊中存在的導電粒子數目·，並 本紙張尺度適用中國國家標埤（CNS ) Λ4現格（210X297公釐） ---------装------1T—-----0 ·(请先Μ讀背面之注意事項再填寫本頁) -8 - A7 ______B7 五、發明説明（6 ) 且其指示設置在凸塊與基髏上的電極之間的導電糊（具有 高導電粒子密度）與凸塊周圍存在的導電糊（具有較低的 導電粒子密度）比較的狀態。 藉著形成導電粒子濃密存在在每一凸出電極與基體電 極之間的部份，可減小電連接電阻。 另外，在未被捕捉在每一凸出電極與基體上的接線之 間而被轉移靠近凸出電極的末端的導電糊中，藉著具有相 當低密度的導電粒子的部份來造成應力鬆弛，因而可達成 高度可靠的連接。 當電路基體的電極由於如上所述的加壓而變形時，有 可能產生斷開的問題。因此，最好選擇性地組合電路基體 的變形與安裝時形成在導電糊中的導電粒子濃密存在的部 份。 ' 經濟部中央標準局貝工消资合作社印^ -{請先閲讀背面之注意Ϋ項再填寫本 在任何情況中，藉著組合加熱與安裝時的加壓，可藉 著較小的壓力（與不使用本發明相比）來抑制凸出電極高 度的分散。另外，本發明具多種用途，因爲不論加熱與加 壓同時或獨立執行均不會有問題。亦即，只要在絕緣樹脂 及/或熱塑性樹脂由於加熱而軟化之下施加壓力即不會有 問題。 從以下形成本發明的此揭示的一部份的連同圖式的較 \ 佳實施例的詳細敘述及申請專利範圍可使本發明的上述及 其他目的，優點，操作方式，新穎特徵，以及較佳的瞭解 更顯明。雖然以上及以下所述及所示的揭示集中於揭示本 發明的較佳實施例，但是必須瞭解其只是說明及舉例用而 本紙張尺度適用中國围家標埤（CNS ) Λ4規格（210X297公釐） -9- 經濟部中次榡準扃負工消费合作社印繁 A7 B7五、發明説明（7 ) 非加以限制，本發明的精神及範圔只受申請專利範圍的用 語的限制。 圖式的簡要敘述 圖1A至1C爲根搛本發明的實施例的連接結構的剖 面圖。 圖2爲顯示根據本發明的實施例的安裝方法的流程圖 〇 圖3包含顯示本發明的結構/方法中凸塊形成階段的 剖面及平面圖。 圖4包含顯示本發明的結構/方法中導電糊塗覆階段 的剖面圖。 圖5及6爲顯示本發明的結構/方法中充塡樹脂施加 階段的剖面圖》 圖7爲顯示本發明的結構/方法中加熱及加壓階段的 剖面圖。 圖8爲在完成圖2的安裝方法後的最終連接結構的剖 面圖。 圖9 A爲圖6的充塡樹脂施加階段的二凸塊/電極區 域的放大剖面圖。 圖9 B爲接近圖7的加熱及加壓階段的開始的二凸塊 /電極區域的放大剖面圖。 圖9 C爲接近圖7的加熱及加壓階段的結束及/或圖 8的最終連接結構的二凸塊/電極區域的放大剖面圖-。 請 先 閱 讀 背 面 之 注 項 再 旁 裝 訂 線 本紙張尺度適用中國围家標率（C’NS ) Λ4規格（210X297公羞） -10- 經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（8 ) 圖10爲顯示本發明與不利的方式之間的比較的照片 主要元件對照表 1 半導體I C裝置 2 凸出電極（凸塊） 3 導電糊 4 導電粒子 5 熱塑性樹脂 6 電路基體 7 電極 7 D 電極 8 絕緣樹脂（層） 8 D 絕緣樹脂（層） 9 充塡樹脂 ---------择------1T------.^ (請先聞讀背面之注意事項再填寫本頁) 1 0 區域 3 2 凸塊形成 階 段 3 4 凸塊形成 階 段 3 6 凸塊形成 階 段 3 8 凸塊形成 階 段 4 0 乳狀隆起物 4 2 托盤 5 0 凸塊形成 階 段 本紙張尺度通用中國國家標率（rNS ) Λ4規格（210 X 297公釐） -11 - A7 ___B7_ 五、發明説明（9 ) 本發明的較佳實施例的詳細敘述 相同的參考數字及字元在適當時被用來在不同的圖中 指示相同 >相應，或類似的組件。另外，在以下的詳細敘 述中，以括號表示舉例的尺寸/値/範圍，但是本發明不 受限於此》 以下參考圖式敘述本發明。更具體地說，圖1 A至 1C顯示完成將倒裝晶片裝載在基體（例如有機基體）上 之後的本發明的倒裝晶片連接結構的剖面（於不同的放大 率）。在圖ΓΑ至1C中，參考數字1表示半導體1C裝 置，數字2表示設置（例如以1 3 Ο μιη的節距）在半導 體IC裝置的電極上的凸出電極（凸塊），數字3表示設 置在各凸塊2上的導電糊，數字4表示導電糊3中所含的 導電粒子，數字5表示導電糊3中所含的熱塑性樹脂，數 字6表示電路基體，數字7表示設置成電路基體6的一部 份的電極，數字8表示基體所具有的絕緣樹脂，而數字9 表示具有預定的硬化收縮力的下方充塡樹脂。 經濟部中央標準局負Η消费合作社印製 ·(請先閲讀背面之注意事項再填寫本頁) 充塡樹脂9最好爲具有環氧丙烯酸酯，酚環氧，或氰 基丙烯酸成爲主要組份的材料。特別是在電路基體6是由 有機物質形成時，環氧丙烯酸酯或酚環氧較佳。另外，充 塡樹脂9的玻璃化溫度最好比半導體I C裝置1的常態操 作溫度髙，使得充塡樹脂9不會在半導體I C裝置1的正 常操作期間軟化。熱塑性樹脂5及絕緣樹脂8最好爲在充 塡樹脂9的硬化溫度軟化的材料。 凸出電極（凸塊）2最好爲金凸塊，銀凸塊，銀錫 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） -12- 經濟部中央標準局負-Χ消费合作社印^ A7 _： _B7 五、發明説明（10 ) 合金凸塊，或類似者·導電糊3最好爲具有金粉末的熱塑 性樹脂（金粉末最好具有小片的形狀，平均粒子尺寸最好 在厚度爲1.至2 且直徑爲2至1 0 的範圍內，且 以在9 2至9 7wt% (重量百分比）的範圍內的濃度包 含在樹脂內），具有銀粉末的熱塑性樹脂（銀粉末最好具 有小片的形狀，平均粒子尺寸最好在厚度爲1至2 且 直徑爲2至1 0 # m的範圍內，且以在8 6至9 4w t % (重量百分比）的範圍內的濃度包含在樹脂內），或是由 銀鉑合金粉末所組成的材料（銀鉑合金粉末最好具有小片 的形狀，平均粒子尺寸最好在厚度爲1至2 且直徑爲 2至1 0//m的範圍內，且以在8 7至9 5wt% (重量 百分比）的範圍內的濃度包含在樹脂內）^ 以下參考圖2至9敘述用來將具有凸出凸塊2的半導 體I C裝置1安裝在基體電極7上的結構/方法。更具體 地說，凸出凸塊2是根據引線凸塊方法或類似者而產生在 半導體1C裝置1的電極上（圖2的步驟1，見圖3)。 更具體地說，圖3包含顯示本發明的結構/方法中凸塊形 成階段的剖面圖及平面圖。 '' 在圖3中，參考數字3 2表示首先工具接近半導體 I C裝置1的凸塊形成階段，而參考數字3 4表示凸塊材 料被施加（例如經由加熱/熔化）在半導體I C裝置1的 表面以形成凸塊的主要部份的凸塊形成階段。其次，參考 數字3 6及3 8表示在工具移離半導體I C裝置1之下中 斷加熱以形成尖頭乳狀隆起物4 0的凸塊形成階段。·最後 本紙張尺度適用中國國家標率（CNS ) Λ4現格（2丨0X297公釐） ---------装------1T------^ ·<請先Μ讀背面之注意事項再填寫本页) -13- 經濟部中夾標準局另工消費合作社印繁 A7 _B7 五、發明説明（H) ，參考數字5 0表示另一工具被壓抵於尖頭乳狀隆起物 4 0且/或被加熱以使尖頭乳狀隆起物4 0變平坦而形成 凸塊的一小部份的凸塊形成階段。一旦在半導體1C裝置 1的所有適當位置處形成凸塊（凸出5 0 ;/m)，半導體 1C裝置1顛倒（見圖3中間的圖所示），使得所形成的 凸塊可被壓抵於具有用來與凸塊相應對接的電極（例如襯 墊及/或導電線）的基體。圖3中從底部算起的第二圖表 示裝有凸塊且顛倒的半導體I C裝置1的剖面圓，而圖3 底部的圖表示沿著半導體IC裝置1的周邊的凸塊圖型的 例子（具有1 3 0 /zm的凸塊節距）的平面圖。 其次，圖4包含顯示本發明的結構/方法中的導電糊 塗覆階段的剖面圖。由導電粒子4及熱塑性樹脂5構成的 導電糊3塗覆在托盤4 2上，成爲具有指定厚度的層L ( 圖4頂部的圖），且經由將凸出凸塊2的末端沒入及/或 壓入至層L內（見圖4中間的圖）而轉移導電糊3 (圖2 的步驟2)。可將導電糊層及/或凸出凸塊2加熱以便導 電糊層更容易轉移至凸塊2上。然後，將半導體I C裝置 1移離托盤4 2。結果，導電糊層L的一部份轉移且&持 塗覆（例如2 0至4 0 //m)在每一凸塊2上，成爲導電 糊部份3(圖4下方的圖 圖5及6爲顯示本發明的結構/方法中充塡樹脂施加 階段的剖面圖。更具體地說，電路基體6上要安裝半導體 1C裝置1的部份接收需要量的充塡樹脂9 (圖2的步驟 3,見圖5)。然後，半導體1C裝置1安裝成使得·想要 本紙悵尺度適元中國國家標嘩（（，NS ) A4規格（210X297公藶) ~ -14 - ---------^------1T------.^ I：請先S·讀背面之注意事項再填寫本頁) 經满部中央標準局βη消費合作社印繁 A7 B7 五、發明説明（12 ) 的凸出凸塊2的位置與電路基體6的電極7的位置對準， 並且被推向塗覆有充塡樹脂9的電路基體6(圖2的步驟 4,見圖6)。圖9A爲圖6的二凸塊/電極區域的放大 剖面圖，且顯示充塡樹脂9仍然存在在凸塊/電極對之間 。圖9A另外顯示導電糊部份3於其整個部份仍然具有大 致相等的導電粒子分佈。另外，電極7及絕緣樹脂8仍然 互相分開。 圖7爲顯示本發明的結構/方法中的加熱及加壓階段 的剖面圖》更具體地說，在施加壓力P(例如爲30克/ 凸塊X 2 0 0凸塊=6公斤）以將電路基體6向半導體 I C裝置1偏壓下，基體6及半導體I C裝置1的至少之 —被加熱至超過充塡樹脂9的熔化/軟化溫度的溫度•維 持此加壓/加熱直到充塡樹脂9中產生充分的黏著力（圖 2的步驟5，見圖4) »例如，含有環氧丙烯酸酯成爲主 要組份的樹脂如果被加熱至1 8 0 °C 3 0秒鐘，則會充分 地熔化/軟化，使得不會有任何空洞產生在樹脂中。圖 9 B爲圖7的階段的二凸塊/電極區域的放大剖面画，且 顯示充塡樹脂9被擠出凸塊/電極對之間。此很重要，'因 爲如此一來電絕緣的充塡樹脂9便不會妨礙凸塊/電極對 之間的導電（亦即不會成爲污染物）。 圖9 B另外顯示導電糊部份3開始在其整個部份具有 不相等的導電粒子分佈。更具體地說，當導電凸塊2的小 部份接近電極7時，充塡樹脂內的較大導電粒子4被擠在 凸塊/電極對之間，且/或比較小的（亦即較液態熔·化/ 本紙張尺度適用中國S家標峰（（’NS ) Λ4規格（210X297公嫠） ---------餐------,1T------0 一{請先閣讀背面之注意事項再填寫本頁) -15- 經濟部中泱棉準局K3C.T消於合竹.ii印絮 A7 _ B7_ 五、發明説明（13 ) 軟化的）熱塑性樹脂粒子移動得慢。因此，較小的熱塑性 樹脂粒子被擠而移動至在電極7與凸塊2的主要部份之間 的環繞凸塊的小部份（亦即乳狀隆起物）的周邊區域。其 結果爲在就夾在或擠在電極7與凸塊2的小部份（亦即乳 狀隆起物）之間的區域D中有較高的導電粒子密度（見圖 1C)，而在其他蓝域L(亦即未夾住或未携住的區域） 由於被擠至該處的樹脂粒子的稀釋而具有較低的導電粒子 密度。 此非常有利，因爲髙濃度的導電粒子層增進凸塊/電 極對之間的導電，同時減小凸塊/電極對的接觸電阻。在 本發明中，熱塑性樹脂5，導電粒子4，加熱，加壓，與 時間參數的組合應選擇成導致小於3 0毫歐姆（πιΩ)的 接觸電阻，而選擇成導致小於1 ΟπιΩ的接觸電阻更好。 更具體地舉例而言，如果導電糊3爲具有銀鉑合金粉末的 熱塑性樹脂（銀鉑合金粉末具有小片的形狀，平均粒子尺 寸大約爲厚度爲1 //m且直徑爲2至1 0 ，且以9 0 wt%(重量百分比）的原始濃度包含在樹脂內），則於 1 5 0°C加熱且以2 0克/凸塊加壓1 0秒鐘會導致ίΕ就 夾在或擠在電極7與凸塊2的小部份（亦即乳狀隆起物） 之間的區域D中有大於9 7w t %的高密度導電粒子濃度 ，而在其他區域（亦即未夾住或未擠住的區域）中有8 9 至9 〇w t %的較低密度的導電粒子濃度，並且會導致大 約4 0 πι Ω的接觸電阻。 本發明中的加壓很重要，因爲此加壓傾向於改善·凸塊 本紙張尺度適用中國S家標埤（（'NS ) Λ4規格（210X297公釐） ---------装-----—.η------0 -(請先聞讀背面之注意事項再填寫本頁) -16- 經潢部中决標準局妇Μ消资合作社印？农 A7 B7 五、發明说明（14 ) /電極對之間的接觸電阻（降低）及導電性（提高）。亦 即，如果未加壓以將大量（即使不是大約全部）的熱塑性 樹脂5從就夾在及擠在電極7與凸塊2的小部份（乳狀隆 起物）之間的區域D擠出，則此種非導電性的熱塑性樹脂 會作用成爲降低凸塊/電極對之間的導電性且提高其間的 電阻的污染物。已證明熱塑性樹脂5，導電粒子4，加熱 ，與時間參數的一種組合在未加壓下導致大約4 ΟπιΩ的 接觸電阻，而加壓的組合導致大幅改善的小於1 ΟπιΩ的 接觸電阻。 在加熱/加壓的早期階段（見圖9 Β)，電極7及絕 緣層（樹脂）8未變形。於加熱/加屋的後期階段（見圔 9 C )，凸塊2，電極7 (例如18#m厚），及/或絕 緣層8可能會變形，因爲在壓力繼續施加之下，這些組件 之間的自由空間用盡而容許組件之間的干涉。更具體地說 ，圖9 C中左側的凸塊/電極對顯示出電極7 D及絕緣層 部份8 D已變形。 以下討論變形及濃密導電粒子層的優點/重要性。更 具體地說，當凸塊2形成在半導體I C裝置1上時，&於 製造上的限制，凸塊從半導體I C裝置1的表面測量起的 延伸距離不一致，亦即有非平面狀的偏差或變化，例如 ±7/zm。類似地，當電極7形成在基體6上時，由於製 造上的限制，電極從基體6的表面測量起的延伸距離不一 致，也有非平面狀的偏差或變化，例如±7 //m。圖9A 至9 C顯示左側電極7具有高於右側電極的髙度的情.況。 本紙張尺度適用中國囤家標绛（（’NS ) Λ4規格（210Χ297公着） 裝 I ~~訂H ^1 線 _(請先閲讀背面之注意事項再填寫本頁) -17- 經淆部中决摞準局兵-Τ消资合作·社印顰 A7 B7 五、發明説明（15) 因此，左側的凸塊/電極對在加熱./加壓階段用盡自由空 間，並且遭受干涉及碰撞/扭曲。另一方面，右側的凸塊 /電極對在二者之間具有充分.的自由空間，因而不發生碰 撞/扭曲。本發明的濃密導電粒子層的一重要功能爲此層 可調整地充塡在每一凸塊/電極對之間的任何自由空間中 ，以改善凸塊/電極對之間的接靥電阻（降低）及導電性 (提高）。濃密導電粒子層的厚度（亦即圖1中的H*)對 於扭曲的凸塊/電極對與間隔分開的凸塊/電極對均相同 ，提供對接的凸塊/電極對之間的調整的主要是凸塊2， 電極7(例如18厚），及/或絕緣層8的機械變形 〇 雖然在本發明中的凸塊2，電極7，及/或絕緣層8 在加壓期間遭受某些變形，但是所遭受的變形小於許多其 他不利方案所遭受的變形。更具體地說，圖1 0爲顯示本 發明與不利方案之間的比較的照片。圖1 0下方的照片顯 示不利的方案B。在此方案中，具有導電粒子的熱固性（ 相對於熱塑性）層塗覆在導電凸塊上，並且設定成由於升 髙的溫度而硬化。 ' 因爲使用硬化（亦即非撓性）的熱固性層，所以在加 壓期間必須施加高壓（與本發明相比），造成若干不利的 結果。更具體地說，高壓造成導電凸塊上的硬化熱固性層 破裂及移動至導電凸塊周圍的區域。因此，此破裂的熱固 性層不能改善凸塊/電極對之間的接觸電阻（降低）及導 電性（提高）。除了熱固性餍的損壞/破裂外，髙壓·造成 本紙張尺度適用中國Κ家標啤（rNS ) Λ4規格（210X297公釐） ---------装-- 請先时讀背面之注意事項再填寫本頁) ,ιτ 線 18 - 經濟部中女標準局另-T消费合作社印褽 A7 B7 五、發明説明（16 ) 凸塊2，電極7〜及/或絕緣暦8的極度扭曲。更具體地 說，圖1 0下方的照片顯示基體電極及基體均極度扭曲。 此極度扭曲很不利而可能造成許多問題，例如基體電極從 基體剝落，基體電極破裂或斷裂，間隙的徹底改變而造成 基體電極與基體接地平面（圖10下方的照片中直的較淺 的彩色條）之間的阻抗的徹底改變，及/或基體電極與基 體接地平面之間的短路。相比之下，如圖1 0上方的照片 中所示的本發明的結構遭受較小的變形，因此較不可能發 生剝落，破裂，斷裂，阻抗改變，及/或短路。 另外，本發明也利用下方充塡樹脂9及/或導電糊3 中的殘餘應力及/或區域L(圖1C)中的導電糊的撓性 來吸收連接結構中的線性膨脹/收縮應力，以導致具有良 好的膨脹/收縮循環數目（例如1000)的結構？更具 體地說，充塡樹脂在冷卻/固定期間的收縮（在製造期間 )在連接結構內導致殘餘應力。另外，在冷卻/固定期間 的繼續加壓也會增加殘餘應力。已發現此殘餘應力及/或 區域L(圖1C)中的導電糊的撓性在結構後續的正常操 气 作的加熱/冷卻期間有利地吸收線性膨脹/收縮應力。因 此，可確保增加的可靠性。 另外，本發明的加熱階段很有利。更具體地說，形成 在有機電路基體6上的絕緣樹脂8由於加熱而軟化，使得 有機電路基體6的電極7及絕緣樹脂8可在需要時在與無 任何加熱下嘗試變形的情況相比相當低的壓力下變形*另 外，設置在凸出凸塊2與有機電路基體6的電極7之間的 本紙張尺度適用中國國家標埤（（’NS ) Λ4現格（210X297公釐〉 ----------^------、u------0 '{請先閲讀背面之注意事項再填寫本頁) • 19 · 經湞部中央標準局t3cJ·消费合作社印4,1木 A7 __B7_ 五、發明説明（17 ) 導電糊3中的熱塑性樹脂5由於加熱而軟化，使得軟化的 熱塑性樹脂環繞凸出電極2被壓力擠出，因而產生導電粒 子4具有_密濃度的區域10。 另外，經由上述過程，可獲得圖1所示的安裝結構。 在圖1所示的倒裝晶片連接結構中，凸出凸塊2及電極7 的高度的任何變化是由濃密的導電粒子層及/或由有機電 路基體6的電極7及樹脂8的變形來補償，因而可增進製 造期間的良率。另外，藉著在每一凸塊/電極對之間形成 具有高密度的導電粒子4的層，可實現低電阻/高導電性 的連接。另外，藉著在加上充塡樹脂9時對半導體I C裝 置1與電路基體6之間的充塡樹脂9加壓及加熱以硬化樹 脂，可確保可靠性》 雖然根據本發明，半導體I C裝置1在充塡樹脂9施 加於基體後才安裝，但是也可先將半導體I C裝置1安裝 在有機電路基體6上，然後以充塡樹脂9充塡二者之間的 間隙。或者，也可以導電糊3塗覆有機電路基體6的電極 7而非凸塊2。另外，凸出凸塊2不限於引線凸塊，而可 爲一般的擠製，衝屋凸塊或類似者。 ％ 如上所述，在形成本發明的具有半導體I C裝置1及 有機電路基體6的倒裝晶片結構時，可在對基體不附加任 何特殊製程或任何特殊材料下以高良率建構穩定的低連接 電阻的連接結構。結果，可實現可廣泛地用於數位及類比 I C的低成本的倒裝晶片結構。如此，本發明具有髙應用 性來在任何產品領域中實現低成本及高功能，例如從·高速 本紙張尺度通用中國囤家標埤((、NS ) Λ4規格（2丨0X297公嫠) ---------餐------<τ------0 <請先閲讀背面之注意事項再填寫本頁) -20- A7 ____B7 五、發明説明（18) 訊號傳輸系統到二般消費者的電子設備。 雖然已參考若干所示的較佳實施例來敘述本發明，但 是必須瞭禅熟悉此項技術者可達成在本發明的原理的精神 及範圍內的無數種其他的修正及實施例。更具體地說，在 不離開本發明的精神下，在上述的揭示，圖式，及附隨的 申請專利範圍的範圍內可對結構的組件部份進行合理的變 化及修正。除了組件部份及/或結構的_化及修正外，對 於熟悉此項技術者而言另外的利用也很明顯。例如，本發 明的用來補償電極的非平面狀的導電糊，加熱，及加壓的 安排也可應用於半導體I c裝置以外的較大環境，例如可 應用來補償叠合的印刷電路板對印刷電路板的連接之間的 非平面狀連接。 (請先閱«背面之注意事項再填寫本頁) 經遗部中决標準局負J-消资合作社印裝 本紙張尺度適用中國囤家標啤（CNS ) Λ4規格（210X297公釐） 21

Claims (1)

  1. 經濟部中央橾準局負工消费合作社印«. A8 B8 C8 __ D8 六、申請專利範園 1 ·—種連接結構，包含： 第一組件，具有第一電極； 〆 第二铒件，具有相應於該第一電極的第二電極：及 導電糊，設置在該第一電極的至少一部份與該第二電 極的至少一部份之間以及相鄰於該第一及第二電極設置， 該導電糊內具有用來增進該第一電極與該第二電極之間的 電連接的導電粒子， 其中在設置在該第一電極與第二電極之間的該導電糊 內的導電粒子的密度大於在相鄰於該第一及第二電極設置 的該導電糊內的導電粒子的密度》 2 ·—種連接結構，包含： 第一組件，具有第一電極； 第二組件，具有相應於該第一電極的第二電極；.及 導電糊，在該第一電極的至少一部份與該第二電極的 至少一部份上，且其內具有用來增進該第一電極與該第二 電極之間的電連接的導電粒子， 其中該導電糊在直接設置在該第一電極與該第二電極 之間的區域所具有的導電粒子密度比在該第一電極及該第 二電極的其他部份所具有的導電粒子密度高。 3 · —種倒裝晶片連接結構，包含： 半導體積體電路（I C)裝置’具有第一電極； 竜路基體，具有相應於該第—電極的第二電極：及 導電糊，設置在該第一電極的至少—部份與該第二電 極的至少一部份之間以及相鄰於該第一及第二電極設置’ 本紙張尺度逋用中國國家樣準（CNS ) A4规格（210 X 297公釐）^ ---------餐------tr------^ (請先閱讀背面之注項再填寫本買)
    經濟部中央標準局負工消费合作社印策 夂、申請專利範圍 胃導電糊內具有用來增進該第一電極與該第二電極之間的 電連接的導電粒子， 其中在設置在該第一電極與第二電極之間的該導電糊 內的導電粒子的密度大於在相鄰於該第一及第二電極設置 的該導電糊內的導電粒子的密度》 4·如申請專利範圍第3項所述的倒裝晶片連接結構 ’其中該第一電極爲引線接合凸塊，擠製凸塊，電鍍凸塊 ’蝕刻凸塊，及模衝壓凸塊的至少之一的形式的凸出電極 〇 5·如申請專利範圍第3項所述的倒裝晶片連接結構 ，其中該第一電極爲金凸塊，銀凸塊，及銀/錫合金凸塊 的至少之一。 6·如申請專利範圍第3項所述的倒裝晶片連接結構 ，其中該第二電極爲電極襯墊及電極線的至少之一的形式 的印刷電路電極的至少之一。 7 ·如申請專利範圍第3項所述的倒裝晶片連接結構 ，其中該導電糊包含熱塑性樹脂及熱塑性黏著劑的至少之 一，而該導電糊內的該導電粒子爲金粉末，銀粉末，及銀 鉑合金粉末之一。 8 ·如申請專利範圍第3項所述的倒裝晶片連接結構 ，其中在設置在該第一與第二電極之間的該導電糊內的該 導電粒子的密度爲至少9 7重量百分比（wt%)的濃度 〇 9.如申請專利範圍第3項所述的倒裝晶片連接結構 ---------^------ir------终 t請先背面之注$項再填寫本茛) 本紙張尺度逋用中國困家揉率（CNS ) A4规格（210X297公釐） -23- A8 B8 C8 D8 六、申請專利範園 ’其中互相電連接的該第一與第二電極之間的接觸電阻小 於5 〇毫歐姆。 1 0 ·.如申請·專利範圍第3項所述的倒裝晶片連接結 構’其中互相電連接的該第一與第二電極之間的接觸電阻 小於4 〇毫歐姆。 11·如申請專利範圍第3項所述的倒裝晶片連接結 構’其中互相電連接的該第一與第二電極之間的接觸電阻 小於3 〇毫歐姆。 1 2 ·如申請專利範圍第3項所述的倒裝晶片連接結 構’其中互相電連接的該第一與第二電極之間的接觸電阻 小於2 〇毫歐姆。 1 3 ·如申請專利範圍第3項所述的倒裝晶片連接結 構’其中互相電連接的該第一與第二電極之間的接觸電阻 小於1 0毫歐姆》 1 4 · 一種電子裝置，含有如申請專利範圍第3項所 述的倒裝晶片連接結構。 1 5 · —種倒裝晶片連接結構，包含： 經濟部中央標率局貝工消费合作社印*. 半導體積體電路（1C)裝置，具有第一電極： 電姑基體，具有相應於該第一電極的第二電極；及 導電糊，在該第一電極的至少一部份與該第二電極的 至少一部份上，且其內具有用來增進該第一電極與該第二 電極之間的電連接的導電粒子， 其中該導電糊在直接設置在該第一電極與該第二電極 之間的區域所具有的導電粒子密度比在該第一電極及該第 本紙張尺度適用中•國家椹率（CNS > A4规格（210X297公釐) -24- 經濟部中央橾率局貝工消费合作社印«. A8 B8 C8 六、申請專利範園 二電極的其他部份所具有的導電粒子密度高。 16·如申請專利範圍第15項所述的倒裝晶片連接 結構，其中__第一·電極爲引線接合凸塊，擠製凸塊，電鍍 凸塊，蝕刻凸塊，及模衝壓凸塊的至少之一的形式的凸出 電極。 17·如申請專利範圍第15項所述的倒裝晶片連接 結構，其中該第一電極爲金凸塊，銀凸塊，及銀/錫合金 凸塊的至少之一。 1 8 ·如申請專利範圔第1 5項所述的倒裝晶片連接 結構，其中該第二電極爲電極襯墊及電極線的至少之一的 形式的印刷電路電極的至少之一。 1 9 ·如申請專利範圍第1 5項所述的倒裝晶片連接 結構，其中該導電糊包含熱塑性樹脂及熱塑性黏著劑的至 少之一，而該導電糊內的該導電粒子爲金粉末，銀粉末， 及銀鉑合金粉末之一。 2 〇 ·如申請專利範圔第1 5項所述的倒裝晶片連接 結構，其中在設置在該第一與第二電極之間的該導電糊內 的該導電粒子的密度爲至少9 7重量百分比（w t 的 濃度。 2 1 ·如申請專利範圍第1 5項所述的倒裝晶片連接 結構，其中互相電連接的該第一與第二電極之間的接觸電 阻小於5 0毫歐姆。 2 2 ♦如申請專利範圍第1 5項所述的倒裝晶片連接 結構，其中互相電連接的該第一與第二電極之間的接觸電 本纸尺度逋用中國國家糅率（CNS ) Λ4规格（210X297公釐） ---------^— {請先M1T背面之注^•項再填寫本頁) 訂 線 25 B8 C8 ___ D8 六、申請專利範困 阻小於4 0毫歐姆。 2 3 ·如申請專利範圍第1 5項所述的倒裝晶片連接 結構’其中互相電連接的該第—與第二電極之間的接觸電 阻小於3 0毫歐姆。 2 4 ·如申請專利範圍第1 5項所述的倒裝晶片連接 結構’其中互相電連接的該第一與第二電極之間的接觸電 阻小於2 0毫歐姆。 2 5 ·如申請專利範圍第1 5項所述的倒裝晶片連接 結構’其中互相電連接的該第一與第二電極之間的接觸電 阻小於1 〇毫歐姆。 2 6 ·—種電子裝置，含有如申請專利範圍第1 5項 所述的倒裝晶片連接結構。 ---------#------tr------终 c*請先Mtr背*之注$項再壤寫本買) 經濟部中央揉牟局工消费合作社印*. 本紙⑽逍用中國賴準（峰娜（酶腸·26·
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2924830B2 (ja) * 1996-11-15 1999-07-26 日本電気株式会社 半導体装置及びその製造方法
EP1041616A4 (en) * 1997-11-19 2005-05-11 Matsushita Electric Ind Co Ltd ELECTRONIC STRESS RELAXATION COMPARTMENT, STRAIN RELAXATION CONNECTION CHART, AND BODY MOUNTED ON THE ELECTRONIC STRESS RELAXATION PIECE
JP2001044358A (ja) 1999-07-28 2001-02-16 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2001085470A (ja) * 1999-09-16 2001-03-30 Fujitsu Ltd 半導体装置及びその製造方法
JP2001093938A (ja) * 1999-09-20 2001-04-06 Nec Kansai Ltd 半導体装置及びその製造方法
US6348740B1 (en) * 2000-09-05 2002-02-19 Siliconware Precision Industries Co., Ltd. Bump structure with dopants
JP2002261111A (ja) * 2001-03-06 2002-09-13 Texas Instr Japan Ltd 半導体装置及びバンプ形成方法
KR100443504B1 (ko) 2001-06-12 2004-08-09 주식회사 하이닉스반도체 볼 그리드 어레이 패키지 구조 및 그 제조방법
US7067916B2 (en) * 2001-06-20 2006-06-27 International Business Machines Corporation Extension of fatigue life for C4 solder ball to chip connection
KR100445296B1 (ko) * 2002-07-22 2004-08-21 주식회사 플렉시스 플립 칩 온 필름 및 그 제조방법
US7387827B2 (en) 2002-12-17 2008-06-17 Intel Corporation Interconnection designs and materials having improved strength and fatigue life
US7521115B2 (en) * 2002-12-17 2009-04-21 Intel Corporation Low temperature bumping process
JP2008508519A (ja) * 2004-07-28 2008-03-21 エス・ブイ・プローブ・プライベート・リミテッド 基板上に同一平面上のボンディングパッドを製造するための方法および装置
US11842972B2 (en) 2004-09-28 2023-12-12 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
JP2006100385A (ja) * 2004-09-28 2006-04-13 Rohm Co Ltd 半導体装置
US7713839B2 (en) * 2004-10-06 2010-05-11 Intel Corporation Diamond substrate formation for electronic assemblies
US20070004216A1 (en) * 2005-06-30 2007-01-04 Chuan Hu Formation of assemblies with a diamond heat spreader
TWI339358B (en) * 2005-07-04 2011-03-21 Hitachi Ltd Rfid tag and manufacturing method thereof
JP2009238969A (ja) * 2008-03-27 2009-10-15 Panasonic Corp 電子部品の実装構造および電子部品実装体の製造方法
CN101635290B (zh) * 2008-07-22 2012-05-30 瀚宇彩晶股份有限公司 金属凸块结构及其应用于封装结构
US20120049079A1 (en) * 2010-08-24 2012-03-01 General Electric Company Electronic assembly
JP2014529199A (ja) * 2011-10-10 2014-10-30 コーニンクレッカ フィリップス エヌ ヴェ サブマウント上にｖｃｓｅｌチップを組立てる方法
US20170110392A1 (en) * 2015-10-15 2017-04-20 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same structure
US10741483B1 (en) * 2020-01-28 2020-08-11 Advanced Semiconductor Engineering, Inc. Substrate structure and method for manufacturing the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750726B2 (ja) * 1987-05-07 1995-05-31 松下電器産業株式会社 半導体チップの実装体
JP2574369B2 (ja) * 1988-03-07 1997-01-22 松下電器産業株式会社 半導体チップの実装体およびその実装方法
JPH0666355B2 (ja) * 1988-12-16 1994-08-24 松下電器産業株式会社 半導体装置の実装体およびその実装方法
US5141777A (en) * 1990-05-02 1992-08-25 Advanced Products, Inc. Highly conductive polymer thick film compositions
US5740010A (en) * 1992-10-21 1998-04-14 Devoe; Daniel F. Printing and adhering patterned metal on laid-up multi-layer green wafer before firing so as to later form precise integral co-fired conductive traces and pads on top and bottom surfaces of monolithic, buried-substrate, capacitors
JPH08111437A (ja) * 1994-10-12 1996-04-30 Matsushita Electron Corp 半導体装置の実装方法
US5837119A (en) * 1995-03-31 1998-11-17 International Business Machines Corporation Methods of fabricating dendritic powder materials for high conductivity paste applications
JP2731383B2 (ja) * 1996-09-09 1998-03-25 富士通株式会社 部品実装構造及び部品実装方法

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