TW387129B - Semiconductor devices - Google Patents
Semiconductor devices Download PDFInfo
- Publication number
- TW387129B TW387129B TW087107903A TW87107903A TW387129B TW 387129 B TW387129 B TW 387129B TW 087107903 A TW087107903 A TW 087107903A TW 87107903 A TW87107903 A TW 87107903A TW 387129 B TW387129 B TW 387129B
- Authority
- TW
- Taiwan
- Prior art keywords
- delay control
- wiring
- control unit
- semiconductor device
- cross
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 53
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000012360 testing method Methods 0.000 claims abstract description 17
- 238000004088 simulation Methods 0.000 claims abstract description 12
- 238000010586 diagram Methods 0.000 claims description 46
- 238000004519 manufacturing process Methods 0.000 claims description 46
- 238000005259 measurement Methods 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 4
- 238000007639 printing Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 230000000875 corresponding effect Effects 0.000 claims 3
- 230000002079 cooperative effect Effects 0.000 claims 2
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 claims 1
- 238000012986 modification Methods 0.000 claims 1
- 230000004048 modification Effects 0.000 claims 1
- 235000015170 shellfish Nutrition 0.000 claims 1
- 108090000237 interleukin-24 Proteins 0.000 abstract 1
- 238000013461 design Methods 0.000 description 19
- 239000003990 capacitor Substances 0.000 description 11
- 230000008569 process Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010884 ion-beam technique Methods 0.000 description 4
- 239000000523 sample Substances 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 238000012545 processing Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 235000017166 Bambusa arundinacea Nutrition 0.000 description 1
- 235000017491 Bambusa tulda Nutrition 0.000 description 1
- 241001330002 Bambuseae Species 0.000 description 1
- 101000710013 Homo sapiens Reversion-inducing cysteine-rich protein with Kazal motifs Proteins 0.000 description 1
- 101000585359 Homo sapiens Suppressor of tumorigenicity 20 protein Proteins 0.000 description 1
- 235000015334 Phyllostachys viridis Nutrition 0.000 description 1
- 102100029860 Suppressor of tumorigenicity 20 protein Human genes 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000011425 bamboo Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 210000005252 bulbus oculi Anatomy 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000011960 computer-aided design Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
- 210000004080 milk Anatomy 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000008911 qingzhi Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Architecture (AREA)
- Computer Networks & Wireless Communication (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00783098A JP4229998B2 (ja) | 1998-01-19 | 1998-01-19 | 半導体装置および半導体装置の製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW387129B true TW387129B (en) | 2000-04-11 |
Family
ID=11676524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW087107903A TW387129B (en) | 1998-01-19 | 1998-05-21 | Semiconductor devices |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6269280B1 (ja) |
| JP (1) | JP4229998B2 (ja) |
| KR (1) | KR100303675B1 (ja) |
| DE (1) | DE19842245A1 (ja) |
| TW (1) | TW387129B (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI781017B (zh) * | 2021-12-17 | 2022-10-11 | 力晶積成電子製造股份有限公司 | 測試系統以及其測試電路 |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6360133B1 (en) * | 1999-06-17 | 2002-03-19 | Advanced Micro Devices, Inc. | Method and apparatus for automatic routing for reentrant process |
| US7466180B2 (en) * | 2000-12-12 | 2008-12-16 | Intel Corporation | Clock network |
| KR100396530B1 (ko) * | 2001-09-29 | 2003-09-02 | 기가트론 주식회사 | 혼성신호 집적회로 설계를 위한 실리콘 기판 결합잡음모델링 및 분석 방법 |
| US7292046B2 (en) * | 2003-09-03 | 2007-11-06 | Infineon Technologies Ag | Simulated module load |
| US7102914B2 (en) * | 2004-02-27 | 2006-09-05 | International Business Machines Corporation | Gate controlled floating well vertical MOSFET |
| US7448012B1 (en) | 2004-04-21 | 2008-11-04 | Qi-De Qian | Methods and system for improving integrated circuit layout |
| US7784015B2 (en) * | 2005-07-05 | 2010-08-24 | Texas Instruments Incorporated | Method for generating a mask layout and constructing an integrated circuit |
| JP4320340B2 (ja) * | 2006-12-15 | 2009-08-26 | 川崎マイクロエレクトロニクス株式会社 | 半導体集積回路の設計方法、および、半導体集積回路 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0658937B2 (ja) | 1984-03-07 | 1994-08-03 | 株式会社東芝 | 半導体集積回路 |
| JPH04246857A (ja) | 1991-02-01 | 1992-09-02 | Nec Ic Microcomput Syst Ltd | 半導体集積回路装置 |
| JP3154524B2 (ja) | 1991-08-14 | 2001-04-09 | 株式会社日立製作所 | 半導体装置の設計方法 |
| JPH0669339A (ja) | 1992-08-18 | 1994-03-11 | Hitachi Ltd | 半導体装置 |
| JPH08212185A (ja) | 1995-01-31 | 1996-08-20 | Mitsubishi Electric Corp | マイクロコンピュータ |
| JP3498462B2 (ja) * | 1995-12-22 | 2004-02-16 | ヤマハ株式会社 | 集積回路のクロック配線設計法 |
| JPH09246391A (ja) * | 1996-03-06 | 1997-09-19 | Sharp Corp | 配線設計方法および配線設計装置 |
| US5841296A (en) * | 1997-01-21 | 1998-11-24 | Xilinx, Inc. | Programmable delay element |
| JPH10283777A (ja) | 1997-04-04 | 1998-10-23 | Mitsubishi Electric Corp | Ｓｄｒａｍコアと論理回路を単一チップ上に混載した半導体集積回路装置およびｓｄｒａｍコアのテスト方法 |
| US5930182A (en) * | 1997-08-22 | 1999-07-27 | Micron Technology, Inc. | Adjustable delay circuit for setting the speed grade of a semiconductor device |
| US5889726A (en) * | 1997-11-17 | 1999-03-30 | Micron Electronics, Inc. | Apparatus for providing additional latency for synchronously accessed memory |
| JPH11153650A (ja) * | 1997-11-20 | 1999-06-08 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| US6044024A (en) * | 1998-01-14 | 2000-03-28 | International Business Machines Corporation | Interactive method for self-adjusted access on embedded DRAM memory macros |
-
1998
- 1998-01-19 JP JP00783098A patent/JP4229998B2/ja not_active Expired - Fee Related
- 1998-05-21 TW TW087107903A patent/TW387129B/zh not_active IP Right Cessation
- 1998-07-13 US US09/113,029 patent/US6269280B1/en not_active Expired - Lifetime
- 1998-07-24 KR KR1019980029879A patent/KR100303675B1/ko not_active IP Right Cessation
- 1998-09-15 DE DE19842245A patent/DE19842245A1/de not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI781017B (zh) * | 2021-12-17 | 2022-10-11 | 力晶積成電子製造股份有限公司 | 測試系統以及其測試電路 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11204652A (ja) | 1999-07-30 |
| US6269280B1 (en) | 2001-07-31 |
| KR19990066724A (ko) | 1999-08-16 |
| DE19842245A1 (de) | 1999-07-22 |
| KR100303675B1 (ko) | 2001-09-24 |
| JP4229998B2 (ja) | 2009-02-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8332794B2 (en) | Circuits and methods for programmable transistor array | |
| US7739627B2 (en) | System and method of maximizing integrated circuit manufacturing yield with context-dependent yield cells | |
| TW387129B (en) | Semiconductor devices | |
| CN101794774B (zh) | 半导体集成电路 | |
| Zhao et al. | Low-power clock tree design for pre-bond testing of 3-D stacked ICs | |
| KR20010088859A (ko) | 집적 회로 및 집적 회로 전력 및 접지 라우팅 방법 | |
| US7902879B2 (en) | Field programmable gate array utilizing dedicated memory stacks in a vertical layer format | |
| KR20080087714A (ko) | 3차원 집적회로 설계 방법 및 장치 | |
| Jiang et al. | Modeling TSV open defects in 3D-stacked DRAM | |
| CN110136758A (zh) | 写入辅助 | |
| Kabir et al. | Holistic Chiplet–Package Co-Optimization for Agile Custom 2.5-D Design | |
| US20200211625A1 (en) | Apparatuses and methods for sense line architectures for semiconductor memories | |
| JP5297468B2 (ja) | 半導体集積回路の設計方法およびソフトウエア | |
| US6512708B1 (en) | Placement and routing for wafer scale memory | |
| JPH10229129A (ja) | 半導体集積回路のチップレイアウト及びその検証方法 | |
| US5341383A (en) | Circuit arrangement suitable for testing cells arranged in rows and columns, semiconductor integrated circuit device having the same, and method for arranging circuit blocks on chip | |
| US5694328A (en) | Method for designing a large scale integrated (LSI) layout | |
| JP4170600B2 (ja) | 半導体集積回路及びその設計方法 | |
| Facchini et al. | An RDL-configurable 3D memory tier to replace on-chip SRAM | |
| CN100552456C (zh) | 具有多层弹性的微机电探针卡 | |
| TW512396B (en) | Functional macro and its design method, and semiconductor device design method | |
| JP2008244504A (ja) | 半導体装置 | |
| US20220165706A1 (en) | Semiconductor structure of cell array | |
| US20020075028A1 (en) | Design circuit pattern for test of semiconductor circuit | |
| JP3115743B2 (ja) | Ｌｓｉ自動レイアウト方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |