TW380301B - An open-bottomed via liner structure and method for fabricating same - Google Patents
An open-bottomed via liner structure and method for fabricating same Download PDFInfo
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- TW380301B TW380301B TW086118239A TW86118239A TW380301B TW 380301 B TW380301 B TW 380301B TW 086118239 A TW086118239 A TW 086118239A TW 86118239 A TW86118239 A TW 86118239A TW 380301 B TW380301 B TW 380301B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明G ) 發明領域 本發明係關於在半導體裝置中形成擋件或襯墊層之結構 之製成’特別的是本發明係關於在一通孔侧壁而不在通孔 底部產生絕緣與擴散擋件之襯墊結構之製成。 發明背景 一半導體晶片内裝一列裝置,而裝置之接觸點係由導電 線圖案予以銜接,為了獲取所有之裝置優點及在—給定晶 片上取得電路密度,通常需在晶片之不同裝置與電路元件 之間做成銜接。惟,由於一晶片上之裝置與電路整合高 度,銜接無法再以單一之導電線網路達成,其通常需形成 二或多條此高度之導電線’且呈垂直間隔及由中間絕緣層 分隔。 ,銜接工作可利用通孔而形成於不同高度之導電線之間, 通孔係姓刻穿過將諸高度分隔之絕緣層,通孔填注金屬而 形成通孔柱’諸層導電線銜接圖案以及由通孔柱銜接之個 別向度層-併操作而在晶片上之電路間配送訊號。 在此單純型式中,一诵^丨夕愈】士,& + 疋I成為先以阻光件遮蔽一絕 緣層,然後選擇性蝕刻一部份之 丨1刀 <、名緣層。通孔利用習知之 ,-η相平版印刷技術,以蝕 」牙避形成於阻光件中之開 孔,以利形成底部導電層之一開 理,菩Μ Ρ人 根據縱橫比及接地原 f向或非寺向之飯刻過程可 中。 、征J ^於製成一孔於介電質
通孔蝕刻且阻光件移除後,即可沉積—道兩 中,壤册奸孤 > 社寸迅層於通孔 導材枓儿積於通孔中,以形成導+猛Μ、+ A 机聲電層間t電力銜 私紙張尺度適财ϋ @家轉(CNS)概格( (請先閲讀背面之注意事項再填寫本頁)
五、發明説明(: 接惟,一襯墊層通常為絕緣層與導電層之間所需者。 通孔侧壁上呈現之—槪塾層係有其必要 除層及導體金屬德典p W 為…構上g 展之η:= 發生,除非在導電層及韻刻絕續 間有-保叙_層。惟,相較於導電材料則最佳次 :現::科應較具電阻性,使得存在於通孔底部之襯墊可塌 σ、Ί接觸阻抗’接觸阻抗之增加並不必要,因其合= =訊號缓慢傳送通過線路結構。為了結構完整性:: i·層應概設於整個侧壁以及大致覆蓋通孔之底部。 襯墊及導電層可利用賤射、⑽、無電式沉積及電子沉 積而積存,通常Rf偏恩賤射係屬習知技術且在賤射沉積而 離子衝擊於待沉積層期間相關於材料之重複放射。作用 時,Rf偏壓崎為沉積期間一基層或薄膜之正離子衝擊, 因此,在Rf偏壓軸期間,其同時進行待沉積材料之蚀刻 及沉積,先前沉積之層並未蚀刻成為一標準Rf偏壓激射沉 積物之一部份。
Rf偏壓麟期間’粒子衝㈣—乾物上,使㈣滅射至 半導體晶片基層上,在製程期間待沉積之離子亦衝擊於半 導體基層’使基層可具有一平滑表面。 可形成-襯塾層之材料大致具有一大於導電材料之電 阻,且襯蟄材料通常選擇為可用時減至最低之接觸阻抗、 在絕緣材料與導電材料之間提供適當之黏著、及提供一良 好之擴散擒件。當使用鋼做為導電材料時,接觸阻抗問題 更开/複雜使用鋼時,-連續之不同類襯I材料呈現於通 孔底部處之車交高阻抗將有礙於通孔導體材料與下層線路之 5- 本紙张尺度適用中國國家標準(CNS ) A4規格(210X297公釐) —J I - — -----'.—'^1 I (請先閲請背面.y注意事項再填寫本頁) 訂 .-7^ 經濟部中央標準局員工消費合作社印装 A7 B7 五、發明説明( 間單一晶體或連續介面之 其兴逾.曰ΛJ面又構成,早—晶體介面之構成係有 供較大之結構完整性。H 下層線路之間之介面提 ^ ^ , 列如,在鋼電鍍之前之銅籽層之沉 電鍍之環境,鋼層有利於在通孔金屬介 :==:體鋼結構之構成,因為種一構上較 並未揭述在—濺射沉積期間選擇地做㈣壓, 使传’儿積之槪塾層女it、S ~£丨、、 現上層大致自通孔《屐部去除,而通孔侧壁 儿積材料大致上不受影痤, ^ 〜a 棱供此一結構之方法需促 成連、銅通孔與導電金屬線之產生。 因此有必要利用—種產生—士 . 易於無電式沉積及電m 1: 法’孩万法較 式/儿積,尤其是做銅電鍍;及一種 、'’:構’其具有一襯墊材料呈現於通孔之侧壁上,而不在通 孔之底部上。 發明概述 緣是’本發明之—目的在提供-種製成-通孔之方法, 且具有概塾材料於通孔之側壁上,而不在通孔之底部上, 即形成一無底式通孔。 本發明之另一目的在提供-種製成-通孔之方法,且且 有一第二材料沉積於通孔之侧壁上,而不在通孔之底部 上。 本發明之又一目的在提供一種較利於鋼電鍍之環境。 上述及其他特性、内容、及優點可由本發明之以下詳細 說明獲得瞭解,其闡釋一種製成一無底式襯墊結構之方 -6- 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公澄) ---------.7—装— 「I {請先閲讀背面之注意事項再填寫本頁) -訂 T1" 經濟部中央標準局員工消費合作社印製 經濟部中央榡準局員工消費合作社印製 A7
----- B7_L 五、發明説明(4 ) 法,其包含: a) 取得一具有一通孔之材料; b) 沉積一第一層於具有通孔之材料上,第一層覆蓋於通 孔之側壁及底部; 、 c) 濺射沉積一第二層於第一層上,在第二層進行濺射沉 積之2份時間中令材料進行Rf偏壓,使得沉積於通孔底部 上足第一層大致去除,且沉積於通孔侧壁上之大致所有第 一層不受影響。 圖式簡單說明 圖la係用於一濺射沉積裝置所需之結構示意圖。 圖lb係材料與所需濺射沉積裝置之間關係之示意圖。 圖2a係執行本發明方法所產生之中間結構。 圖2b類似於圖2a ’惟其揭示中間結構之不同段細部構 ° 發明方法所取得之—最終結構,其中通孔之底 4並未包含沉積之第—或第二層。 :4揭示本發:方法所取得之一最終結構,其中通孔之底 4並未包含沉積之第—層。 較佳實例詳細說明 本發明包含-種積置—用於通孔結構之 ::孔:=最終結構中僅於侧壁上存在有L Γ 式展部即開放以供下層之線路做低阻抗式接 請參閱詳示之圖式,特別是圖la、lb,—實施本發明方 -7 用中國國^7^7^7^0><297公整) I n I I n I n n I I 1 (请光閲讀背面之注意事項真娘寫本頁)
,1T d A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明(5 ) 法(所需裝置3G即揭示,裝置 1 ’容室^設有-準直儀2以及-夾環式屬沉積宣 在沉積期間令晶片3承受Rf偏壓2〇,二夾頭可 如圖lb所示接觸於晶片3。 衣式阳片夾頭4係 裝置之排列組構係指一結構例子 方法:其他裝置排列方式並不存在,且本= 依賴於圖1 a、1 b所示之裝置排列方式。 、 本:明之二實例皆具有特定之共同製程條件,而影響圖 在-較佳實例中,壓、叫放二; =壓:皆做控!1 ’而在一最佳實例中,所用之氣體應為 同軋肢,及在取理想之實例中,氣體係氬氣。 么總沉積時間及Rf使用因素在本發明之二方法實例中皆可 1化,總沉積時間為欲做Rf偏壓濺射沉積之材料、濺射沉 積材料之所需厚度、及通孔尺寸與縱橫比之函數。 μ偏壓作動之時間部份為三個變數之因素,諸變數即 丁tnt Trf〇n及Trfoff。Tt(Jt為賤射沉積過程之總時間量,即總沉 積時間;Trf(3n為濺射沉積步驟過程之時間,其中Rf偏壓係 接通或作動,Trfoff為濺射沉積步驟期間,當R f偏壓已接通 後之Rf偏壓斷電時間。其中,令本發明製程達到最佳效率 之變數係由下式界定: 1 )0.50 < Trfon/Ttot < 0.75 2) 0.75 < Trfoff/Ttot 3) (Trfoff-Trfon)/ Ttot >0.18 -8 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) I n I i n n n - n I n n - I T I I _ I n I -¾ *T-y (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 Α7 Β7 五、發明説明(6 上述岫二個等式說明Rf偏壓οη/off時間與總沉積時間之 間關係’(Trfoff_Trfc)n)界定濺射沉積之Rf偏壓部份使用 (duty)因素,使用因素為汉£偏壓接通或作動之時間長度。 上述又第三等式說明Rf偏壓之使用因素需至少大約為總沉 積時間之18%,以利取得本發明製程結果之結構。 本發明製程所產生之一最終結構係具有一呈現於一通孔 =壁上之襯墊層,但是未呈現於通孔之底部,在本發明之 製較中,圖2 a所示之一第一層i 0係先利用習知之任意裝置 而沉積於一通孔100,即第一層1〇覆蓋通孔1〇〇。第一層1〇 内含—可襯設通孔之材料,以防止隨後沉積之材料擴散至 絕緣層12,在本文中,絕緣層12係鋪設於一可做為金屬層 1 4之材料上,大體而言,通孔丨〇〇係延伸穿過絕緣層1 2而 到達底部之金屬層1 4。 圖2a所示在此例中做為一襯墊層之第一層丨〇係詳示於圖 2 b襯塾層大致以1 〇標示,其包含一侧壁襯整丨〇a、底部 :墊i〇b、及表面襯墊10c,表面櫬墊1〇c在必要時可利用任 意I習知裝置去除。覆蓋於侧壁1〇a之襯墊材料需延伸至通 孔之底面,因為一完整之遮擋件需存在於絕緣材料12與通 孔1 00内之任意後續沉積材料之間。可襯設於通孔之材料包 含但是不限定於鈥、氮化飲、鶴、叙、氮化麵、氮化艇/ 纽、;ΪΕ/氮化輕、及叙/氮化知/知。 本發明方法產生一種環境,其中襯墊材料之導電品質將 不再為襯墊材料選擇上之因素,在歷史上,一潛在性襯墊 材料之絕緣品質會造成一個別材料因接觸之阻抗增加而做 -9 - 本紙張尺度適用中國國家標準(CNS ) M規格(2Ι〇.χ297公瘦) (請先閲讀背面之注意事項再填寫本頁} .1¾ ίΐτ------——"------------- 經濟部中央標準局員工消费合作社印裝 五·、發明説明(7 ^不艮之襯墊材料選擇。由於櫬墊材料並未呈現於通孔底 4,因此其對電子訊號之傳送不致扮演障礙物之角色。因 此,一襯墊材料之絕緣品質不再成為—襯墊材料選擇上之 =要因素,而其他設計因素現在即可做成襯墊材料之選 。必要時除了上述之絕緣及半導體性材料外,現在可使 用其他者做為襯墊材料,因為其非導電性將不再影響電子 訊號之傳送。 θ 圖2 a、2 b代表文後將做進一步處理之中間結構。 圖3、4揭示本發明方法之不同實例所產生之變換最終結 構,在圖3中’一第二層"係利用_Rf偏壓濺射沉積而積 存於第一層1〇上,第二沉積物為濺射所沉積而成,濺射沉 _積製程條件需加以選擇,使得先前沉積之層,即塗覆於通 ^底部之一襯墊層10形成"大致去除”,但是在濺射沉積後 "大致所有”先前沉積襯墊層仍襯鋪於侧壁。"大致去除"係 指濺射沉積量不足以明顯影響最終結構之電子與電容潛在 性後仍留在通孔100底部上之第一沉積材料量,而,,大^所 有,,係指隨後沉積之濺射沉積量足以防止導電材料擴散至絕 緣層後仍留存於通孔侧壁上之第一沉積材料量。 此外,在圖3中之濺射沉積第二層u係大致自通孔底部 去除,但疋大致上所有濺射沉積第二層丨丨仍留存於侧壁 上,濺射沉積之第二層11可為一使通孔結構較導電於金屬 化沉積物之材料,此為多層式連通所必須者,或其可為本 身金屬化。 圖4中,一第二沉積物係進行濺射沉積於第二層n,第 -10- 本纸浪尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (讀先閱讀背面之注意事項再4寫本頁) ------;-----^----ΤΛ衣-----1Τ--- 五、發明説明(8 A7 B7 經濟部中央標準局員工消費合作杜印製 二沉積物利用_Rf偏壓進行濺射沉積,而Rf偏壓濺射沉積 ‘表條件為加以選擇,使得塗於通孔100底部之先前沉積襯 墊層1 0大致上去除,但是大致上所有襯設於侧壁之襯墊材 料仍田存。圖4中,Rf偏壓濺射沉積之第二層仍留存在通 孔底部以及通孔侧壁,第二層可為任意之材料,但是在本 發明之較佳實例中其係高度導電材料,例如銅、鋁、或 金。 範例1 在此例子中,製程變數導致圖4所示之最終結構,而第二 騎沉積層U呈現於通孔之侧壁及底部上,第—層即觀塾 層10則為氮化钽/妲,且係利用任意習知技藝沉積。第二 之Rf偏壓濺射沉積層u為鋼,銅之濺射沉積物產生一第二 層,,後一連續之銅結構可利用習知技藝之任意裝置而形 成於第二層U頂部,㈣沉積之Rf_約為16〇伏,^偏 壓放電大約i Kw’用於賤射沉積製程中之氣體為氬,且氨 壓力大約為5亳托(mTorr) ’總沉積時間τ⑹大约153秒、。 少於⑸秒之總沉積時間。為了形成第二層沉積物於通孔^ 行而無Rf偏壓作用,且通孔底部塗覆她冗積之第二層 丁如選足為可賦與-預定厚度之錢射沉積物於侧壁上 其係在前述等式之限制範圍内。 範例2 此例子中,製程變數導致圖3所示之最終結構,立中第二 偏壓歲射沉積層n呈現於侧壁上,但是不在通孔底部 進 且 (請先閲讀背面之注意事項再填寫本頁)
.IT -11 - A7 B7
五、發明説明(9 ) 上’第一層即襯墊層10為氮化鈕/钽且利用任意習知技藝. 衣置予以沉積,第二之Rf偏壓濺射沉積層丨丨為銅,用於濺 射’儿積之Rf偏壓電壓設定為大約16〇伏,Rf偏壓放電大約^ kw,濺射沉積製程中所用之氣體為氬且氬壓力大約5毫 托,>儿積時間Ttot大約153秒,Trf〇ff大約153秒,選定以 預足每度之錢射沉積物於侧.壁上,且其在前述等式 之限制範圍内。 本發明雖已藉由特定實例說明,但是經由前文可知其多 種變換、修改及變化對習於此技者皆屬顯而易知之事,緣 疋本發明之目的欲涵蓋諸此變換、修改及變化於本發明 之精神範疇及申請範園内。 A (請先閲讀背面之注意事項再填寫本頁} 經濟部中央標準局員工消費合作社印裝
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Claims (1)
- 六、申請專利範圍 A8 B8 C8 D8 經濟部中央標準局J工消費合作社印製 1. 一種製成一無底式襯塾結構之方法,包含以下步驟: a) 取得一具有一通孔之材料; b) /儿積第—層於具有通孔之材科上,第一層覆蓋於 通孔之侧壁及底部; 〇濺射沉積一第二層於第—層上,在第二層進行濺射 沉積义邵份時間中令材料進行^^偏壓,使得沉積於通孔 底部上之第一層大致去除,且沉積於通孔侧壁上之大致 所有第一層不受影響。 2. 如申請專利範圍第1項之方法, 3·如申請專利範圍第1項之方法 層包含一絕緣材料。 4. 如申請專利範園第1項之方法 層包含一半導體材料。 5. 如申請專利範圍第1項之方法 層包含一導電性材料。 6. 如申請專利範園第5項之方法 層係選自以下族群,包含鈦、氮化鈦、鎢、鈦鎢、氮化 鎢、钽、氮化钽、氮化妲/鈕、钽/氮化銓、及钽/氮化鈕 /麵。 7. 如申請專利範圍第6項之方法,其中第一層係氮化钽/ 輕。 8. 如申請專利範圍第1項之方法,寻中第二層係一金屬。 9. 如申請專利範圍第8項之方法,其中第二層係銅。 10_如申請專利範圍第1項之方法’其中濺射沉積Rf偏壓係 其中材料係一基層。 ,其中覆蓋於通孔之第一 ,其中覆蓋於通孔之第一 ,其中覆蓋於通孔之第一 ’其中覆蓋於通孔之第一 (請先閱讀背面之注意事項再填寫本頁) • I · t- Γ I -13- 本紙張尺度適用中國國家標準(CNS ) A4规格(210X297公釐)經濟部中央標準局員工消費合作社印製 作用為總濺射沉積時間之最少約25%及最多約50%。 11. —種半導體物件,包含: a·—材料,具有一通孔; b_~積置於通孔中之第一層,第一層襯設於通孔; /儿積於第一層上之第二層,第二層係利用偏壓 ,射沉積而積存;其中沉積於通孔底部上之第_層係在 第層之R f偏壓錢射沉積期間大致去除,但是沉積於通 孔側壁上之大致所有第一層則在第二層之Rf偏壓濺射沉 積期間不受影響。 12. 如申凊專利範圍第〗丨項之物件,其中第—層包含一半導 體材料。 13. 如申凊專利範園第丨丨項之物件,其中第一層包含一絕緣 材料。 认如申請專利範園第u項之物件,其中第—層包含一導電 性材料。 15. 如申請專利範圍第14項之物件,其中第—層包含氮化妲 /叙。 16. 如申請專利範圍第1 1項之物件,其中第二層包含一導電 性材料。 17. 如申請專利範圍第丨6項之物件,其中第二層係鋼。 -14 - 本紙張尺度適用中國國家標隼(CNS ) Α4規格(21〇Χ297公釐) .—^ I i ^ ~ 訂 (請先聞讀背面之注意事項再填寫本頁) Q
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US5933753A (en) | 1999-08-03 |
KR19980063734A (ko) | 1998-10-07 |
KR100268213B1 (ko) | 2000-10-16 |
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