TW376583B - Layout for SRAM structure - Google Patents

Layout for SRAM structure

Info

Publication number
TW376583B
TW376583B TW087108266A TW87108266A TW376583B TW 376583 B TW376583 B TW 376583B TW 087108266 A TW087108266 A TW 087108266A TW 87108266 A TW87108266 A TW 87108266A TW 376583 B TW376583 B TW 376583B
Authority
TW
Taiwan
Prior art keywords
region
source
storage
transistor
transistors
Prior art date
Application number
TW087108266A
Other languages
English (en)
Inventor
Tsiu Chiu Chan
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Application granted granted Critical
Publication of TW376583B publication Critical patent/TW376583B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors
TW087108266A 1997-05-30 1998-05-27 Layout for SRAM structure TW376583B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/865,641 US6005296A (en) 1997-05-30 1997-05-30 Layout for SRAM structure

Publications (1)

Publication Number Publication Date
TW376583B true TW376583B (en) 1999-12-11

Family

ID=25345936

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087108266A TW376583B (en) 1997-05-30 1998-05-27 Layout for SRAM structure

Country Status (5)

Country Link
US (1) US6005296A (zh)
EP (1) EP0881685A1 (zh)
JP (1) JPH1145948A (zh)
KR (1) KR19980087485A (zh)
TW (1) TW376583B (zh)

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US8193050B2 (en) 2008-03-28 2012-06-05 United Microelectronics Corp. Method for fabricating semiconductor structure
JP2012178590A (ja) * 1998-05-01 2012-09-13 Sony Corp 半導体記憶装置

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US6501138B1 (en) * 1999-04-16 2002-12-31 Seiko Epson Corporation Semiconductor memory device and method for manufacturing the same
KR100289810B1 (ko) * 1999-05-10 2001-05-15 김영환 반도체 소자 제조를 위한 할로 이온 주입 방법
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JP4009810B2 (ja) * 2000-04-11 2007-11-21 セイコーエプソン株式会社 半導体記憶装置
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JP3386037B2 (ja) * 2000-06-15 2003-03-10 セイコーエプソン株式会社 半導体記憶装置
US6668366B2 (en) * 2000-08-18 2003-12-23 Texas Instruments Incorporated System and method for processing a transistor channel layout
JP2002373946A (ja) * 2001-06-13 2002-12-26 Mitsubishi Electric Corp スタティック型半導体記憶装置
JP4219663B2 (ja) * 2002-11-29 2009-02-04 株式会社ルネサステクノロジ 半導体記憶装置及び半導体集積回路
JP4186970B2 (ja) 2005-06-30 2008-11-26 セイコーエプソン株式会社 集積回路装置及び電子機器
US7561478B2 (en) 2005-06-30 2009-07-14 Seiko Epson Corporation Integrated circuit device and electronic instrument
JP4830371B2 (ja) 2005-06-30 2011-12-07 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4010336B2 (ja) 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
KR100826695B1 (ko) * 2005-06-30 2008-04-30 세이코 엡슨 가부시키가이샤 집적 회로 장치 및 전자 기기
JP4661401B2 (ja) 2005-06-30 2011-03-30 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4151688B2 (ja) 2005-06-30 2008-09-17 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4010333B2 (ja) * 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4010332B2 (ja) * 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
US7593270B2 (en) 2005-06-30 2009-09-22 Seiko Epson Corporation Integrated circuit device and electronic instrument
JP4010335B2 (ja) 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
US20070001974A1 (en) * 2005-06-30 2007-01-04 Seiko Epson Corporation Integrated circuit device and electronic instrument
US7564734B2 (en) 2005-06-30 2009-07-21 Seiko Epson Corporation Integrated circuit device and electronic instrument
KR100828792B1 (ko) 2005-06-30 2008-05-09 세이코 엡슨 가부시키가이샤 집적 회로 장치 및 전자 기기
US7755587B2 (en) 2005-06-30 2010-07-13 Seiko Epson Corporation Integrated circuit device and electronic instrument
JP4661400B2 (ja) 2005-06-30 2011-03-30 セイコーエプソン株式会社 集積回路装置及び電子機器
US7567479B2 (en) 2005-06-30 2009-07-28 Seiko Epson Corporation Integrated circuit device and electronic instrument
US7764278B2 (en) 2005-06-30 2010-07-27 Seiko Epson Corporation Integrated circuit device and electronic instrument
JP4665677B2 (ja) 2005-09-09 2011-04-06 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4586739B2 (ja) 2006-02-10 2010-11-24 セイコーエプソン株式会社 半導体集積回路及び電子機器
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
SG192532A1 (en) 2008-07-16 2013-08-30 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
JP7248966B2 (ja) * 2016-07-06 2023-03-30 国立研究開発法人産業技術総合研究所 半導体記憶素子、電気配線、光配線、強誘電体ゲートトランジスタ及び電子回路の製造方法並びにメモリセルアレイ及びその製造方法

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012178590A (ja) * 1998-05-01 2012-09-13 Sony Corp 半導体記憶装置
US8193050B2 (en) 2008-03-28 2012-06-05 United Microelectronics Corp. Method for fabricating semiconductor structure
US8816439B2 (en) 2008-03-28 2014-08-26 United Microelectronics Corp. Gate structure of semiconductor device

Also Published As

Publication number Publication date
EP0881685A1 (en) 1998-12-02
US6005296A (en) 1999-12-21
KR19980087485A (ko) 1998-12-05
JPH1145948A (ja) 1999-02-16

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