TW374918B - Semiconductor memory device having multilevel memory cell array - Google Patents

Semiconductor memory device having multilevel memory cell array

Info

Publication number
TW374918B
TW374918B TW086101401A TW86101401A TW374918B TW 374918 B TW374918 B TW 374918B TW 086101401 A TW086101401 A TW 086101401A TW 86101401 A TW86101401 A TW 86101401A TW 374918 B TW374918 B TW 374918B
Authority
TW
Taiwan
Prior art keywords
cell array
memory cell
multilevel
multilevel memory
word line
Prior art date
Application number
TW086101401A
Other languages
English (en)
Inventor
Kiyokazu Hashimoto
Original Assignee
Nec Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Electronics Corp filed Critical Nec Electronics Corp
Application granted granted Critical
Publication of TW374918B publication Critical patent/TW374918B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
TW086101401A 1996-02-07 1997-02-05 Semiconductor memory device having multilevel memory cell array TW374918B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2082196A JP2976871B2 (ja) 1996-02-07 1996-02-07 半導体記憶装置

Publications (1)

Publication Number Publication Date
TW374918B true TW374918B (en) 1999-11-21

Family

ID=12037712

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086101401A TW374918B (en) 1996-02-07 1997-02-05 Semiconductor memory device having multilevel memory cell array

Country Status (4)

Country Link
US (1) US5838610A (zh)
JP (1) JP2976871B2 (zh)
KR (1) KR100232273B1 (zh)
TW (1) TW374918B (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6857099B1 (en) * 1996-09-18 2005-02-15 Nippon Steel Corporation Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
KR100259972B1 (ko) * 1997-01-21 2000-06-15 윤종용 메모리 셀당 2개 이상의 저장 상태들을 갖는 불휘발성 반도체 메모리 장치
JPH1115773A (ja) * 1997-06-24 1999-01-22 Matsushita Electron Corp 半導体集積回路、コンピュータシステム、データ処理装置及びデータ処理方法
KR100332950B1 (ko) * 1998-04-10 2002-08-21 삼성전자 주식회사 단일비트동작모드와다중비트동작모드를갖는불휘발성반도체메모리장치및그것의기입/독출방법
JP4282197B2 (ja) * 2000-01-24 2009-06-17 株式会社ルネサステクノロジ 不揮発性半導体記憶装置
US6185127B1 (en) * 2000-01-31 2001-02-06 Summit Microelectronics, Inc. Selectable analog functions on a configurable device and method employing nonvolatile memory
EP1193715A1 (en) * 2000-09-20 2002-04-03 STMicroelectronics S.r.l. Nonvolatile memory device, having parts with different access time, reliability and capacity
JP2005285190A (ja) * 2004-03-29 2005-10-13 Sanyo Electric Co Ltd メモリ
JP2006024342A (ja) * 2004-06-08 2006-01-26 Toshiba Corp 不揮発性半導体記憶装置、不揮発性半導体記憶装置の書き込み方法、メモリカード及びｉｃカード
KR100645050B1 (ko) 2004-10-21 2006-11-10 삼성전자주식회사 프로그램 특성을 향상시킬 수 있는 불 휘발성 메모리 장치및 그것의 프로그램 방법
ITVA20070042A1 (it) * 2007-04-27 2008-10-28 St Microelectronics Srl Metodo di gestione di un dispositivo di memoria e relativo dispositivo di memoria
ITVA20070026A1 (it) * 2007-03-02 2008-09-03 St Microelectronics Srl Metodo di gestione di una memoria tri-livello
KR101330710B1 (ko) 2007-11-01 2013-11-19 삼성전자주식회사 플래시 메모리 장치
JP2011123612A (ja) * 2009-12-09 2011-06-23 Sanyo Electric Co Ltd メモリ制御装置
US9437273B2 (en) * 2012-12-26 2016-09-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0148488B1 (en) * 1983-12-23 1992-03-18 Hitachi, Ltd. Semiconductor memory having multiple level storage structure
JP2768321B2 (ja) * 1995-02-28 1998-06-25 日本電気株式会社 半導体記憶装置

Also Published As

Publication number Publication date
US5838610A (en) 1998-11-17
JP2976871B2 (ja) 1999-11-10
KR970063252A (ko) 1997-09-12
KR100232273B1 (ko) 1999-12-01
JPH09213079A (ja) 1997-08-15

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