TW367414B - Parallel bit test circuit having common output driver and parallel bit test method using the same - Google Patents

Parallel bit test circuit having common output driver and parallel bit test method using the same

Info

Publication number
TW367414B
TW367414B TW087108711A TW87108711A TW367414B TW 367414 B TW367414 B TW 367414B TW 087108711 A TW087108711 A TW 087108711A TW 87108711 A TW87108711 A TW 87108711A TW 367414 B TW367414 B TW 367414B
Authority
TW
Taiwan
Prior art keywords
parallel bit
bit test
drivers
data line
comparison circuit
Prior art date
Application number
TW087108711A
Other languages
English (en)
Inventor
Byung-Chul Kim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW367414B publication Critical patent/TW367414B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
TW087108711A 1998-03-23 1998-06-03 Parallel bit test circuit having common output driver and parallel bit test method using the same TW367414B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980009964A KR100322525B1 (ko) 1998-03-23 1998-03-23 출력드라이버를공유하는병렬비트테스트회로및이를이용한병렬비트테스트방법

Publications (1)

Publication Number Publication Date
TW367414B true TW367414B (en) 1999-08-21

Family

ID=19535233

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087108711A TW367414B (en) 1998-03-23 1998-06-03 Parallel bit test circuit having common output driver and parallel bit test method using the same

Country Status (4)

Country Link
US (1) US6442717B1 (zh)
JP (1) JP3661979B2 (zh)
KR (1) KR100322525B1 (zh)
TW (1) TW367414B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6775193B1 (en) 2003-04-01 2004-08-10 Giga Semiconductor, Inc. System and method for testing multiple embedded memories
KR100699827B1 (ko) * 2004-03-23 2007-03-27 삼성전자주식회사 메모리 모듈
KR100557225B1 (ko) * 2004-11-04 2006-03-07 삼성전자주식회사 반도체 메모리 장치의 데이터 입/출력 방법 및 이를 위한반도체 메모리 장치
KR100694418B1 (ko) 2004-11-15 2007-03-12 주식회사 하이닉스반도체 메모리 장치의 병렬 압축 테스트 회로
KR100733409B1 (ko) 2005-09-29 2007-06-29 주식회사 하이닉스반도체 테스트 제어 장치 및 이를 포함하는 반도체 메모리 장치
US20070208968A1 (en) * 2006-03-01 2007-09-06 Anand Krishnamurthy At-speed multi-port memory array test method and apparatus
KR100809070B1 (ko) * 2006-06-08 2008-03-03 삼성전자주식회사 반도체 메모리 장치의 병렬 비트 테스트 회로 및 그 방법
JP5448698B2 (ja) 2009-10-09 2014-03-19 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びそのテスト方法
KR101062845B1 (ko) 2010-03-31 2011-09-07 주식회사 하이닉스반도체 글로벌 라인 제어회로
JP2012083243A (ja) 2010-10-13 2012-04-26 Elpida Memory Inc 半導体装置及びそのテスト方法
JP5654855B2 (ja) 2010-11-30 2015-01-14 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
KR20210122942A (ko) * 2020-04-01 2021-10-13 삼성전자주식회사 메모리 장치 및 그것의 테스트 방법

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US3772595A (en) * 1971-03-19 1973-11-13 Teradyne Inc Method and apparatus for testing a digital logic fet by monitoring currents the device develops in response to input signals
US3921142A (en) * 1973-09-24 1975-11-18 Texas Instruments Inc Electronic calculator chip having test input and output
US4363124A (en) * 1980-06-26 1982-12-07 International Business Machines Corp. Recirculating loop memory array tester
JPS63257999A (ja) * 1987-04-15 1988-10-25 Mitsubishi Electric Corp 半導体記憶装置
US5127011A (en) * 1990-01-12 1992-06-30 International Business Machines Corporation Per-pin integrated circuit test system having n-bit interface
JP2806026B2 (ja) 1990-09-26 1998-09-30 ヤマハ株式会社 メモリテスト回路
JPH0554641A (ja) 1991-08-28 1993-03-05 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR950001293B1 (ko) * 1992-04-22 1995-02-15 삼성전자주식회사 반도체 메모리칩의 병렬테스트 회로
JP3293935B2 (ja) * 1993-03-12 2002-06-17 株式会社東芝 並列ビットテストモード内蔵半導体メモリ
US5646948A (en) * 1993-09-03 1997-07-08 Advantest Corporation Apparatus for concurrently testing a plurality of semiconductor memories in parallel
US5912850A (en) * 1995-08-03 1999-06-15 Northern Telecom Limited Multi-port RAM with shadow write test enhancement
KR100197554B1 (ko) * 1995-09-30 1999-06-15 윤종용 반도체 메모리장치의 고속테스트 방법
US5734613A (en) * 1996-06-20 1998-03-31 Northern Telecom Limited Multi-port random access memory
JP3866818B2 (ja) * 1997-02-14 2007-01-10 三菱電機株式会社 半導体記憶装置
US5754486A (en) * 1997-02-28 1998-05-19 Micron Technology, Inc. Self-test circuit for memory integrated circuits
JP3833341B2 (ja) * 1997-05-29 2006-10-11 株式会社アドバンテスト Ｉｃ試験装置のテストパターン発生回路
US6032274A (en) * 1997-06-20 2000-02-29 Micron Technology, Inc. Method and apparatus for compressed data testing of more than one memory array
US5910923A (en) * 1997-10-23 1999-06-08 Texas Instruments Incorporated Memory access circuits for test time reduction

Also Published As

Publication number Publication date
KR100322525B1 (ko) 2002-06-22
JP3661979B2 (ja) 2005-06-22
KR19990075641A (ko) 1999-10-15
JPH11339499A (ja) 1999-12-10
US6442717B1 (en) 2002-08-27

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees