TW355833B - Method of manufacturing a radiation-resistant semiconductor integrated circuit - Google Patents
Method of manufacturing a radiation-resistant semiconductor integrated circuitInfo
- Publication number
- TW355833B TW355833B TW085110503A TW85110503A TW355833B TW 355833 B TW355833 B TW 355833B TW 085110503 A TW085110503 A TW 085110503A TW 85110503 A TW85110503 A TW 85110503A TW 355833 B TW355833 B TW 355833B
- Authority
- TW
- Taiwan
- Prior art keywords
- radiation
- conductivity type
- manufacturing
- integrated circuit
- semiconductor integrated
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 230000005855 radiation Effects 0.000 title 1
- 239000012535 impurity Substances 0.000 abstract 3
- 150000002500 ions Chemical class 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 206010073306 Exposure to radiation Diseases 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7231715A JP2778550B2 (ja) | 1995-09-08 | 1995-09-08 | 半導体集積回路の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW355833B true TW355833B (en) | 1999-04-11 |
Family
ID=16927887
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW085110503A TW355833B (en) | 1995-09-08 | 1996-08-29 | Method of manufacturing a radiation-resistant semiconductor integrated circuit |
Country Status (5)
Country | Link |
---|---|
US (1) | US6146977A (zh) |
JP (1) | JP2778550B2 (zh) |
KR (1) | KR100262235B1 (zh) |
CN (1) | CN1152798A (zh) |
TW (1) | TW355833B (zh) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6320245B1 (en) | 1998-05-19 | 2001-11-20 | Nec Corporation | Radiation-hardened semiconductor device |
EP1542289A1 (fr) * | 2003-12-11 | 2005-06-15 | STMicroelectronics S.A. | Structure MOS résistante aux radiations |
KR100672708B1 (ko) * | 2004-12-30 | 2007-01-22 | 동부일렉트로닉스 주식회사 | 시모스 이미지 센서의 격리막 형성방법 |
KR100657130B1 (ko) * | 2005-12-27 | 2006-12-13 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
CN100373585C (zh) * | 2006-03-17 | 2008-03-05 | 中国科学院上海微系统与信息技术研究所 | 提高金属氧化物半导体器件场区抗总剂量的加固方法 |
JP2011512026A (ja) * | 2008-01-17 | 2011-04-14 | リルジャ,クラス,オロフ | ソフト−エラー・ハード・エレクトロニクス及び耐放射線論理セルのためのレイアウト方法 |
US9083341B2 (en) | 2008-01-17 | 2015-07-14 | Robust Chip Inc. | Soft error resilient circuit design method and logic cells |
CN102110692A (zh) * | 2011-01-24 | 2011-06-29 | 中国电子科技集团公司第五十八研究所 | 抗辐照eeprom存储阵列隔离结构 |
CN102522424B (zh) * | 2011-12-23 | 2014-04-30 | 北京大学 | 一种减小电荷共享效应的cmos器件及其制备方法 |
US8652929B2 (en) | 2011-12-23 | 2014-02-18 | Peking University | CMOS device for reducing charge sharing effect and fabrication method thereof |
CN104752513B (zh) * | 2015-03-12 | 2017-11-21 | 西安电子科技大学 | 一种制备基于65nm工艺的冗余掺杂抗辐照MOS场效应管的方法 |
CN108565212A (zh) * | 2017-11-29 | 2018-09-21 | 珠海创飞芯科技有限公司 | 一种mos晶体管的制作方法及mos晶体管 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4261761A (en) * | 1979-09-04 | 1981-04-14 | Tektronix, Inc. | Method of manufacturing sub-micron channel width MOS transistor |
JPS61226967A (ja) * | 1985-03-30 | 1986-10-08 | Toshiba Corp | Mis型半導体装置 |
US4987093A (en) * | 1987-04-15 | 1991-01-22 | Texas Instruments Incorporated | Through-field implant isolated devices and method |
NL8802219A (nl) * | 1988-09-09 | 1990-04-02 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumlichaam waarin door ionenimplantaties halfgeleidergebieden worden gevormd. |
JP2822278B2 (ja) * | 1991-03-05 | 1998-11-11 | 呉羽化学工業株式会社 | 塩化ビニル系単量体の懸濁重合方法 |
JPH0653232A (ja) * | 1992-08-03 | 1994-02-25 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5240874A (en) * | 1992-10-20 | 1993-08-31 | Micron Semiconductor, Inc. | Semiconductor wafer processing method of forming channel stops and method of forming SRAM circuitry |
US5405788A (en) * | 1993-05-24 | 1995-04-11 | Micron Technology, Inc. | Method for forming and tailoring the electrical characteristics of semiconductor devices |
KR0152909B1 (ko) * | 1994-10-21 | 1998-12-01 | 문정환 | 반도체장치의 격리구조의 제조방법 |
JPH08125180A (ja) * | 1994-10-25 | 1996-05-17 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5556798A (en) * | 1994-12-01 | 1996-09-17 | United Microelectronics Corp. | Method for isolating non-volatile memory cells |
-
1995
- 1995-09-08 JP JP7231715A patent/JP2778550B2/ja not_active Expired - Lifetime
-
1996
- 1996-08-29 TW TW085110503A patent/TW355833B/zh active
- 1996-09-05 KR KR1019960038332A patent/KR100262235B1/ko not_active IP Right Cessation
- 1996-09-06 CN CN96112904A patent/CN1152798A/zh active Pending
- 1996-09-06 US US08/709,151 patent/US6146977A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR970018223A (ko) | 1997-04-30 |
JP2778550B2 (ja) | 1998-07-23 |
US6146977A (en) | 2000-11-14 |
JPH0982793A (ja) | 1997-03-28 |
CN1152798A (zh) | 1997-06-25 |
KR100262235B1 (ko) | 2000-07-15 |
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