TW322613B - Continuous method of implementing solder bump on semiconductor wafer electrode - Google Patents

Continuous method of implementing solder bump on semiconductor wafer electrode Download PDF

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Publication number
TW322613B
TW322613B TW086102912A TW86102912A TW322613B TW 322613 B TW322613 B TW 322613B TW 086102912 A TW086102912 A TW 086102912A TW 86102912 A TW86102912 A TW 86102912A TW 322613 B TW322613 B TW 322613B
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continuous method
barrier layer
item
diffusion barrier
layer
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TW086102912A
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guang-long Lin
Jyh-Mey You
Wenn-Shiuan Jaw
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guang-long Lin
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Priority to TW086102912A priority Critical patent/TW322613B/zh
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Priority to US09/037,635 priority patent/US6153503A/en

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Description

經濟部中央橾準局貝工消费合作社印裝 3^2613 A7 B7 ―一 ...-.- -- ――-.--五、發明説明（1 ) 發明領域 本發明係關於一種用於覆晶接合電子構裝技術之矽晶 片的焊錫隆點的製作方法，尤其有關一種以波焊技術方法 製作該焊錫隆點的連續方法。 發明背景 電^子構裝技術之發展，是電子相關產品如電腦、計算 機、1C卡....等功能提升與輕、薄、短、小化的關鍵，近 二十餘年來，電子元件之構裝技術早期是以雙排腳 (Dual-In-Line Package ’ DIP)技術爲主，導線架 (Lead Frame)以插腳方式植入印刷電路板的通孔 (Plated Through Hole)，再經由焊錫將之黏合，雙 排腳技術受限於導線架的生產技術，不易有高密度的輸出 入（I/O)數；插腳式的構裝技術，於80年代逐漸爲表面 黏著技術(Surface Mount Technology，SMT)所 取代，此技術之輸出入數可較爲提升，其技術重點之一在 於能更自動化的生產，是目前電子構裝的技術主流；表面 黏著技術的成熟運用，進而促成了多晶片模組 (Multichip Module，MCM)近年來蓬勃發展，國際 間相關的硏究報告甚多，亦有專門性的學術硏討會專注於 多晶片模組構裝技術之討論，此技術使得產品體積能更縮 /J、〇 多晶片模組技術種類很多，因黏著基板的不同，有 MCM-C (陶瓷基板），MCM-P (高分子基板），MCM- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ^装------訂------ (請先閲讀背面之注意事項再填寫本頁) 3226i3 Α7 _—_Β7_ 五、發明説明（2 ) (請先閱讀背面之注意事項再填寫本頁)
Si (矽晶基板），MCM-D (薄膜鍍著）等；於多晶片模 組技術中’以矽晶片與基板接合技術來區分，則又可分爲 打線接合（Wire Bonding)，捲帶式自動接合（Tape Automatic Bonding，TAB)，以及覆晶接合（Flip Chip Bonding)等三種；打線接合以及捲帶式自動接合 技術’限於接點空間幾合之安排，矽晶片上接點必須是設 計於晶_片之周圍（Peripheral)，執是之故，接點數有 限’單一晶片之接點數，TAB可達600左右，打線接合更 少’但覆晶接合可達1600之譜，此差異之主因在於覆晶 接合技術的接點可設計成矩陣，完全利用晶片的表面積， 此技術最早爲I B Μ於1 9 6 0年代所硏發，但因專利關係， 直至近年才廣爲電子工業界所重視並積極投入發展。· 麵濟部中夹株準局貝工消費合作社印製 覆晶接合（英文又稱Controlled Collapse Chip Connection，C4)技術排除了接線與接腳（Lead)所 需的空間，使得晶片可直接黏著於基板上，此爲直接基板 黏晶（Chip on Board)技.術，或稱裸晶接合（Bare Chip Bonding)技術，可大幅省略封膠需求，提高晶片 本身輸出入或集積密度，並提升基板黏合的晶片密度；覆 晶接合技術的關鍵在於必須配合基板線路與晶片本身線路 設計之需求，於晶片上直接製作接合晶片所需的接點，此 接點通常爲焊錫隆點（Solder Bump)，其視製程溫度之 需要，選擇不同熔點的焊錫合金材料。焊錫隆點通常以對 位（Alignment)方式與基板的焊錫墊（Bump Pad) 接合，藉重流（Reflow)將晶片黏著於基板上。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局貞工消费合作社印製 A7 _____B7_ 五、發明説明（3 ) “片上的焊錫隆點之製作方式，目前多以物理氣相蒸 鍍(Physical Vapor Deposition，PVD )或電鍍 (Electroplating)爲主，先藉光罩顯影技術製作所需 隆點樣式（Pattern)，再以兩種技術之一鍍上焊錫，此 兩種技術，目前均甚成熟，但均具有鍍層成長速度慢、分 批式生產流程較不易連續自動化等共同缺點。 夂，物理氣相蒸鍍以熱蒸發（Thermal Evaporation )蒸鍍爲主，但其蒸鍍速度慢，長時間 鍍，以及氣相凝結之結果，會使晶片長久承受高溫與能 量，導致溫度上升，甚至造成鍍上之焊錫再熔融。 而電鍍之製程又較物理氣相琴鍍複雜，其鍍層亦即焊 錫隆點高度之控制受制於電流密度分佈之影響，欲獲致高 度均勻的焊錫隆點，有賴於電鍍槽的設計。且電鍍所得之 焊錫隆點表面爲平坦狀，必須再經重流才能獲致圓弧狀之 表面以利接合。 由上述知，至目前止，製作焊錫隆點的先前技術，一 則費時，另則焊錫隆點品質不易控制。 發明要旨 本發明之主要目的即在提出一種以目前電子工業界所 極易接受與投入之波焊（Wave Soldering)技術於半導體 晶片之電極上製作焊錫隆點的連續方法，具有可連續製 作、製程簡易及迅速的優點。 爲達成上述目的，一依照本發明內容而完成的於半導 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） ------------ (請先閲讀背面之注意事項再填寫本頁) 訂 吻6!3 A7 __B7_ 五、發明説明（4 ) < 體晶片之電極上製作焊錫隆點的連續方法，包含下列步 驟： a) 於一半導體晶圓之複數個半導體晶片的電極上形成 一擴散障礙層； b) 於該擴散障礙層上形成一潤濕層； c) 將複數個具有該擴散障礙層及潤濕層的半導體晶 圓，以該擴散障礙層及潤濕層朝向地面的方式連續通過一 熔融焊錫波面，並讓該等半導體晶圓具擴散障礙層及潤濕 層的一表面與該熔融焊錫波面接觸，於是在該潤濕層表面 上形成焊錫隆點，且在除了該擴散障礙層及潤濕層以外的 半導體晶片表面上實質上不形成有焊錫隆點。 於本發明方法中，該熔融焊錫波面可使用一溫度介於 210 °C至360 °C之鉛錫合金而形成。 於本發明方法中，較佳的，該等半導體晶圓於通過該 熔融焊錫波面之前被預熱至一介於150 °C至200 °C的溫 度。較佳的，該等半導體晶片被預熱的時間介於20秒至 4 0秒。 經濟部中央揉準局貞工消费合作社印製 (請先閲讀背面之注意事項再填寫本頁) 於本發明方法中，較佳的，該等半導體晶圓與該熔融 焊錫波面接觸的時間介於3秒至7秒。 於本發明方法中，較佳的，該等半導體晶片通過該熔 融焊錫波面的速度介於1 . 0 m / m i η至2 . 5 m / m i η。 選擇性的，形成於該潤濕層上的焊錫隆點被進一步施 予一助熔劑並加熱重流之，而加高該焊錫隆點的高度。 適合用於作爲本發明方法中的潤濕層的材料例如爲 本紙張又度適用中國國家標準（CNS ) Α4规格（210X297公釐） 經濟部中央梯準局貝工消費合作杜印裝 A7 B7 五、發明説明（5 )
Au、Pd ' Cu、Sn、Ag、Cr及其等彼此之間的合金。 適合用於作爲本發明方法中的擴散障礙層的材料包括 (但不限於）Mo、MoN、Ni、非電鍍Ni及TiN。 於本發明方法中，較佳的，該擴散障礙層係使用一用 於形成該半導體晶片之電極的樣式化光阻作爲罩層進行濺 鍍而形成。該潤濕層係接著該擴散障礙層之濺鍍後，繼續 濺鍍另一種材料，及剝除該樣式化光阻罩層而形成。 圖示之簡單說明： 圖一爲本發明方法中製作焊錫隆點下方金屬（Under Bump Metallurgies，簡稱 UMB)的流程圖。 圖二爲依本發明方法之一第一實施例所製作焊錫隆點 下方金屬（ 5 0 0 0 A A 1 / 5 0 0 0 A Mo/ 5 0 0 0 A Pd)的歐傑縱 深分析圖。 圖三爲依本發明方法之一第二實施例所製作焊錫隆點 下方金屬（ 5 0 0 0 A A 1 / 5 0 0 0 A γ-Μο2Ν/ 5 0 0 0 Α Pd)的 歐傑縱深分析圖。 圖四爲依本發明方法之一第三實施例於一矽晶圓 (3 . 0英吋）所製得焊錫隆點的放大照片，其中該矽晶圓 有8X8組矽晶片，每片矽晶片有20X20個lOOemX 100 # m大小之焊錫隆點。 圖五爲圖四之進一步放大照片。 圖六依本發明方法之一第四實施例於一矽晶圓（3.0 英吋）所製得焊錫隆點的放大照片，其中該矽晶圓有8X8 • 7 - 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） ----------^------訂------Λ>- (請先閲讀背面之注意事項再填寫本頁) 經濟部中央梯準局負工消费合作社印製 A7 B7 五、發明説明（6 ) 組矽晶片，每片矽晶片有20X20個100//mX100ym大 小之焊錫隆點。 圖七爲圖六之進一步放大照片。 圖八依本發明方法之一第五實施例於一矽晶圓（3.0 英吋）所製得焊錫隆點的放大照片，其中該矽晶圓有8 X 8 組矽晶片，每片矽晶片有20X20個100emX100；am大 小之焊錫隆點。 圖九爲圖八之進一步放大照片。 圖十依本發明方法之一第三實施例於一矽晶圓（3.0 英吋）所製得焊錫隆點[A丨（5000Α)/γ-Μ〇2Ν(5000Α) /Pd(5000A)/63Sn-37Pb的歐傑縱深分析圖，其中該焊 錫隆點經1 5 0 °C熱處理1 0 0 0小時。 較佳具體實施例的詳細說明 本發明的製程包含於一半導體晶圓（例如矽晶圓）的金 屬電極（例如鋁電極）上形成焊錫隆點下方金屬（U n d e r Bump Metallurgies，簡稱UMB)，再於其上藉波焊技 術形成焊錫隆點。該焊錫隆點下方金屬包含一形成於該金 屬電極上的擴散障礙層，及形成於該擴散障礙層上的潤濕 層。 於一半導體晶圓的金屬電極上形成焊錫隆點下方金屬 UMB的較佳實例方式如圖一流程圖所示。於一矽晶圓上 藉旋轉塗覆（Spin Coating)的方法塗覆一層光阻，塗 覆後的晶圓，於90°C軟烤20分鐘之後，覆蓋一光罩，例 -8 ¥紙張尺度適用中國國家樣準（CNS ) A4規格（210X297公釐） 一 ----------------訂------4 ί (請先閱讀背面之注意事項再填寫本頁) 經濟部中央楯準局貝工消費合作社印製 A7 B7 五、發明説明（7 ) 如以膠片製作具8X8個晶片組，每個晶片可有20X20或 其它焊錫隆點樣式（Pattern) ’每個焊錫隆點大小可爲 100#mXl00#m，或其它如lmmXlmm，間距可爲 2 5 0 # m ;覆蓋光罩後即在黃光室進行曝光與顯影，顯影 後矽晶片隨即進行眞空濺鍍電極，例如3000A〜5000A 之鋁薄膜，以及焊錫擴散障礙層，例如3000A〜5000A 之鉬或氮化鉬薄膜，於該擴散障礙層之上再濺鍍一’潤濕 層，例如3000A〜5000A之鈀薄膜；濺鍍後之半導體晶 圓以適當之溶劑，例如丙酮，浸漬以進行剝膜（L i ft off )而去除該光阻，獲致具樣式化UMB之晶圓。此具樣 式化UMB之晶圓即可在不使用一助熔劑或藉助一助熔劑 下於該UMB上以波焊技術形成焊錫隆點。 將複數個此等具樣式化UMB之晶圓分別置於複數個 夾治具上，再以一波焊錫機之輸送帶輸送晶圓通過該波焊 錫機之一焊錫槽內的熔融焊鍚之波面進行波焊，波焊之預 熱溫度可爲150 °C〜200 °C，該焊錫槽之焊錫成份可爲 63Sn-37Pb或其它常見之焊錫成份如95Pb-5Sn等，該 焊錫槽之焊錫的溫度可爲210 °C〜360 °C，視焊錫成份而 定，晶圓輸送速度可爲1.0 m/min〜2.5 m/min，如此 以一般波焊錫設備而言，自預熱至完成製作焊錫隆點所需 時間僅爲_分鐘左右。 上述之夾治具，以鋁合金板製成具與晶圓大小相同之 孔槽，孔槽內壁下方有凸緣以支撐平放該具樣式化UMB 之晶圓，於製作焊錫隆點時，該具樣式化UMB之晶圓擬 -9 - 本紙張尺度適用中國國家梂準（CNS ) A4規格（210>：297公釐） —----------- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局貝工消费合作社印裝 A7 ___B7_ 五、發明説明（8 ) 製作焊錫隆點之面朝下置於該夾治具之孔槽內並且使得該 等樣式化UMB暴露於該夾治具之孔槽。 經上述製程即可連續地製作適當之焊錫隆點於矽晶片 之電極上。本發明之特點包括以適當之潤濕層進行焊錫， 不需一般焊錫習用之助熔劑（Flux，或稱助焊劑）；焊 錫隆點係以工業界極易接受之波焊設備行之；以波焊技術 製作焊錫隆點不具有先前技藝之蒸鍍與電鍍製作焊錫隆點 的缺點；及以波焊製作焊錫隆點具有製程簡易、迅速，易 於與連續製程配合。 依上述焊錫隆點之製作方法，所製作之焊錫隆點及相 關步驟之部份實施例如下述。 實施例一 依圖一之流程，於一矽晶圓上依序眞空濺鍍鋁電極及 UMB，其中該鋁電極及UMB爲5 0 0 0A A1/5 0 00A Mo/5000A Pd所組成。以歐傑（Auger)縱深分析 (Depth Profile)法分析該鋁電極及UMB，結果如圖 二所示。從圖二可以看出，在開始分析50kseC內只有Pd 元素，介於l〇〇-150ksec期間只有Mo元素，而200ksec 後則只有A1元素，顯示作爲擴散障礙層的Mo有效的隔絕 了該鋁電極與作爲潤濕層的Pd。 實施例二 依圖一之流程，於一矽晶圓上依序眞空濺鍍鋁電極及 -1 0 - 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央梯準局貝工消费合作杜印製 322exs a? _B7_ 五、發明説明（9 ) UMB，其中該鋁電極及UMB爲5 000A A1/5 0 0 0A r-Mo2N/5000A Pd所組成。以歐傑（Auger)縱深分析 (Depth Profile )法分析該鋁電極及UMB，結果如圖 三所示。從圖三可以看出，作爲擴散障礙層的M〇2N有效 的隔絕了該鋁電極與作爲潤濕層的P d。 實施例三 依圖一之流程於一矽晶圓上依序眞空濺鍍鋁電極及 UMB，其中該矽晶圓上被形成有8X8組矽晶片，每片矽 晶片有20 X 20個大小爲100 y m X 100 // m之5000A A 1 / 5 0 0 0 A r -Mo2N/ 5 0 0 0 A Pd 的構造。 將該具有鋁電極及UMB的矽晶圓置於一夾治具上， 再以一波焊錫機之輸送帶輸送通過該波焊錫機之一焊錫槽 內的熔融63Sn-3 7Pb焊鍚之波面進行波焊，波焊之條件 爲預熱150 °C ，焊錫槽溫度275 °C ，輸送速度 1.9m/min。可得焊錫隆點如圖四與圖五所示， 實施例四 除了波焊條件中之輸送速度改爲1.3m/min外，重覆 實施例三的步驟。所獲得之焊錫隆點如圖六及七所示。 實施例五 除了波焊條件中之焊錫槽溫度改爲225 °C及輸送速度 改爲1.3m/min外，重覆實施例三的步驟。所獲得之焊錫 -11- 本紙張尺度逋用中國國家標準（CNS ) A4規格（210 X 297公釐） ------IT------Ϋ~'1 (請先閲讀背面之注意Ϋ項再填寫本頁) A7 _B7_ 五、發明説明（10 ) 隆點如圖八及九所示。 實施例六 實施例三〜五所製作之焊錫隆點平均高度爲左 右，經適當助熔劑之助，加以重流（R e Π 〇 w )其焊錫隆 點高度可達20#m左右》 實施例七 將上述實施例三製得的具焊錫隆點的矽晶圓以1 5 0 °C 熱處理1000小時後，以歐傑（Auger)縱深分析 (Depth Profile)法分析該焊錫隆點，結果如圖十所 示。從圖十可以看出，在開始分析120ksec後仍未出現 A1元素，顯示該擴散障礙層有效的防阻焊鍚向鋁電極擴 散。 本發明已經配合上述具體實施例被描述，熟悉本項技 藝人士將可基於以上描述作出多種變化。本發明的範圍包 括界定於下列申請專利範圍及其精神內的該等變化。 ----------^------.訂------^).1 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央柢準局員工消费合作社印装 -12- 本紙張尺度速用中國國家梂準（CNS ) A4規格（210X297公釐）

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  1. 8888 ABCD 經濟部中央標準局貝工消费合作社印製 六、申請專利祀圍 1. 一種於半導體晶片之電極上製作焊錫隆點的連續 方法，包含下列步驟： a) 於一半導體晶圓之複數個半導體晶片的電極上形成 一擴散障礙層； b) 於該擴散障礙層上形成一潤濕層； c) 將複數個具有該擴散障礙層及潤濕層的半導體晶 圓，以該擴散障礙層及潤濕層朝向地面的方式連續通過一 熔融焊錫波面，並讓該等半導體晶圓具擴散障礙層及潤濕 層的一表面與該熔融焊錫波面接觸，於是在該潤濕層表面 上形成焊錫隆點，且在除了該擴散障礙層及潤濕層以外的 半導體晶片表面上實質上不形成有焊錫隆點。 2. 如申請專利範圍第1項的連續方法，其中該熔融焊 錫波面係使用一溫度介於210 °C至360 °C之鉛錫合金而形 成。 3. 如申請專利範圍第1項的連續方法，其中該等半導 體晶圓於通過該熔融焊錫波面之前被預熱至一介於150。(： 至200 °C的溫度。 4. 如申請專利範圍第1項的連續方法，其中該等半導 體晶圓與該熔融焊錫波面接觸的時間介於3秒至7秒。 5 .如申請專利範圍第2項的連續方法，其中該給錫合 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------------1T------1,1 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消费合作社印装 A8 B8 C8 D8 六、申請專利範圍 金爲 6 3 S η - 3 7 P b 或 9 5 P b - 5 S η ° 6.如申請專利範圍第1項的連續方法，其中該等半導 體晶圓被預熱的時間介於2 0秒至4 0秒。 7·如申請專利範圍第1項的連續方法，其中該等半導 體晶圓通過該熔融焊錫波面的速度介於1 ·〇 m/min至2.5 8. 如申請專利範圍第1項的連續方法，其中該潤濕層 上所形成的焊錫隆點被進一步施予一助溶劑並加熱重流 之，而加高該焊錫隆點的高度。 9. 如申請專利範圍第1項的連續方法，其中該潤濕層 爲Au、Pd、Cu ' Sn、Ag或Cr或其等彼此之間的合金。 10. 如申請專利範圍第1項的連續方法，其中該擴散障 礙層爲Mo、MoN、Ni、非電鍍Ni或TiN。 11. 如申請專利範圍第1項的連續方法，其中該擴散障 礙層的厚度介於3 0 0 0埃至5 0 0 0埃。 12. 如申請專利範圍第1項的連續方法，其中該潤濕層 的厚度介於3 0 0 0埃至5 0 0 0埃。 本紙張尺度適用中國國家揉準（CNS > A4規格（210X297公釐） -----------------訂------4 ί (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印裝 ^22613 as B8 C8 1 D8 六、申請專利範圍 13.如申請專利範圍第丨項的連續方法，其中該擴散障 礙層係使用一用於形成該半導體晶片之電極的樣式化光阻 作爲罩層進行濺鍍而形成。 1 4 ·如申請專利範圍第1 3項的連續方法，其中該潤濕 層係接著該擴散障礙層之濺鍍後，繼續濺鍍另一種材料， 及剝除該樣式化光阻罩層而形成。 本紙張尺度適用中國國家橾準（CNS ) A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6989294B1 (en) * 1998-06-10 2006-01-24 Asat, Ltd. Leadless plastic chip carrier with etch back pad singulation
US6229200B1 (en) 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US8330270B1 (en) 1998-06-10 2012-12-11 Utac Hong Kong Limited Integrated circuit package having a plurality of spaced apart pad portions
KR100447968B1 (ko) 2001-08-07 2004-09-10 주식회사 하이닉스반도체 웨이퍼 레벨 패키지의 제조방법
TW529143B (en) * 2001-12-03 2003-04-21 Advanced Semiconductor Eng Method for producing under-bump metallurgy layer (UBM)
US6756294B1 (en) * 2002-01-30 2004-06-29 Taiwan Semiconductor Manufacturing Company Method for improving bump reliability for flip chip devices
US6596619B1 (en) 2002-05-17 2003-07-22 Taiwan Semiconductor Manufacturing Company Method for fabricating an under bump metallization structure
US6703069B1 (en) * 2002-09-30 2004-03-09 Intel Corporation Under bump metallurgy for lead-tin bump over copper pad
JP2007501111A (ja) * 2003-08-04 2007-01-25 チバ　スペシャルティ　ケミカルズ　ホールディング　インコーポレーテッド 強く付着しているコーティングの製造方法
US7179670B2 (en) 2004-03-05 2007-02-20 Gelcore, Llc Flip-chip light emitting diode device without sub-mount
US7918383B2 (en) * 2004-09-01 2011-04-05 Micron Technology, Inc. Methods for placing substrates in contact with molten solder
US9070851B2 (en) 2010-09-24 2015-06-30 Seoul Semiconductor Co., Ltd. Wafer-level light emitting diode package and method of fabricating the same
US9227257B2 (en) 2012-04-24 2016-01-05 Seagate Technology Llc Laser subassembly metallization for heat assisted magnetic recording
US8863068B2 (en) * 2012-06-18 2014-10-14 International Business Machines Corporation Current-aware floorplanning to overcome current delivery limitations in integrated circuits
US8826203B2 (en) 2012-06-18 2014-09-02 International Business Machines Corporation Automating current-aware integrated circuit and package design and optimization
CN205944139U (zh) 2016-03-30 2017-02-08 首尔伟傲世有限公司 紫外线发光二极管封装件以及包含此的发光二极管模块

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053357A (en) * 1989-12-27 1991-10-01 Motorola, Inc. Method of aligning and mounting an electronic device on a printed circuit board using a flexible substrate having fixed lead arrays thereon
US5252180A (en) * 1990-05-17 1993-10-12 Xerox Corporation Electrical contacts for an electro-optic modulator
US5316788A (en) * 1991-07-26 1994-05-31 International Business Machines Corporation Applying solder to high density substrates
US5311404A (en) * 1992-06-30 1994-05-10 Hughes Aircraft Company Electrical interconnection substrate with both wire bond and solder contacts
US5376584A (en) * 1992-12-31 1994-12-27 International Business Machines Corporation Process of making pad structure for solder ball limiting metallurgy having reduced edge stress
US5300461A (en) * 1993-01-25 1994-04-05 Intel Corporation Process for fabricating sealed semiconductor chip using silicon nitride passivation film
US5831828A (en) * 1993-06-03 1998-11-03 International Business Machines Corporation Flexible circuit board and common heat spreader assembly
US5511306A (en) * 1994-04-05 1996-04-30 Compaq Computer Corporation Masking of circuit board vias to reduce heat-induced board and chip carrier package warp during wavesolder process
US5493075A (en) * 1994-09-30 1996-02-20 International Business Machines Corporation Fine pitch solder formation on printed circuit board process and product
US5642265A (en) * 1994-11-29 1997-06-24 Sgs-Thomson Microelectronics, Inc. Ball grid array package with detachable module
US5492235A (en) * 1995-12-18 1996-02-20 Intel Corporation Process for single mask C4 solder bump fabrication
US5531021A (en) * 1994-12-30 1996-07-02 Intel Corporation Method of making solder shape array package
US5795619A (en) * 1995-12-13 1998-08-18 National Science Council Solder bump fabricated method incorporate with electroless deposit and dip solder
US5773359A (en) * 1995-12-26 1998-06-30 Motorola, Inc. Interconnect system and method of fabrication
AU6279296A (en) * 1996-06-12 1998-01-07 International Business Machines Corporation Lead-free, high tin ternary solder alloy of tin, silver, and indium
US5910354A (en) * 1997-03-04 1999-06-08 W.L. Gore & Associates, Inc. Metallurgical interconnect composite

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