TW313668B - - Google Patents
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- Publication number
- TW313668B TW313668B TW086101352A TW86101352A TW313668B TW 313668 B TW313668 B TW 313668B TW 086101352 A TW086101352 A TW 086101352A TW 86101352 A TW86101352 A TW 86101352A TW 313668 B TW313668 B TW 313668B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- cold cathode
- semiconductor wafer
- mounting
- fixing
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims description 57
- 235000012431 wafers Nutrition 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 38
- 239000004065 semiconductor Substances 0.000 claims description 30
- 239000000853 adhesive Substances 0.000 claims description 29
- 230000001070 adhesive effect Effects 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 22
- 238000009434 installation Methods 0.000 claims description 12
- 239000006023 eutectic alloy Substances 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 229920001169 thermoplastic Polymers 0.000 claims description 2
- 229920001187 thermosetting polymer Polymers 0.000 claims description 2
- 239000004416 thermosoftening plastic Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 12
- 238000005520 cutting process Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 238000003466 welding Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010894 electron beam technology Methods 0.000 description 5
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- QUCZBHXJAUTYHE-UHFFFAOYSA-N gold Chemical compound [Au].[Au] QUCZBHXJAUTYHE-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 206010028980 Neoplasm Diseases 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 201000011510 cancer Diseases 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 230000002079 cooperative effect Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
- H01J1/02—Main electrodes
- H01J1/30—Cold cathodes, e.g. field-emissive cathode
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- H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
- H01J29/46—Arrangements of electrodes and associated parts for generating or controlling the ray or beam, e.g. electron-optical arrangement
- H01J29/48—Electron guns
- H01J29/485—Construction of the gun or of parts thereof
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- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
- H01J9/02—Manufacture of electrodes or electrode systems
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- H01J9/02—Manufacture of electrodes or electrode systems
- H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
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- H01J9/02—Manufacture of electrodes or electrode systems
- H01J9/18—Assembling together the component parts of electrode systems
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Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes For Cathode-Ray Tubes (AREA)
- Cold Cathode And The Manufacture (AREA)
Description
經濟部中央標準局員工消費合作社印製 ^^3668 A7 B7 五、發明説明(1 ) 本發明係有關於基板上固接半導體晶片之方法及其結 構。 最近已有人開發出電子場致發射冷陰極以作爲電子餘 等的電子源。圖4係顯示出此電子場致發射冷陰極的剖 面。冷陰極30係,一般爲在半導體基板31上將數百個至 數萬個微小突起的射極32配置成圓形或正方形等形狀,藉 此以形成用來發射電子之發射區域33 ;爲了將強電場施Z 在微小突起的射極上,故介由絕緣層35而在射極32的上 方形成有閘電極34。 電子場致發射冷陰極係,當在閘電極34與射極32間 施加電壓時,電場會集中在射極32之尖尖的前端部,藉此 從射極32會發射出對應於自此頂點至兩電極間的電位差 又電子。當射極的微小突起之直徑爲! " m,在射極& 與閘電極34間施加50〜100V電壓時,會有約! " A之電 子自各射極發射出。因此,通常使用於陰極射線管之電子 場致發射冷陰極,雖然形成有數千〜數萬個微小突起的射 極,但由於1個射極之直徑小到丨"m,故所形成之發射 區域的大小爲數百"m見方。 圖5係顯示用來安裝電子場效發射冷陰極之電子鎗呤 極結構體的剖面圖。安裝著冷陰極41之套f 43被絕緣^ 44固定在外側陰極支持體45上。4〇代表接線,ο代表^ 陰極的發射區域,49代表接續埠。又,46代表第】拇極, 47代表第2柵極。且,由於電子鎗之特性係藉由冷陰極μ 的發射區域42與第i柵極46之位置關係的精度以決 本紙張尺度朝巾®®丨;(GNS) A4· ( 21Qx297公楚- ---------^! 1 - (請先閲讀背面之注意事項再填寫本頁) 訂 .I I -1 - In 經濟部中央標準局員工消費合作社印製 A7 _______B7 五、發明説明(2 ) " --- 出,故前述位置關係之精度必須要求爲高精度。 接著使用特開平7_161304號公叔所揭示出之技術以 説明習知之使用冷陰極的陰極結構體。圖6(a)係特開平7_ 161304號公報之陰極結構體的斜視圖;圖6(b)係a a,線的 剖面圖。陰極構造體50具有頂面形成有窗孔51之帽狀的 晶片固定具52 ;電子場效發射冷陰極係,其發射區域53 由此晶片固定具S2的窗孔露出,其接觸區域54係固定 成與窗孔51之裡面周緣部相接觸。如圖6所示般,電子場 致發射冷陰極係藉由彈性接續片61而抵壓在晶片支持具 52上。此習知例之特徵在於,冷陰極與閘電極間之接續未 使用配線,而是採用將冷陰極抵壓在晶片支持具上。 接著使用圖7以説明陰極射線管的構造。由陰極結構 體71之冷陰極所發射之電子束78係,經由配置在陰極結 構體71的對面之由第丨〜第6柵極構成之電子鎗72的電子 透鏡以進行聚焦,當通過遮蔽罩73後,最後衝擊至螢光幕 77而發出所望之色。用來構成螢光幕77的各色之各個畫 .T、之螢光體點之典型大小爲直徑丨〇〇 " m,故電子束78 形成在螢光幕77上之點徑必須具有可同時照射複數個螢 光體單元之大小。 又’在大型陰極射線管中,由於在陰柘射線管端面具 有球面相差之問題,故電子束之點徑會有變大的傾向,因 此必須使得點徑更加微小化。因此,電子透鏡之組合精度 會變知相當南’由數"m至1 m。亦即,電子鎗之組 裝精度必須限定在電子束的聚焦分布及螢光面的位置分布 ^------1T------1 4 » - · (請先閱讀背面之注意事項再填寫本頁) 5 經濟部中央標準局員工消費合作社印製 〇136β8 A7 B7五、發明説明(3 ) 可容許之範圍内。 此處之重點在於,在使用冷陰極之電子鎗中,聚焦至 螢光體單元之像爲冷陰極的發射區域之點光源像。因此, 冷陰極之安裝在垂直於電子束行進方向的平面上之安裝位 置精度係直接反映螢光體單元之位置精度。因此,冷陰極 單元之安裝位置必須具有相當高的精度。 接著,説明習知技術之高精度地安裝矽晶片等微小元 件之方法。如圖8所示般,特開平4-221865號公報爲揭示 出矽晶片等微小元件的固定方法之技術。此方法爲,在安 裝、固定複數個微小元件時,不用對各個微小元件進行位 置對準,而可自動進行位置對準的技術。其在形成於基板 81上之凸部82的上端面及微小元件83的下端面塗布具有 良好的銲材潤濕性之塗布材。接著介由銲材84而將微小元 件83設置在基板凸部82的上端面。當藉由加熱以溶融銲 材84時,基於銲材84之表面張力,微小元件83會與基板 凸部82相接合,藉此以將微小元件83銲在既定位置上。 此習知例中,藉由基板凸部82的外形大小、微小元件83 的外形大小、基板凸部82對於銲材84的表面張力之面分 布、微小元件83對於銲材84的表面張力之面分布以高精 度地決定出最終微小元件83的位置。 接著,如圖9(a)、(b)所示般,特開平1-108734號公報 揭示出可防止銲材所含之焊劑或氣體流至配線固定部之技 術,藉此以避免固著部的機械強度、電氣特性、熱安定性 之劣化。其在金屬基底91下部設置開口部92,藉由絕缘 ----------裝-------訂------1给 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐)
材93以將引線96固定在開口部92上。引線96係,藉由 銲材97以接續在印刷配線板94上。由於銲材中所含之銲 劑或氣體對於晶片95及配線98會產生不佳的影響,故形 成有堤99以防止銲劑流失至晶片95及配線%。又,習知 之如圖10(a)、(b)所示般之形成元件嵌合突起部以進行定 位之技術已廣爲人知。其爲當晶片1〇2安裝固定在圖1〇中 叉基板101上時,藉由將晶片1〇2之2個面抵接在突起部 103上以提高安裳位置的精度。 本發明所要解決之問題爲,有關使用冷陰極的電子鎗 之構造及其製造方法之以下數點。亦即,⑴必須將冷陰極 的安裝位置在士數"m之精度下固定在既定的位置;(幻在 固足凡件後,就算使用玻璃在玻璃轉移溫度以下之高熱(最 鬲550 °C)下將電子鎗封入陰極射線管時,亦不致造成安裝 位置的精度之劣化。 首先,説明基本事項之用來形成冷陰極的一般矽晶片 的尺寸A度。秒晶片係藉由切割妙晶圓等方法以得出者。 經由切割之晶片外形尺寸精度至多爲±數十"m,面對面 的平行面<精度至多爲】8〇±5度。此乃基於切割時所使用 又切割刀切在割晶圓時之產生磨耗所造成之厚度變薄、初 期之切割位置對準時所使財光學顯微鏡的精度、切割裝 置的機械精度等以決定出。 因此,如用來説明習知例之圖8及圖〗〇所示般,會產 生曰曰片的外形尺寸精度直接反映晶片安裝位置精度之缺 點。且,在圖8之習知例中,除了晶片之尺寸精度外,由 7 經濟部中央標準局員工消費合作社印製 313668 A7 B7五、發明説明(5 ) 於所使用的銲材對於基板側及晶片内面側之潤濕性形成平 均分布,故凸部與晶片之中心不易形成一致,因此會產生 安裝位置精度比晶片外形尺寸精度更差之問題點。 又,用來將冷陰極接著在陰極結構體的基板之銲材之 代表性者爲共晶合金(Eutectic Alloy),可舉金妙共晶合金 爲例,其溶融溫度爲430 °C。將電子鎗封入陰極射線管時 的溫度爲比金矽共晶合金的融點還高之550 °C。因此,在 用玻璃封止時,就算高精度地安裝著冷陰極,由於銲材之 金秒共晶合金會溶融,故會造成冷陰極的移動,如此將產 生位置精度劣化之問題。 又,其他安裝晶片之方法可舉金-金熱壓著法爲例。此 時,由於金與妙之界面會產生合金化,故在玻璃封止時的 550 °C附近安裝材會溶融,因此也會產生安裝精度劣化之 問題。 另一方面,當使用融點爲550 °C以上之高融點的共晶 合金作爲安裝材時,會產生以下之問題。亦即,(1)由於銀 銲材等含有相當多的銲劑等雜質,故不適於用來安裝半導 體晶片;(2)當溶融溫度超過600 °C以上時,基於用來安裝 之金屬基板與晶片之熱膨脹係數差,在安裝完成後之冷卻 時會造成安裝位置的移動,故會導致安裝精度之劣化;(3) 爲了加熱至600 °C以上,若不將環境氣體中的氧濃度抑制 到相當低,則元件受到傷害的可能性相當大。 本發明之目的爲提供一種基板上固接半導體晶片之方 法及其結構,以安裝精度佳地將半導體晶片固接在基板 ---------裝------訂-----1線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家揉準(CNS )八4規格(210 X 297公釐) 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明(6 ) 上。 、 本發明係提供一種基板上固接冷陰極之結構;該冷陰 極爲電子場致發射冷陰極,具有:發射部,具備多數個形 成於半導體基板上之導電性物質所構成之微小突起;及閘 極部,介由絕緣膜而形成在前述半導體基板上;其特徵在 於,使用安裝材以將前述冷陰極安裝在前述基板上,且藉 由無機接著劑以固定冷陰極的周邊,該無機接著劑之硬化 溫度較前述安裝所使用之安裝材的硬化溫度爲低。 本發明係提供一種基板上固接冷陰極之方法;該冷陰 極爲電子場致發射冷陰極,具有:發射部,具備多數個形 成於半導體基板上之導電性物質所構成之微小突起;及閘 極部,介由絕緣膜而形成在前述半導體基板上;其特徵在 於,具備:使用安裝材以將前述冷陰極安裝在前述基板的 既定位置上之步驟;使用無機接著劑以固定冷陰極的周邊 之步驟;該無機接著劑之硬化溫度較前述安裝步驟所使用 之安裝材的硬化溫度爲低。 參照圖面以説明本發明。圖1(a)係顯示本發明的第1 實施形態之陰極結構體的上視圖;圖1(b)係顯示A-A’線剖 面圖。接著説明陰極結構體的構造及製造方法,亦即安裝 順序。將陰極結構體的基板1裝設在安裝裝置上,該安裝 裝置具備用來檢知位置對準記號之CCD攝影機、及用來基 於該攝影機之輸出値以算出安裝位置之電腦,藉此以檢知 出基板1的2個位置對準記號,並算出冷陰極2的中心位 置。接著檢知出冷陰極2的位置對準圖形6,並計算出冷 ---------L .— _____I 丁_____一 泉 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) 經濟部中央標準局員工消費合作社印製 五、發明説明(7 ) 陰極2的中心位置。接著,將冷陰極2及銲材3移動並安 裝在基板1的既定位置上。特別是,在此實施形態中,鲜 材J及冷陰極2被安裝成使得發射區域7對準既定之位 置’例如基板1的中心位置。將基板i及冷陰極2保持在 此狀態下加熱至既定溫度。由於所使用之金秒共晶合金鮮 材會在430 C左右溶融,故加熱至43〇 左右。接著當金 矽共晶合金溶融後,暫時將基板1及冷陰極2保持在I狀 態下一陣子’以使其冷卻之。在冷卻後,在冷陰極的周圍 f布無機_ 4。無機接著劑可使用例如—c 製< AZ-120或東亞合成化學製之一贿ic d等。接著 將基板1及冷陰極2加熱至無機接著癌 «rm 顺《丨4的硬化溫度(150 二成加熱後,將其冷部。依據以上的順序, 冷陰極2會被安裝在_結構體的基板i h定位置上。 ^圖5所讀,電子鎗之例爲,使用稱爲套筒u之圓 柱狀的金屬體以作爲陰極結構體的基板。套筒㈣介由絕 2 44以固定在外側陰極支持體化上,藉此以形成陰極 結構體。此陰極結構體被安裝成使得其與第!树極从及其 與第2_47_對位置之精度板佳。例如精度爲+ 1〇" m以下。因此,冷陰極41之用來發射電子東⑼之稱作發 射區域42與第!柵極46及其與第2_47之間位置精度 保持於既定之高精度下。 如圖7所示般,電子鎗被封止在坡璃製之陰極射線管 74内。此時,由於玻璃的融點高到6〇〇。〇以上,故安裝有 冷陰極之陰極結構體71附近之溫度亦會上昇至55〇<;(:。在 本紙張尺度適用中國國家標隼(CNS ) A4规格(210X 297公釐) 丨裝------訂-----1—線 ' · (請先聞讀背面之注意事項再填寫本頁) A7 B7
經濟部中央標準局員工消費合作社印製 五、發明説明(8) 此實施形態中,由於使用在550 °C之溫度下仍可維持硬化 之無機接著劑固定冷陰極的外周部,故不致產生冷陰極之 位移。被封止的陰極射線管在排氣步驟時,一面在400 °C 下加熱2小時同時由排氣管排放出内部的不純氣體。完成 排氣後封止排氣管75。 圖2係顯示出本發明的第2形態。圖2(a)係冷陰極組 裝在陰極結構體的基板上之上視圖;圖2(b)係2(a)圖中 A-A’線剖面圖。此實施形態中,冷陰極2安裝在陰極結構 體的基板1上之後,將無機接著劑4斷續地塗布在至少6 個點以上,藉此以固定冷陰極。此實施形態中,由於斷續 地塗布無機接著劑,因此可分散基於矽、金及無機接著劑 間之熱膨脹係數的不同所造成之應變(Stiain),故可減輕對 於矽所造成之傷害。 圖3(a)、(b)係顯示本發明的第3實施形態之上視圖及 A-A’剖面圖。基板1形成有凹部,使用銲材3以將冷陰極2 固定在此凹部,並將無機接著劑4充填在槽8内。 在上述第1〜第3實施形態中,係針對使用金矽共晶合 金作爲銲材之情形進行説明,但除此之外亦可使用導電性 膠等。但是,在使用熱硬化性導電性膠時,必須使用硬化 溫度較無機接著劑的硬化溫度高之導電性膠。在使用熱可 塑性導電性膠時,必須使用可塑溫度較無機接著劑的硬化 溫度高者。 接合方法之其他實施形態爲,藉由在冷陰極的下部與 基板的安裝部分形成金膜,而藉由金-金之壓著以進行元件 11 (請先閲讀背面之注意事項再填寫本頁)
I 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) Α7 Β7 五、發明説明(9) 的安裝亦可。在金-金接合時,接合溫度必須爲300 °C左右 且壓力爲1〜10kg/cm2。由於接合溫度較無機接著劑之硬化 溫度高,因此可直接使用無機接著劑。 如以上所説明般,本發明中,由於在固定冷陰極之位 置時使用無機接著劑,該無機接著劑之硬化溫度較安裝冷 陰極時之硬化溫度爲低,因此具有在固定冷陰極之位置時 不致劣化元件位置的精度之效果。又,就算在將電子鎗封 止於玻璃製之陰極射線管内時之高溫步驟中,亦不致造成 冷廢極之位置移動。 【圖面之簡單説明】 圖1(a)、(b)係本發明的第1實施形態之上祝圖及A-A’ 線剖面圖。 * 圖2(a)、(b)係本發明的第2實施形態之上祝圖及A-A’ 線剖面圖。 圖3(a)、(b)係本發明的第3實施形態之上視圖及A-A’ 線剖面圖。 圖4係顯示冷陰極的構造之剖面圖。 圖5係使用冷陰極之電子鎗的剖面圖。 經濟部中央標準扃員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 圖6(a)、(b)係顯示習知的陰極結構體之斜視圖與A-A’ 線剖面圖。 圖7係顯示使用冷陰極之陰極射線管的剖面圖。 圖8係顯示習知的冷陰極微小元件的固定構造之剖面 圖。 圖9(a)、(b)係顯示習知的冷陰極晶片的固定構造之平 12 本紙張尺度適用中國國家標準贫..CNS ) Α4規格(210X297公釐) 318668
A7 B7 五、發明説明(10) 面.圖及剖面圖。 · 圖10(a)、(b)係顯示習知的冷陰極晶片的固定構造之 平面圖及剖面圖。 【符號説明】 1〜基板,2〜冷陰極,3〜銲材,4〜無機接著劑,5、 6〜對準記號,7〜發射區域,8〜槽。 ----------—裝-- - f (請先閱讀背面之注意事項再填寫本頁) 訂- 線 經濟部中央標準局員工消費合作社印製 13 本紙張尺度逍用中國國家標準(CNS ) Λ4規格(210X297公釐)
Claims (1)
- 3ΐ3ββ8 Α8 Β8 C8 D8 六、申請專利範圍 1. 一種基板上固接半導體晶片之’方法,具備下列步 驟: 使用安裝材以將前述半導體晶片安裝在前述基板的既 定位置上之安裝步驟; 使用無機接著劑以固定前述半導體晶片的周邊之步 驟;該無機接著劑之硬化溫度較前述安裝步驟所使用之安 裝材的硬化溫度爲低。 2. 如申請專利範圍第1項所述之基板上固接半導體晶 片之方法,其中,使用該無機接著材以將該半導體晶片的 周邊之至少6點固接在該基板上。 3. 如申請專利範圍第1項所述之基板上固接半導體晶 片之方法,其中,使用該安裝材以將該半導體晶片安裝在 該基板的凹部上。 4. 如申請專利範圍第1項所述之基板上固接半導體晶 片之方法,其中,該安裝材爲金矽共晶合金。 5. 如申請專利範圍第1項所述之基板上固接半導體晶 片之方法,其中,該安裝材爲金-金接合材,且在該半導體 晶片之下部及該基板之安裝部分形成有金膜。 6. 如申請專利範圍第1項所述之基板上固接半導體晶 片之方法,其中,該安裝材爲導電性膠。 7. 如申請專利範圍第1項所述之基板上固接半導體晶 片之方法,其中,該安裝材爲熱硬化性導電性膠,其硬化 溫度高於無機接著材之硬化溫度;或該安裝材爲熱可塑性 導電性膠,其可塑溫度高於無機接著材之硬化溫度。 14 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐)I . 裝 - 訂 -線 1 - (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印装 A8 B8 C8 D8 六、申請專利範圍 8. 如申請專利範圍第1項所述之基板上固接半導體晶 片之方法,其中,該半導體晶片爲電子場致發射冷陰極。 9. 一種基板上固接冷陰極之方法;該冷陰極爲電子場 致發射冷陰極,具有:發射部,具備多數個形成於半導體 基板上之導電性物質所構成之微小突起;及閘極部,介由 絕緣膜而形成在前述半導體基板上.;其特徵在於,具備: 使用安裝材以將前述冷陰極安裝在前述基板的既定位置上 之安裝步驟;使用無機接著劑以固定冷陰極的周邊之步 驟;該無機接著劑之硬化溫度較前述安裝步驟所使用之安 裝材的硬化溫度爲低。 10. —種基板上固接半導體晶片之結構,使用安裝材以 將前述半導體晶片安裝在前述基板上,且藉由無機接著劑 以固定半導體晶片的周邊,該無機接著劑之硬化溫度較前 述安裝所使用之安裝材的硬化溫度爲低。 11. 一種基板上固接冷陰極之結構;該冷陰極爲電子場 致發射冷陰極,具有:發射部,具備多數個形成於半導體 基板上之導電性物質所構成之微小突起;及閘極部,介由 絕緣膜而形成在前述半導體基板上;其特徵在於,使用安 裝材以將前述冷陰極安裝在前述基板上,且藉由無機接著 劑以固定冷陰極的周邊,該無機接著劑之硬化溫度較前述 安裝所使用之安裝材的硬化溫度爲低。 本紙張尺度適用中國國家標準(CNS ) Μ規格(210X297公釐)(請先聞讀背面之注意事項再填寫本頁) -裝· 經濟部中央標準局員工消費合作社印製
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DE102004055511B3 (de) * | 2004-11-17 | 2006-02-09 | Danfoss Silicon Power Gmbh | Verfahren zum Herstellen eines Leistungshalbleitermoduls |
CN105480936B (zh) * | 2014-09-17 | 2017-05-10 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制作方法和电子装置 |
US11387373B2 (en) * | 2019-07-29 | 2022-07-12 | Nxp Usa, Inc. | Low drain-source on resistance semiconductor component and method of fabrication |
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NL8602330A (nl) * | 1986-09-15 | 1988-04-05 | Philips Nv | Werkwijze voor het contacteren van halfgeleiderkathoden, alsmede voor het vervaardigen van een electronenbuis voorzien van een dergelijke kathode. |
JPH01108734A (ja) * | 1987-10-22 | 1989-04-26 | Toshiba Components Co Ltd | 半導体装置 |
US5187123A (en) * | 1988-04-30 | 1993-02-16 | Matsushita Electric Industrial Co., Ltd. | Method for bonding a semiconductor device to a lead frame die pad using plural adhesive spots |
US5175060A (en) * | 1989-07-01 | 1992-12-29 | Ibiden Co., Ltd. | Leadframe semiconductor-mounting substrate having a roughened adhesive conductor circuit substrate and method of producing the same |
US5194695A (en) * | 1990-11-02 | 1993-03-16 | Ak Technology, Inc. | Thermoplastic semiconductor package |
JPH04221865A (ja) * | 1990-12-20 | 1992-08-12 | Fujikura Ltd | 微小素子の固定方法 |
US5211707A (en) * | 1991-07-11 | 1993-05-18 | Gte Laboratories Incorporated | Semiconductor metal composite field emission cathodes |
JP3018050B2 (ja) * | 1991-11-15 | 2000-03-13 | ローム株式会社 | 半導体装置およびその製造方法 |
US5318918A (en) * | 1991-12-31 | 1994-06-07 | Texas Instruments Incorporated | Method of making an array of electron emitters |
US5229331A (en) * | 1992-02-14 | 1993-07-20 | Micron Technology, Inc. | Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology |
JPH0721903A (ja) * | 1993-07-01 | 1995-01-24 | Nec Corp | 電界放出型陰極を用いた陰極線管用電子銃構体 |
JPH07161304A (ja) * | 1993-12-13 | 1995-06-23 | Nec Kansai Ltd | 陰極構体および陰極構体用電界放出型陰極 |
US5585301A (en) * | 1995-07-14 | 1996-12-17 | Micron Display Technology, Inc. | Method for forming high resistance resistors for limiting cathode current in field emission displays |
-
1996
- 1996-01-30 JP JP8014059A patent/JP2856135B2/ja not_active Expired - Lifetime
-
1997
- 1997-01-29 KR KR1019970002592A patent/KR100240305B1/ko not_active IP Right Cessation
- 1997-01-29 US US08/790,469 patent/US5923956A/en not_active Expired - Fee Related
- 1997-02-04 TW TW086101352A patent/TW313668B/zh active
Also Published As
Publication number | Publication date |
---|---|
KR970060459A (ko) | 1997-08-12 |
US5923956A (en) | 1999-07-13 |
JP2856135B2 (ja) | 1999-02-10 |
KR100240305B1 (ko) | 2000-01-15 |
JPH09213200A (ja) | 1997-08-15 |
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