TW223704B - Method for integrated circuit fabrication including linewidth control during etching - Google Patents
Method for integrated circuit fabrication including linewidth control during etchingInfo
- Publication number
- TW223704B TW223704B TW082110292A TW82110292A TW223704B TW 223704 B TW223704 B TW 223704B TW 082110292 A TW082110292 A TW 082110292A TW 82110292 A TW82110292 A TW 82110292A TW 223704 B TW223704 B TW 223704B
- Authority
- TW
- Taiwan
- Prior art keywords
- integrated circuit
- control during
- during etching
- circuit fabrication
- fabrication including
- Prior art date
Links
- 238000005530 etching Methods 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 abstract 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 abstract 1
- 239000001301 oxygen Substances 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- ing And Chemical Polishing (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/998,503 US5326727A (en) | 1992-12-30 | 1992-12-30 | Method for integrated circuit fabrication including linewidth control during etching |
Publications (1)
Publication Number | Publication Date |
---|---|
TW223704B true TW223704B (en) | 1994-05-11 |
Family
ID=25545297
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW082110292A TW223704B (en) | 1992-12-30 | 1993-12-06 | Method for integrated circuit fabrication including linewidth control during etching |
Country Status (4)
Country | Link |
---|---|
US (1) | US5326727A (zh) |
EP (1) | EP0605123A3 (zh) |
JP (1) | JPH0778758A (zh) |
TW (1) | TW223704B (zh) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5928527A (en) * | 1996-04-15 | 1999-07-27 | The Boeing Company | Surface modification using an atmospheric pressure glow discharge plasma source |
US5633210A (en) * | 1996-04-29 | 1997-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming damage free patterned layers adjoining the edges of high step height apertures |
US5804088A (en) * | 1996-07-12 | 1998-09-08 | Texas Instruments Incorporated | Intermediate layer lithography |
TW363220B (en) * | 1996-07-15 | 1999-07-01 | Applied Materials Inc | Etching organic antireflective coating from a substrate |
US5837428A (en) * | 1996-08-22 | 1998-11-17 | Taiwan Semiconductor Manufacturing Compnay Ltd. | Etching method for extending i-line photolithography to 0.25 micron linewidth |
EP0859400A3 (en) * | 1996-12-23 | 1998-09-02 | Texas Instruments Incorporated | Improvements in or relating to integrated circuits |
US5962195A (en) * | 1997-09-10 | 1999-10-05 | Vanguard International Semiconductor Corporation | Method for controlling linewidth by etching bottom anti-reflective coating |
JP3003657B2 (ja) * | 1997-12-24 | 2000-01-31 | 日本電気株式会社 | 半導体装置の製造方法 |
JP3253604B2 (ja) * | 1998-11-13 | 2002-02-04 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP2000208767A (ja) | 1998-11-13 | 2000-07-28 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2000208488A (ja) | 1999-01-12 | 2000-07-28 | Kawasaki Steel Corp | エッチング方法 |
US6297166B1 (en) | 1999-04-22 | 2001-10-02 | International Business Machines Corporation | Method for modifying nested to isolated offsets |
JP2001156045A (ja) | 1999-11-26 | 2001-06-08 | Kawasaki Steel Corp | 半導体装置の製造方法および製造装置 |
US6779159B2 (en) | 2001-06-08 | 2004-08-17 | Sumitomo Mitsubishi Silicon Corporation | Defect inspection method and defect inspection apparatus |
DE10241990B4 (de) * | 2002-09-11 | 2006-11-09 | Infineon Technologies Ag | Verfahren zur Strukturierung von Schichten auf Halbleiterbauelementen |
US8377795B2 (en) * | 2009-02-12 | 2013-02-19 | International Business Machines Corporation | Cut first methodology for double exposure double etch integration |
JP6746518B2 (ja) * | 2017-03-10 | 2020-08-26 | 株式会社Adeka | エッチング液組成物及びエッチング方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4244799A (en) * | 1978-09-11 | 1981-01-13 | Bell Telephone Laboratories, Incorporated | Fabrication of integrated circuits utilizing thick high-resolution patterns |
US4521274A (en) * | 1984-05-24 | 1985-06-04 | At&T Bell Laboratories | Bilevel resist |
JPS60262150A (ja) * | 1984-06-11 | 1985-12-25 | Nippon Telegr & Teleph Corp <Ntt> | 三層レジスト用中間層材料及びそれを用いた三層レジストパタン形成方法 |
US4657629A (en) * | 1986-03-27 | 1987-04-14 | Harris Corporation | Bilevel resist process |
US4770739A (en) * | 1987-02-03 | 1988-09-13 | Texas Instruments Incorporated | Bilayer photoresist process |
EP0285797A3 (de) * | 1987-03-11 | 1989-01-04 | Siemens Aktiengesellschaft | Verfahren zur Erzeugung von Resiststrukturen |
US5126231A (en) * | 1990-02-26 | 1992-06-30 | Applied Materials, Inc. | Process for multi-layer photoresist etching with minimal feature undercut and unchanging photoresist load during etch |
JPH0574743A (ja) * | 1990-12-20 | 1993-03-26 | Fujitsu Ltd | 多層レジストのパターニング方法 |
EP0525942A2 (en) * | 1991-05-31 | 1993-02-03 | AT&T Corp. | Integrated circuit fabrication process using a bilayer resist |
-
1992
- 1992-12-30 US US07/998,503 patent/US5326727A/en not_active Expired - Lifetime
-
1993
- 1993-12-06 TW TW082110292A patent/TW223704B/zh not_active IP Right Cessation
- 1993-12-08 EP EP93309855A patent/EP0605123A3/en not_active Withdrawn
- 1993-12-24 JP JP5325583A patent/JPH0778758A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
EP0605123A2 (en) | 1994-07-06 |
EP0605123A3 (en) | 1995-10-25 |
US5326727A (en) | 1994-07-05 |
JPH0778758A (ja) | 1995-03-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |