TW202247360A - 電子機器 - Google Patents
電子機器 Download PDFInfo
- Publication number
- TW202247360A TW202247360A TW111105036A TW111105036A TW202247360A TW 202247360 A TW202247360 A TW 202247360A TW 111105036 A TW111105036 A TW 111105036A TW 111105036 A TW111105036 A TW 111105036A TW 202247360 A TW202247360 A TW 202247360A
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- Prior art keywords
- metal layer
- semiconductor substrate
- porous metal
- chip
- electronic device
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 298
- 239000002184 metal Substances 0.000 claims abstract description 298
- 239000004065 semiconductor Substances 0.000 claims abstract description 148
- 239000000758 substrate Substances 0.000 claims abstract description 136
- 239000010931 gold Substances 0.000 claims description 47
- 239000000463 material Substances 0.000 claims description 31
- 239000002245 particle Substances 0.000 claims description 30
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 16
- 239000002923 metal particle Substances 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 229910052709 silver Inorganic materials 0.000 claims description 11
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 229910052697 platinum Inorganic materials 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 53
- 229920002120 photoresistant polymer Polymers 0.000 description 28
- 238000000034 method Methods 0.000 description 11
- 239000000203 mixture Substances 0.000 description 10
- 239000011295 pitch Substances 0.000 description 10
- 239000011347 resin Substances 0.000 description 9
- 229920005989 resin Polymers 0.000 description 9
- 238000007789 sealing Methods 0.000 description 9
- 230000002093 peripheral effect Effects 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000002844 melting Methods 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013590 bulk material Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- -1 gold-aluminum Chemical compound 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000005476 size effect Effects 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 238000001035 drying Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- QUCZBHXJAUTYHE-UHFFFAOYSA-N gold Chemical compound [Au].[Au] QUCZBHXJAUTYHE-UHFFFAOYSA-N 0.000 description 1
- PQTCMBYFWMFIGM-UHFFFAOYSA-N gold silver Chemical compound [Ag].[Au] PQTCMBYFWMFIGM-UHFFFAOYSA-N 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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Abstract
本揭示之目的在於提供一種可提高氣密性之電子機器。
本揭示之電子機器具備半導體基板、晶片、凸塊、及側壁部。凸塊將設置於半導體基板及晶片之對向之主面之複數個連接焊墊彼此連接。側壁部包含以環狀包圍設置有複數個上述凸塊之區域之多孔質金屬層,連接半導體基板與晶片。晶片與半導體基板,熱膨脹率相差0.1 ppm/℃以上。晶片係半導體雷射,半導體基板具有驅動半導體雷射之驅動電路。
Description
本揭示係關於一種電子機器。
將電子電路元件覆晶連接於基板上之電子機器為防止於自半導體晶圓將各電子機器單片化時使用之切削水之入侵,例如藉由樹脂密封。
但,於藉由樹脂密封電子機器之情形時,存在由樹脂引起之電極之污染、因將樹脂注入至每個電子機器引起之作業時間之長期化、及因作業時間之長期化引起廢棄之樹脂量之增加等之問題。
因此,存在將電子電路元件之電極與基板之電極之間由金-錫接合、金-銀接合、金-鋁接合或金-金接合連接,將電子電路元件之周緣部、與對向之基板以與電極間連接相同之連接方法接合密封之電子機器(例如,參照專利文獻1)。一種電子器件,其特徵在於將上述電子電路元件之晶片電極與上述基板之內部電極之間以金-錫(Au-Sn)接合、金-銀(Au-Ag)接合、金-鋁(Au-AI)接合或金-金(Au-Au)接合連接,且將上述電子電路元件之周緣部或需要密封之部分、與其所對向之上述基板以與上述相同之連接方法接合密封。
[先前技術文獻]
[專利文獻]
[專利文獻1]日本專利特開2004-214469號公報
[發明所欲解決之問題]
然而,於上述之先前技術中,於電子電路元件或基板存在厚度之不均或翹曲之情形時,有時於密封部分之金屬產生間隙,使電子機器之氣密性降低。因此,於本揭示中,提案一種可提高氣密性之電子機器。
[解決問題之技術手段]
根據本揭示,提供一種電子機器。電子機器具備半導體基板、晶片、凸塊、及側壁部。凸塊將設置於上述半導體基板及上述晶片之對向之主面之複數個連接焊墊彼此連接。側壁部包含以環狀包圍設置複數個上述凸塊之區域之多孔質金屬層,連接上述半導體基板與上述晶片。
以下,基於圖式對本揭示之實施形態進行詳細說明。另,於以下之各實施形態中,藉由對相同之部位標註相同之符號及相同之陰影線,省略重複之說明。
[1.電子機器之剖面構造]
圖1係本揭示之實施形態之電子機器之剖面說明圖。圖2係圖1所示之A-A線之剖面說明圖。如圖1所示,本揭示之電子機器1具備半導體基板2、晶片3、及將設置於半導體基板2及晶片3之對向之主面之連接焊墊21、31彼此連接之凸塊4。
再者,如圖1及圖2所示,電子機器1具備:側壁部,其包含以環狀包圍設置有複數個凸塊4之區域之多孔質金屬層51,連接半導體基板2與晶片3。又,電子機器1於側壁部5與半導體基板2之間亦設置電極墊21。設置於側壁部5與半導體基板2之間之連接焊墊21未與半導體基板2內部之電路連接。
晶片3係例如半導體雷射,於GaAs(砷化鎵)之基材之一側之主面具備複數個連接焊墊31。又,晶片3於基材之內部具備半導體雷射之發光部等。發光部具備出射雷射光之2維配置之複數個發光元件。發光元件於晶片3內與連接焊墊31連接。
另,晶片3具備之電子零件亦可為半導體雷射之發光部以外之任意之電子零件。又,晶片3之基材亦可係例如InP(磷化銦)等之半絕緣性基材。
半導體基板2係例如Si(矽)基板,於內部具備驅動半導體雷射之驅動電路。半導體基板2於一側之主面具備複數個連接焊墊21。連接焊墊21於半導體基板2之內部與驅動電路連接。另,半導體基板2具備之電子電路亦可為半導體雷射之驅動電路以外之任意之電子電路。
電子機器1於半導體基板2覆晶安裝晶片3,藉由凸塊4電性連接半導體基板2內之驅動電路、與半導體雷射即晶片3。又,電子機器1設置連接焊墊21、31及凸塊4之空間由側壁部5密封密閉。
此處,例如,於具備半導體雷射之驅動電路之半導體基板2上覆晶安裝具備半導體雷射之晶片3且製造電子機器之情形時,於一般之製造方法中,首先於矽晶圓形成複數個驅動電路。
其後,於各驅動電路上經由塊狀之金屬製之凸塊積層晶片3,藉由凸塊將設置於驅動電路及晶片3之對向之主面之連接焊墊21、31彼此連接。且,對每個電子機器切割Si晶圓並單片化。
於將Si晶圓按每個電子機器單片化之步驟中,一面對Si晶圓供給切削水一面進行切割。此時,若切削水入侵至半導體基板2與晶片3之間,則對電子機器造成壞影響。因此,一般而言,於將各電子機器樹脂密封之後,將Si晶圓按每個電子機器單片化。
但,於藉由樹脂密封電子機器之情形時,存在因樹脂引起之電極之污染、因將樹脂注入至每個電子機器引起之作業時間之長期化、及因作業時間之長期化導致超過使用期限而廢棄之樹脂量之增加等之問題。
因此,存在一種藉由凸塊將設置於半導體基板2及晶片3之對向之主面之連接焊墊21、31彼此連接,以與連接焊墊21、31間之連接相同之連接方法將必須密封之設置連接焊墊21、31及凸塊之區域接合密封的技術。
又,於一般之覆晶安裝中,藉由一面壓接設置於半導體基板2或晶片3之對向之主面之塊狀之Au(金)、Cu(銅)、及焊料等之金屬製之凸塊一面加熱,於半導體基板2安裝晶片3。
然而,於半導體基板2與晶片3之熱膨脹率例如相差0.1 ppm/℃以上之情形時,若使用塊狀之Au、Cu、及焊料等作為凸塊之材料,則產生如以下般之問題。
例如,於使用塊狀之Au作為凸塊之材料之情形時,為藉由凸塊穩定連接熱膨脹率不同之半導體基板2與晶片3,必須加熱至300℃以上之高溫,且於半導體基板2與晶片3之間施加100 MPa以上之高壓。
又,於使用塊狀之Cu作為塊狀之材料之情形時,必須加熱380℃以上。如此,於使用塊狀之Au或Cu作為塊狀之材料之情形時,必須以高溫高壓進行凸塊之連接,有時該高溫高壓對晶片3造成損傷,有時使電子機器之可靠性降低。
另一方面,於使用焊料作為凸塊之材料之情形時,雖與Au或Cu相比可以低溫低壓進行凸塊之連接,但焊料耐熱性及連接強度劣於Au或Cu。因此,焊料製之凸塊例如於因搭載於晶片3之半導體雷射等之電子零件之發熱而引起晶片3熱膨脹時,有因半導體基板2與晶片3之熱膨脹率之不同而產生開放故障,使電子機器之可靠性降低之虞。
又,如上所述,本揭示之半導體基板2係Si基板,熱膨脹率係5.7 ppm/℃。另一方面,本揭示之晶片3之基材係GaAs,熱膨脹率係2.6 ppm/℃。
如此,電子機器1之半導體基板2與晶片3之熱膨脹率之差遠大於0.1 ppm/℃。因此,電子機器1於凸塊之材料為塊狀之Au、Cu、或焊料之情形時,有產生如上述般之問題,且使可靠性降低之虞。
又,於將半導體基板2與晶片3之間之必須密封之區域之周緣部,藉由表面被鍍敷處理之塊狀之金屬包圍而接合密封之情形時,若半導體基板2與晶片3之熱膨脹率例如相差0.1 ppm/℃以上,則於密封部分產生龜裂。藉此,電子機器氣密性降低。
再者,若半導體基板2或晶片3存在厚度之不均或翹曲,則於積層半導體基板2與晶片3時,於密封部分中,僅可以鍍敷膜之凸面之突出與半導體基板2及晶片3接合。
其結果,電子機器因於密封部分散佈間隙,故氣密性降低。又,若為防止密封部分中之間隙之產生,而升溫升壓將半導體基板2與晶片3接合,則電子機器中,相鄰之細微之凸塊彼此有產生短路故障之虞。
因此,電子機器1之凸塊4例如包含Au之多孔質金屬層41。多孔質金屬層41包含粒子徑為0.005 μm~1.0 μm且純度為99.9重量%以上之Au粒子。另,多孔質金屬層41之成分亦可為例如純度99.9重量%以上之Cu、Ag(銀)、或Pt(鉑)。
包含粒子徑為0.005 μm~1.0 μm之金屬粒子之多孔質金屬層41藉由粒子徑之尺寸效果,可以低於塊狀金屬之熔點之溫度接合金屬。例如,多孔質金屬層41可以於成分為Au之情形時100℃左右、為Ag之情形時250℃左右、為Cu之情形時150℃左右之溫度連接半導體基板2與晶片3。藉此,因電子機器1可減少熱引起之晶片3之損傷,故可提高可靠性。
又,因多孔質金屬層41具有彈性,故例如即使因半導體雷射之發熱,使晶片3以與半導體基板2不同之熱膨脹率膨脹,亦彈性變化,故可抑制開放故障之產生。藉此,電子機器1例如與使用焊料製之凸塊之情形相比可提高可靠性。
該電子機器1藉由將晶片3積層於於上表面設置凸塊4之半導體基板2,不使凸塊4之多孔質金屬層41熔融地與連接焊墊31連接,將晶片3覆晶安裝於半導體基板2而製造。
又,電子機器1亦可藉由將於下表面設置有包含多孔質金屬層41之凸塊4之晶片3積層於半導體基板2,不使凸塊4之多孔質金屬層41熔融地與連接焊墊21連接,將晶片3覆晶安裝於半導體基板2而製造。另,包含多孔質金屬層41之凸塊4亦可設置於積層前之半導體基板2及晶片3之兩者。
於凸塊4設置於半導體基板2側之情形時,於多孔質金屬層41與半導體基板2側之連接焊墊21之間具備金屬膜42。又,於凸塊4設置於晶片3側之情形時,於多孔質金屬層41與晶片3側之連接焊墊31之間具備金屬膜42。另,金屬膜42亦可設置於多孔質金屬層41與半導體基板2側之連接焊墊21之間、及多孔質金屬層41與晶片3側之連接焊墊31之間之中至少任一者。
於本揭示中,藉由使金屬膜42相對於凸塊4中之與半導體基板2之主面正交之方向之厚度之膜厚比例未達10%,可進行使凸塊4之間距設為20 μm以下之精細間距化。關於該精細間距化,與凸塊4之形成步驟對照予以後述。
再者,凸塊4於多孔質金屬層41之側面(側周面)亦具備金屬膜42。金屬膜42之材料期望與多孔質金屬層41相同。例如,於多孔質金屬層41之材料為Au之情形時,期望金屬膜42為Au膜。
藉此,凸塊4因多孔質金屬層41之側面藉由金屬膜42塗佈,故可防止多孔質金屬層41之粒子崩壞而飛散。因此,凸塊4可防止因多孔質金屬層41之粒子之飛散而導致相鄰之凸塊4彼此短路。
又,於多孔質金屬層41之側面未設置金屬膜42之情形時,於表面較軟之多孔質金屬層41之側面產生表面粗糙,於凸塊4間於形狀產生不均。
與此相對,因凸塊4於多孔質金屬層41之側面設置硬於多孔質金屬層41之金屬膜42,故抑制凸塊4間之形狀之不均,全部成為均一之形狀。且,因凸塊4之側面藉由較硬之金屬膜42塗佈,故可進一步微細化,可進一步精細間距化。
又,凸塊4於晶片3相對於半導體基板2覆晶安裝之情形時,雖於厚度方向略微壓壞,但防止多孔質金屬層41之粒子洩漏至金屬膜42之外部。其結果,凸塊4因金屬膜42之內部之多孔質金屬層41之粒子密度增大,故可減少連接電阻。
又,電子機器1之側壁部5具有與凸塊4同樣之構造。具體而言,側壁部5包含Au之多孔質金屬層51。多孔質金屬層51包含粒子徑為0.005 μm~1.0 μm且純度為99.9重量%以上之Au粒子。另,多孔質金屬層51之成分亦可為例如純度99.9重量%以上之Cu、Ag(銀)、或Pt(鉑)。
多孔質金屬層51藉由如上所述粒子徑之尺寸效果,可以低於塊狀之金屬之熔點之溫度接合金屬。藉此,因電子機器1可減少因形成多孔質金屬層51時之熱引起之晶片3之損傷,故可提高可靠性。
又,因多孔質金屬層51具有彈性,故例如即使因半導體雷射之發熱,使晶片3以與半導體基板2不同之熱膨脹率膨脹,亦彈性變化,故可抑制於側壁部5產生龜裂。藉此,電子機器1可提高必須密封之設置連接焊墊21、31及凸塊4之區域之氣密性。
又,因多孔質金屬層51彈性變化,故例如即使於半導體基板2或晶片3存在厚度之不均或翹曲之情形時,一於接合半導體基板2與晶片3時,追隨半導體基板2或晶片3之表面形狀變化。
藉此,因電子機器1可抑制於側壁部5與半導體基板2之連接部分、及側壁部5與晶片3之連接部分產生間隙,故可提高氣密性。
又,側壁部5如圖2所示以環狀包圍必須密封之設置連接焊墊21、31及凸塊4之區域之方式設置。藉此,電子機器1於半導體基板2或晶片3熱膨脹之情形時,可緩和對設置於角部之凸塊4施加之機械性應力。
具體而言,於半導體基板2或晶片3熱膨脹之情形時,自半導體基板2或晶片3之主面中央越朝向周緣部,因溫度變化引起之膨脹量及收縮量越大。因此,若無側壁部5,則對設置於角部之凸塊4施加機械性應力。
與此相對,電子機器1因半導體基板2及晶片3之周緣部藉由側壁部5密封,故可藉由側壁部5抑制因溫度變化引起之半導體基板2及晶片3之周緣部之膨脹及收縮。藉此,電子機器1可緩和對設置於角部之凸塊4施加之機械性應力。
於側壁部5設置於半導體基板2側之情形時,於多孔質金屬層51與半導體基板2之主面上之連接焊墊21之間具備金屬膜52。又,於側壁部5設置於晶片3側之情形時,於多孔質金屬層51與晶片3之主面上之連接焊墊之間具備金屬膜52。另,金屬膜52亦可設置於多孔質金屬層51與半導體基板2之主面上之連接焊墊21之間、及多孔質金屬層51與晶片3之主面上之連接焊墊之間至少任一者。
於本揭示中,藉由使金屬膜52相對於側壁部5之與半導體基板2之主面正交之方向之厚度之膜厚比例未達10%,而可於同時形成側壁部5及凸塊4之步驟中,進行將凸塊4之間距設為20 μm以下之精細間距化。
再者,側壁部5於多孔質金屬層51之側面(側周面)亦具備金屬膜52。金屬膜52之材料期望與多孔質金屬層51相同。例如,於多孔質金屬層51之材料係Au之情形時,期望金屬膜52為Au膜。
藉此,側壁部5因多孔質金屬層51之側面由金屬膜52塗佈,故可防止多孔質金屬層51之粒子崩壞而飛散。因此,側壁部5可防止因多孔質金屬層51之粒子之飛散而導致相鄰之凸塊4彼此短路。
又,於多孔質金屬層51之側面未設置金屬膜52之情形時,於表面較軟之多孔質金屬層51之側面產生表面粗糙,於側壁部5之側面形狀產生不均。
與此相對,因側壁部5於多孔質金屬層51之側面設置有硬於多孔質金屬層51之金屬膜52,故抑制側面形狀之不均,側面整體成為均一之表面形狀。且,因側壁部5之側面藉由較硬之金屬膜52塗佈,故可進一步微細化。
該電子機器1藉由於上表面設置凸塊4之半導體基板2,積層未設置凸塊4a(參照圖10)之晶片3,不使凸塊4之多孔質金屬層41熔融地與連接焊墊31連接,並將晶片3覆晶安裝於半導體基板2而製造。
又,電子機器1亦可藉由將於下表面設置有包含多孔質金屬層41之凸塊4a(參照圖10)之晶片3積層於未設置有凸塊4之半導體基板2,不使凸塊4a之多孔質金屬層41熔融地與連接焊墊21連接,將晶片3覆晶安裝於半導體基板2而製造。另,包含多孔質金屬層41之凸塊4、4a亦可設置於積層前之半導體基板2及晶片3之兩者。
[2.凸塊及側壁部之形成步驟]
接著,參照圖3~圖10,對本揭示之凸塊及側壁部之形成步驟進行說明。圖3~圖6係顯示本揭示之於半導體基板形成凸塊及側壁部之步驟之說明圖。圖7~圖10係顯示本揭示之於晶片形成凸塊及側壁部之步驟之說明圖。
如圖3所示,於半導體基板2形成凸塊4及側壁部5之情形時,首先,於半導體基板2上之設置於後續形成凸塊4之位置之連接焊墊21之上表面形成金屬膜22。此時,同時於設置於後續形成側壁部5之位置之連接焊墊21之上表面,即於半導體基板2之主面中設置於環狀包圍後續形成凸塊4之區域之位置之連接焊墊21之上表面,亦形成金屬膜32。作為金屬膜22之材料,選擇與後續積層之金屬膜64(參照圖4)相同成分之金屬。另,此處,形成Au之金屬膜22。
其後,於半導體基板2之設置有連接焊墊21及金屬膜22之側之表面形成光阻層61。其後,藉由光微影技術,於光阻層61中之形成凸塊4之位置形成貫通孔62,使金屬膜22之表面露出。同時,於形成側壁部5之位置形成溝槽63,使金屬膜22之表面露出。
此時,以相鄰設置之貫通孔62之中心間之間隔為20 μm(20 μm間距)之方式,形成貫通孔62。該貫通孔62於後續步驟中填充包含作為多孔質金屬層41之材料之金屬粒子之膏50,但由於為20 μm間距之微細構造,故若於該狀態下直接填充膏50,則有微細構造受損傷而崩壞之虞。
因此,如圖4所示,於光阻層61之上表面、貫通孔62之側面、溝槽63之側面、及金屬膜22之上表面,例如藉由濺鍍形成金屬膜64。作為金屬膜64之材料,選擇與後續填充至貫通孔62之膏50所包含之金屬粒子相同成分之金屬。另,此處,形成Au之金屬膜64。
藉此,因光阻層61藉由表面由金屬膜64塗佈而硬化,故於將包含金屬粒子之膏50填充至貫通孔62之情形時,可防止微細之構造崩壞。
又,若此處形成之金屬膜64之膜厚過厚,則貫通孔62之開口變窄,難以將包含金屬粒子之膏50填充至貫通孔62。因此,此處,形成金屬膜64相對於貫通孔62之深度D1,換言之,後續形成之凸塊4中之與半導體基板2之主面正交之方向之厚度(凸塊4之高度D1)之膜厚d1之比例未達10%之較薄之(例如厚度未達1 μm之)金屬膜64。
例如,於形成以20 μm間距排列之高度10 μm之凸塊4之情形時,將金屬膜64之膜厚設為0.2 μm。藉此,即使形成金屬膜64,亦可防止貫通孔62之開口變窄,因而可於之後之步驟將包含金屬粒子之膏50充分填充至貫通孔62。
其結果,金屬膜64相對於溝槽63之深度D2,換言之,後續形成之側壁部5之與半導體基板2之主面正交之方向之厚度(側壁部5之高度D2)之膜厚d1之比例未達10%。
接著,如圖5所示,於形成於光阻層61之貫通孔62及溝槽63,例如填充包含純度為99.9重量%以上且粒子徑為0.005 μm~1.0 μm之Au粒子之膏50。作為將膏50填充至貫通孔62及溝槽63之方法,例如可使用絲網印刷、以刮刀擴開滴下之膏50之方法等任意之方法。
其後,使膏50乾燥及燒結後,藉由使用剝離液等之剝蝕,剝離光阻層61。藉此,如圖6所示,於連接焊墊21之表面依序積層Au之金屬膜22、Au之金屬膜42、及包含粒子徑為0.005 μm~1.0 μm之Au粒子之多孔質金屬層41,完成於多孔質金屬層41之側面亦形成Au之金屬膜42之凸塊4。
同時,以包圍形成凸塊4之區域之方式,依序積層Au之金屬膜22、Au之金屬膜52、及包含粒子徑為0.005 μm~1.0 μm之Au粒子之多孔質金屬層51,完成於多孔質金屬層51之側面亦形成Au之金屬膜52之側壁部5。
如此,凸塊4於連接焊墊21上之金屬膜22與多孔質金屬層41之間,具備膜厚相對於凸塊4之高度D1之比例未達10%之金屬膜42。再者,凸塊4於多孔質金屬層41之側面亦設置有金屬膜42。
又,側壁部5於連接焊墊21上之金屬膜22與多孔質金屬層51之間,具備膜厚相對於側壁部5之高度D2之比例未達10%之金屬膜52。再者,側壁部5於多孔質金屬層51之側面亦設置金屬膜52。
該金屬膜42、52係為防止於光阻層61圖案化之凸塊4及側壁部5之微細構造之崩壞,而形成於光阻層61之上表面、光阻層61所形成之貫通孔62及溝槽63之側面、及金屬膜22之表面者。藉此,凸塊4可進行將間距設為20 μm以下之精細間距化。
又,因金屬膜22藉由濺鍍形成於連接焊墊21之表面,故即使連接焊墊21為與金屬膜22不同成分之金屬,亦與連接焊墊21牢固接合。
又,金屬膜42、52亦可由與多孔質金屬層41、51不同成分之金屬形成,但於由相同成分之Au形成之情形時,多孔質金屬層41、51較設置於成分不同之其他金屬膜上之情形時,以更牢固之接合力與金屬膜42、52接合。另,多孔質金屬層41、51係Au以外之成分(例如,Cu、Ag(銀)或Pt(鉑))之情形時,金屬膜42、52亦可使用與多孔質金屬層41、51相同之金屬(例如,Cu、Ag(銀)或Pt(鉑))。
接著,對於晶片3形成圖10所示之凸塊4a及側壁部5a之步驟進行說明。如圖7所示,於晶片3形成凸塊4a及側壁部5之情形時,首先,於設置於晶片3上之後續形成凸塊4a之位置之連接焊墊31之上表面形成金屬膜32。此時,同時於設置於後續形成側壁部5a之位置之連接焊墊31之上表面,即於晶片3之主面中設置於環狀包圍後續形成凸塊4a之區域之位置之連接焊墊31之上表面,亦形成金屬膜32。作為金屬膜32之材料,選擇與後續積層之金屬膜74(參照圖8)相同成分之金屬。另,此處,形成Au之金屬膜32。另,設置於後續形成側壁部5a之位置之連接焊墊31未與晶片3內部之電路連接。
其後,於晶片3之設置有連接焊墊31及金屬膜32之側之表面形成光阻層71。其後,藉由光微影技術,於光阻層71之形成凸塊4a之位置形成貫通孔72,使金屬膜32之表面露出。同時,於形成側壁部5a之位置形成溝槽73,使金屬膜32之表面露出。
其後,如圖8所示,於光阻層71之上表面、貫通孔72之側面、溝槽73之側面、及金屬膜32之上表面,例如藉由濺鍍,形成金屬膜74。作為金屬膜74之材料,選擇與後續填充至貫通孔72之膏50所包含之Au粒子相同成分之Au。
藉此,因光阻層71藉由表面由金屬膜43塗佈而硬化,故於包含Au粒子之膏50填充至貫通孔72之情形時,可防止微細之構造崩壞。
又,此處,亦形成金屬膜74相對於貫通孔72之深度D1,換言之,後續形成之凸塊4a之與晶片3之主面正交之方向之厚度(凸塊4a之高度D1)之膜厚d1之比例未達10%之較薄之(例如厚度未達1 μm之)金屬膜74。
例如,於形成以20 μm間距排列之高度10 μm之凸塊4之情形時,將金屬膜74之膜厚設為0.2 μm。藉此,因即使形成金屬膜74,亦可防止貫通孔72之開口變窄,故可於後續步驟將包含金屬粒子之膏50充分填充至貫通孔72。
其結果,金屬膜74相對於溝槽73之深度D2,換言之,後續形成之側壁部5a中之與晶片3之主面正交之方向之厚度(側壁部5a之高度D2)之膜厚d1之比例未達10%。
接著,如圖9所示,於形成於光阻層71之貫通孔72及溝槽73,例如填充包含純度為99.9重量%以上且粒子徑為0.005 μm~1.0 μm之Au粒子之膏50。
其後,於使膏50乾燥及燒結後,藉由使用剝離液等之剝蝕,剝離光阻層71。藉此,如圖10所示,於連接焊墊31之表面依序積層Au之金屬膜32、Au之金屬膜42、及包含粒子徑為0.005 μm~1.0 μm之Au粒子之多孔質金屬層41,完成於多孔質金屬層41之側面亦形成Au之金屬膜42之凸塊4a。
同時,以包圍形成凸塊4a之區域之方式,依序積層Au之金屬膜32、Au之金屬膜52、及包含粒子徑為0.005 μm~1.0 μm之Au粒子之多孔質金屬層51,完成於多孔質金屬層51之側面亦形成Au之金屬膜52之側壁部5a。
如此,凸塊4a於連接焊墊31上之金屬膜22與多孔質金屬層41之間,具備膜厚相對於凸塊4a之高度D1之比例未達10%之金屬膜42。再者,凸塊4a於多孔質金屬層41之側面亦設置金屬膜42。
又,側壁部5a於連接焊墊31上之金屬膜32與多孔質金屬層51之間,具備膜厚相對於側壁部5a之高度D2之比例未達10%之金屬膜52。再者,側壁部5a於多孔質金屬層51之側面亦設置金屬膜52。
該金屬膜42、52係為防止於光阻層71圖案化之凸塊4a及側壁部5a之微細構造之崩壞,而形成於光阻層71之上表面、光阻層71所形成之貫通孔72及溝槽73之側面、及金屬膜22之表面者。藉此,凸塊4a與半導體基板2側之凸塊4同樣,可進行將間距設為20 μm以下之精細間距化。
於上述之實施形態中,雖已對將未設置凸塊4a及側壁部5a之晶片3安裝於設置有凸塊4及側壁部5之半導體基板2之情形、與將設置有凸塊4a及側壁部5a之晶片3安裝於未設置凸塊4及側壁部5之半導體基板2之情形進行說明,但此為一例。
本揭示之電子機器亦可為於設置有凸塊4及側壁部5之半導體基板2安裝設置有凸塊4a及側壁部5a之晶片3之構成。該構成之情形時,將金屬膜42、52相對於凸塊4、4a及側壁部5、5a中之與半導體基板2及晶片3之主面正交之方向之厚度之一半之厚膜比例設為未達10%,較佳設為未達5%。
又,於上述之實施形態中,雖對晶片3之基材為Si以外之基材之情形進行說明,但若晶片3之基材為熱膨脹率與半導體基板2不同者,則亦可為於Si摻雜雜質者。
具備上述之半導體雷射之發光部之晶片3、及具備半導體雷射之驅動電路之半導體基板2例如搭載於ToF(Time of flight:飛行時間)感測器或結構燈等之測距裝置。半導體雷射之發光部於搭載於測距裝置之情形時,例如作為ToF感測器之光源或結構燈之光源發揮功能。
[3.效果]
電子機器1具有半導體基板2、晶片3、凸塊4、及側壁部5。凸塊4將設置於半導體基板2及晶片3之對向之主面之複數個連接焊墊21、31彼此連接。側壁部5包含以環狀包圍設置有複數個凸塊4之區域之多孔質金屬層51,連接半導體基板2與晶片3。藉此,電子機器1可提高氣密性。
晶片3之熱膨脹率與半導體基板2相差0.1 ppm/℃以上。藉此,電子機器1例如即使晶片3發熱且以與半導體基板2不同之熱膨脹率膨脹,亦因側壁部5之多孔質金屬層51彈性變化,故可抑制於側壁部5產生龜裂或間隙。再者,側壁部5因即使於晶片3或半導體基板2存在厚度之不均或翹曲,亦追隨晶片3或半導體基板2之形狀彈性變化,故可提高氣密性。
晶片3係半導體雷射。半導體基板2具有驅動半導體雷射之驅動電路。藉此,電子機器1即使因半導體雷射之發光所伴隨之發熱,使晶片3以與半導體基板2不同之熱膨脹率膨脹,側壁部5之多孔質金屬層51亦彈性變化,因而可提高氣密性。
多孔質金屬層51包含粒子徑為0.005 μm~1.0 μm之金屬粒子。該多孔質金屬層51藉由金屬粒子之尺寸效果,可以低於塊狀之金屬之熔點之溫度接合金屬。藉此,電子機器1因於設置有連接焊墊21、31及凸塊4之區域之周緣部,藉由可以較低溫金屬接合之多孔質金屬層51連接半導體基板2與晶片3,故藉由減少因熱引起之損傷,而提高氣密性。
側壁部5具有設置於多孔質金屬層51與於半導體基板2設置之連接焊墊21之間及多孔質金屬層51與於晶片3設置之連接焊墊31之間之至少任一者、與多孔質金屬層51之側面之金屬膜52。藉此,因電子機器1藉由設置於多孔質金屬層51之側面之金屬膜52防止多孔質金屬層51之崩壞,而可提高氣密性。
設置於多孔質金屬層51與於半導體基板2設置之連接焊墊21之間、及多孔質金屬層51與於晶片3設置之連接焊墊31之間之至少任一者之金屬膜52相對於側壁部5、5a之與主面正交之方向之厚度之膜厚比例未達10%。藉此,可防止於光阻層61、71圖案化之側壁部5、5a形成用之溝槽63、73因金屬膜52之形成而變窄。其結果,於光阻層61、71圖案化之溝槽63、73,可適當填充包含作為側壁部5、5a之材料之金屬粒子之膏50。
設置於多孔質金屬層51與於半導體基板2設置之連接焊墊21之間、及多孔質金屬層51與於晶片3設置之連接焊墊31之間之至少任一者之金屬膜52相對於側壁部5、5a之與主面正交之方向之厚度之一半之膜厚比例未達10%。藉此,於半導體基板2及晶片3藉由側壁部5、5a連接之電子機器之情形時,可防止於光阻層71、71圖案化之側壁部5、5a形成用之溝槽63、73因金屬膜52之形成而變窄。其結果,於光阻層61、71圖案化之溝槽63、73,可適當填充包含作為側壁部5、5a之材料之金屬粒子之膏50。
凸塊4、4a具有多孔質金屬層41、與金屬膜42。多孔質金屬層41由與側壁部5、5a之多孔質金屬層51相同之材料形成。金屬膜42設置於多孔質金屬層41與於半導體基板2設置之連接焊墊21之間、及多孔質金屬層41與於晶片3設置之連接焊墊31之間之至少任一者、與多孔質金屬層41之側面。藉此,因凸塊4、4a及側壁部5、5a可同時形成,故無需為接合密封而追加新步驟,藉由形成側壁部5、5a,可接合密封半導體基板2與晶片3。
設置於多孔質金屬層41與連接焊墊21、23之間之金屬膜42相對於凸塊4、4a之與半導體基板2之主面正交之方向之厚度之膜厚比例未達10%。藉此,藉此,可防止於光阻層61、71圖案化之凸塊4、4a形成用之貫通孔62、72因金屬膜42之形成而變窄。其結果,於光阻層61、71圖案化之貫通孔62、72,可適當填充包含作為凸塊4、4a之材料之金屬粒子之膏50。
設置於多孔質金屬層41與連接焊墊21、23之間之金屬膜42相對於凸塊4、4a之與半導體基板2之主面正交之方向之厚度之一半之膜厚比例未達10%。藉此,於半導體基板2及晶片3藉由凸塊4、4a連接之電子機器之情形時,可防止於光阻層61、71圖案化之凸塊4、4a形成用之貫通孔62、72因金屬膜42之形成而變窄。其結果,於光阻層61、71圖案化之貫通孔62、72,可適當填充包含作為凸塊4、4a之材料之金屬粒子之膏50。
多孔質金屬層41、51及金屬膜42、43之材料係相同種類之金屬。藉此,可提高多孔質金屬層41、51與金屬膜42、43之接合強度。
多孔質金屬層41、51之材料係包含純度為99.9重量%以上之金、銀、鉑或銅之多孔質之金屬。藉此,可將半導體基板2之連接焊墊21、與晶片3之連接焊墊31之間之連接電阻抑制得較低。
另,本說明書所記載之效果僅為例示而非限定者,又,可為其他效果。
另,本技術亦可採取如下般構成。
(1)
一種電子機器,其具有:
半導體基板;
晶片;
凸塊,其將設置於上述半導體基板及上述晶片之對向之主面之複數個連接焊墊彼此連接;及
側壁部,其包含以環狀包圍設置複數個上述凸塊之區域之多孔質金屬層,連接上述半導體基板與上述晶片。
(2)
如上述(1)之電子機器,其中
上述晶片與上述半導體基板,熱膨脹率相差0.1 ppm/℃以上。
(3)
如上述(1)或(2)之電子機器,其中
上述晶片係半導體雷射;
上述半導體基板具有驅動上述半導體雷射之驅動電路。
(4)
如上述(1)~(3)中任一項之電子機器,其中
上述多孔質金屬層包含粒子徑為0.005 μm~1.0 μm之金屬粒子。
(5)
如上述(1)~(4)中任一項之電子機器,其中
上述側壁部具有:
金屬膜,其於上述多孔質金屬層與於上述半導體基板設置之連接焊墊之間、及上述多孔質金屬層與於上述晶片設置之連接焊墊之間中至少任一者、與上述多孔質金屬層之側面設置。
(6)
如上述(5)之電子機器,其中
於上述多孔質金屬層與於上述半導體基板設置之連接焊墊之間、及上述多孔質金屬層與於上述晶片設置之連接焊墊之間中至少任一者設置之上述金屬膜,相對於上述側壁部之與上述主面正交之方向之厚度之膜厚比例未達10%。
(7)
如上述(5)之電子機器,其中
於上述多孔質金屬層與於上述半導體基板設置之連接焊墊之間、及上述多孔質金屬層與於上述晶片設置之連接焊墊之間中至少任一者設置之上述金屬膜,相對於上述側壁部之與上述主面正交之方向之厚度之一半之膜厚比例未達10%。
(8)
如上述(1)~(7)中任一項之電子機器,其中
上述凸塊具有:
多孔質金屬層,其由與上述側壁部之多孔質金屬層相同之材料形成;及
金屬膜,其於該多孔質金屬層與於上述半導體基板設置之連接焊墊之間、及該多孔質金屬層與於上述晶片設置之上述連接焊墊之間中至少任一者、與該多孔質金屬層之側面設置。
(9)
如上述(8)之電子機器,其中
於上述多孔質金屬層與連接焊墊之間設置之上述金屬膜相對於上述凸塊之與上述主面正交之方向之厚度之膜厚比例未達10%。
(10)
如上述(8)之電子機器,其中
於上述多孔質金屬層與連接焊墊之間設置之上述金屬膜相對於上述凸塊之與上述主面正交之方向之厚度之一半之膜厚比例未達10%。
(11)
如上述(5)~(10)中任一項之電子機器,其中
上述多孔質金屬層及上述金屬膜之材料係相同種類之金屬。
(12)
如上述(1)~(11)中任一項之電子機器,其中
上述多孔質金屬層之材料係包含純度99.9重量%以上之金、銀、鉑、或銅之多孔質之金屬。
1:電子機器
2:半導體基板
3:晶片
4:凸塊
4a:凸塊
5:側壁部
5a:側壁部
21:連接焊墊
22:金屬膜
31:連接焊墊
32:金屬膜
41:多孔質金屬層
42:金屬膜
50:膏
51:多孔質金屬層
52:金屬膜
61:光阻層
62:貫通孔
63:溝槽
64:金屬膜
71:光阻層
72:貫通孔
73:溝槽
74:金屬膜
d1:膜厚
D1:深度(高度)
D2:深度(高度)
圖1係本揭示之實施形態之電子機器之剖面說明圖。
圖2係圖1所示之A-A線之剖面說明圖。
圖3係顯示本揭示之於半導體基板形成凸塊及側壁部之步驟之說明圖。
圖4係顯示本揭示之於半導體基板形成凸塊及側壁部之步驟之說明圖。
圖5係顯示本揭示之於半導體基板形成凸塊及側壁部之步驟之說明圖。
圖6係顯示本揭示之於半導體基板形成凸塊及側壁部之步驟之說明圖。
圖7係顯示本揭示之於晶片形成凸塊及側壁部之步驟之說明圖。
圖8係顯示本揭示之於晶片形成凸塊及側壁部之步驟之說明圖。
圖9係顯示本揭示之於晶片形成凸塊及側壁部之步驟之說明圖。
圖10係顯示本揭示之於晶片形成凸塊及側壁部之步驟之說明圖。
1:電子機器
2:半導體基板
3:晶片
4:凸塊
5:側壁部
21:連接焊墊
22:金屬膜
31:連接焊墊
32:金屬膜
41:多孔質金屬層
42:金屬膜
51:多孔質金屬層
52:金屬膜
Claims (12)
- 一種電子機器,其具有: 半導體基板; 晶片; 凸塊,其將設置於上述半導體基板及上述晶片之對向之主面之複數個連接焊墊彼此連接;及 側壁部,其包含以環狀包圍設置複數個上述凸塊之區域之多孔質金屬層,連接上述半導體基板與上述晶片。
- 如請求項1之電子機器,其中 上述晶片與上述半導體基板,熱膨脹率相差0.1 ppm/℃以上。
- 如請求項1之電子機器,其中 上述晶片係半導體雷射; 上述半導體基板具有驅動上述半導體雷射之驅動電路。
- 如請求項1之電子機器,其中 上述多孔質金屬層包含粒子徑為0.005 μm~1.0 μm之金屬粒子。
- 如請求項1之電子機器,其中 上述側壁部具有: 金屬膜,其於上述多孔質金屬層與於上述半導體基板設置之連接焊墊之間、及上述多孔質金屬層與於上述晶片設置之連接焊墊之間中至少任一者、與上述多孔質金屬層之側面設置。
- 如請求項5之電子機器,其中 於上述多孔質金屬層與於上述半導體基板設置之連接焊墊之間、及上述多孔質金屬層與於上述晶片設置之連接焊墊之間中至少任一者設置之上述金屬膜,相對於上述側壁部之與上述主面正交之方向之厚度之膜厚比例未達10%。
- 如請求項5之電子機器,其中 於上述多孔質金屬層與於上述半導體基板設置之連接焊墊之間、及上述多孔質金屬層與於上述晶片設置之連接焊墊之間中至少任一者設置之上述金屬膜,相對於上述側壁部之與上述主面正交之方向之厚度之一半之膜厚比例未達10%。
- 如請求項1之電子機器,其中 上述凸塊具有: 多孔質金屬層,其由與上述側壁部之多孔質金屬層相同之材料形成;及 金屬膜,其於該多孔質金屬層與於上述半導體基板設置之連接焊墊之間、及該多孔質金屬層與於上述晶片設置之連接焊墊之間中至少任一者、與該多孔質金屬層之側面設置。
- 如請求項8之電子機器,其中 於上述多孔質金屬層與連接焊墊之間設置之上述金屬膜相對於上述凸塊之與上述主面正交之方向之厚度之膜厚比例未達10%。
- 如請求項8之電子機器,其中 於上述多孔質金屬層與連接焊墊之間設置之上述金屬膜相對於上述凸塊之與上述主面正交之方向之厚度之一半之膜厚比例未達10%。
- 如請求項5之電子機器,其中 上述多孔質金屬層及上述金屬膜之材料係相同種類之金屬。
- 如請求項1之電子機器,其中 上述多孔質金屬層之材料係包含純度99.9重量%以上之金、銀、鉑、或銅之多孔質之金屬。
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JP5924235B2 (ja) * | 2012-10-30 | 2016-05-25 | 株式会社ソシオネクスト | 半導体装置およびその製造方法 |
TWI662657B (zh) * | 2015-04-07 | 2019-06-11 | 聯華電子股份有限公司 | 半導體元件的堆疊結構 |
JP2018160589A (ja) * | 2017-03-23 | 2018-10-11 | 富士通株式会社 | 電子装置、及び電子装置の製造方法 |
JP7480711B2 (ja) * | 2019-02-05 | 2024-05-10 | ソニーグループ株式会社 | 発光素子組立体、マルチビームレーザチップ組立体及び光造形装置、並びに、部材組立体及びその製造方法 |
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2022
- 2022-01-28 WO PCT/JP2022/003199 patent/WO2022176563A1/ja active Application Filing
- 2022-01-28 US US18/264,719 patent/US20240113066A1/en active Pending
- 2022-01-28 CN CN202280009141.2A patent/CN116711056A/zh active Pending
- 2022-01-28 JP JP2023500684A patent/JPWO2022176563A1/ja active Pending
- 2022-01-28 KR KR1020237025731A patent/KR20230147601A/ko unknown
- 2022-01-28 EP EP22755886.3A patent/EP4297071A1/en active Pending
- 2022-02-11 TW TW111105036A patent/TW202247360A/zh unknown
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US20240113066A1 (en) | 2024-04-04 |
CN116711056A (zh) | 2023-09-05 |
KR20230147601A (ko) | 2023-10-23 |
WO2022176563A1 (ja) | 2022-08-25 |
EP4297071A1 (en) | 2023-12-27 |
JPWO2022176563A1 (zh) | 2022-08-25 |
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