CN116711056A - 电子器件 - Google Patents

电子器件 Download PDF

Info

Publication number
CN116711056A
CN116711056A CN202280009141.2A CN202280009141A CN116711056A CN 116711056 A CN116711056 A CN 116711056A CN 202280009141 A CN202280009141 A CN 202280009141A CN 116711056 A CN116711056 A CN 116711056A
Authority
CN
China
Prior art keywords
metal layer
porous metal
chip
semiconductor substrate
electronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202280009141.2A
Other languages
English (en)
Inventor
今东孝之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Semiconductor Solutions Corp
Original Assignee
Sony Semiconductor Solutions Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Publication of CN116711056A publication Critical patent/CN116711056A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02355—Fixing laser chips on mounts
    • H01S5/0237—Fixing laser chips on mounts by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H01S5/0261—Non-optical elements, e.g. laser driver components, heaters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11466—Conformal deposition, i.e. blanket deposition of a conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13169—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/27444—Manufacturing methods by blanket deposition of the material of the layer connector in gaseous form
    • H01L2224/2745—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/27466—Conformal deposition, i.e. blanket deposition of a conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/2747—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/278—Post-treatment of the layer connector
    • H01L2224/27848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2902—Disposition
    • H01L2224/29023—Disposition the whole layer connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2902—Disposition
    • H01L2224/29034—Disposition the layer connector covering only portions of the surface to be connected
    • H01L2224/29035—Disposition the layer connector covering only portions of the surface to be connected covering only the peripheral area of the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29169—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/012—Semiconductor purity grades
    • H01L2924/01203—3N purity grades, i.e. 99.9%
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10335—Indium phosphide [InP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1426—Driver
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H01S5/0234—Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings

Abstract

根据本发明的电子器件(1)设置有半导体基板(2)、芯片(3)、凸块(4,4a)和侧壁部(5,5a)。所述凸块(4,4a)将设置于所述半导体基板(2)和所述芯片(4,4a)的相互面对的主表面上的多个连接焊盘(21,31)彼此连接。所述侧壁部(5,5a)包括多孔质金属层(41,51)，所述多孔质金属层(41,51)环状地包围设置有多个所述凸块(4,4a)的区域，并且所述侧壁部(5,5a)将所述半导体基板(2)和所述芯片(3)连接起来。所述芯片(3)的热膨胀系数与所述半导体基板(2)的热膨胀系数之间的差为0.1ppm/℃以上。所述芯片(3)是半导体激光器，并且所述半导体基板(2)包括用于驱动所述半导体激光器的驱动电路。

Description

电子器件
技术领域
本发明涉及一种电子器件。
背景技术
关于把电子电路元件以倒装芯片(flip-chip)方式连接于基板上的电子器件，为了防止当从半导体芯片将各电子器件单片化地切割下来时所使用的切割水侵入，使用例如树脂来密封该电子器件。
然而，在使用树脂来密封该电子器件时，存在诸如电极被树脂污染、因向每个电子器件注射树脂而导致作业时间的延长、以及因作业时间的延长而导致要废弃的树脂量的增加等问题。
因此，存在这样一种电子器件(例如，参见专利文献1)：其中，电子电路元件的电极和基板的电极这二者之间利用金-锡接合、金-银接合、金-铝接合或金-金接合而彼此连接，并且电子电路元件的周缘部和与之相对的基板利用与电极间连接相同的连接方法而被接合且被密封。即，有一种电子器件，其中，电子电路元件的芯片电极和基板的内部电极利用金-锡(Au-Sn)接合、金-银(Au-Ag)接合，金-铝(Au-Al)接合或金-金(Au-Au)接合而彼此连接，并且电子电路元件的周缘部或待密封部和与之相对的基板利用与上述相同的连接方法而被接合且被密封。
引用文献列表
专利文献
专利文献1:日本专利申请特开JP 2004-214469A
发明内容
本发明要解决的技术问题
然而，在上述现有技术中，当电子电路元件或基板具有厚度不均或翘曲时，就会相对于被密封部分的金属而产生间隙，并且电子器件的气密性会降低。因此，本发明提出了一种能够提高气密性的电子器件。
解决问题的技术方案
根据本发明，提供了一种电子器件。根据本发明的电子器件包括半导体基板、芯片、凸块和侧壁部。所述凸块将设置于所述半导体基板和所述芯片的相互面对的主表面上的多个连接焊盘彼此连接。所述侧壁部包括多孔质金属层，所述多孔质金属层环状地包围设置有多个所述凸块的区域，并且所述侧壁部将所述半导体基板和所述芯片连接起来。
附图说明
图1是根据本发明实施方案的电子器件的剖面说明图。
图2是沿着图1所示的线A-A剖开的剖面说明图。
图3是示出了根据本发明的在半导体基板上形成凸块和侧壁部的步骤的说明图。
图4是示出了根据本发明的在半导体基板上形成凸块和侧壁部的步骤的说明图。
图5是示出了根据本发明的在半导体基板上形成凸块和侧壁部的步骤的说明图。
图6是示出了根据本发明的在半导体基板上形成凸块和侧壁部的步骤的说明图。
图7是示出了根据本发明的在芯片上形成凸块和侧壁部的步骤的说明图。
图8是示出了根据本发明的在芯片上形成凸块和侧壁部的步骤的说明图。
图9是示出了根据本发明的在芯片上形成凸块和侧壁部的步骤的说明图。
图10是示出了根据本发明的在芯片上形成凸块和侧壁部的步骤的说明图。
具体实施方案
下面，将会在附图的基础上详细说明本发明的实施方案。注意，在下面所说明的各实施方案中，相同的部分由相同的附图标记及相同的阴影线表示，并且将会省略重复的说明。
[1.电子器件的剖面构造]
图1是根据本发明的实施方案的电子器件的剖面说明图。图2是沿着图1所示的线A-A剖开的剖面说明图。如图1所示，根据本发明的电子器件1包括半导体基板2、芯片3和凸块4，所述凸块4将设置于半导体基板2和芯片3的相互面对的主表面上的连接焊盘21和31彼此连接。
此外，如图1和图2所示，电子器件1包括侧壁部5，所述侧壁部5包含环状地包围设置有多个凸块4的区域的多孔质金属层51，并且所述侧壁部5将半导体基板2和芯片3连接起来。另外，在电子器件1中，在侧壁部5和半导体基板2之间还设置有连接焊盘21。设置于侧壁部5和半导体基板2之间的连接焊盘21未与半导体基板2内部的电路连接。
芯片3例如是半导体激光器，并且在砷化镓(GaAs)基底材料的一侧主表面上包括多个连接焊盘31。另外，芯片3在该基底材料内部包括该半导体激光器的发光部等。该发光部包括发射激光的呈二维状排列的多个发光元件。这些发光元件在芯片3内被连接至连接焊盘31。
注意，芯片3所包含的电子部件亦可以是除了半导体激光器的发光部以外的任何电子部件。另外，例如，芯片3的基底材料可以是诸如磷化铟(InP)等半绝缘性基底材料。
半导体基板2例如是硅(Si)基板，并且在该半导体基板内包括用于驱动半导体激光器的驱动电路。半导体基板2在一侧主表面上包括多个连接焊盘21。连接焊盘21被连接至半导体基板2内部的驱动电路。注意，半导体基板2所包含的电子电路亦可以是除了用于半导体激光器的驱动电路以外的任何电子电路。
在电子器件1中，芯片3以倒装芯片方式安装在半导体基板2上，并且半导体基板2中的驱动电路和作为半导体激光器的芯片3通过凸块4彼此电气连接。另外，在电子器件1中，设置有连接焊盘21和31及凸块4的空间由侧壁部5气密地密封。
这里，例如，在通过将包括半导体激光器的芯片3以倒装芯片方式安装到包括用于该半导体激光器的驱动电路的半导体基板2上来制造电子器件的情况下，在常规制造方法中，首先在Si芯片上形成多个驱动电路。
然后，芯片3经由块体状金属凸块被层叠到各驱动电路上，并且利用这些凸块将设置于驱动电路和芯片3的相互面对的主表面上的连接焊盘21和31彼此连接。接着，对Si芯片进行切割从而按照各电子器件进行单片化。
在将Si芯片切割从而按照各电子器件进行单片化的步骤中，一边向Si芯片供给切割水一边进行切片。此时，如果切割水侵入半导体基板2和芯片3之间，那么就会对电子器件产生不利影响。因此，通常，利用树脂密封各电子器件，然后才将Si芯片切割以按照各电子器件进行单片化。
然而，当利用树脂密封电子器件时，存在诸如电极被树脂污染、由于向各电子器件注射树脂而导致作业时间的延长、以及由于作业时间的延长而导致要废弃的树脂量的增加等问题。
因此，存在这样一种技术，即，利用凸块把设置于半导体基板2和芯片3的相互面对的主表面上的连接焊盘21和31彼此连接，并且利用与连接焊盘21和31之间的连接相同的连接方法将需要密封的且设置有连接焊盘21、31及凸块的区域接合且密封。
另外，在常规的倒装芯片方式的安装中，通过挤压和加热设置于半导体基板2和芯片3的相互面对的主表面上的块体状的由诸如金(Au)、铜(Cu)或焊料等金属制成的凸块，将芯片3安装到半导体基板2上。
然而，在半导体基板2和芯片3二者的热膨胀系数彼此相差例如0.1ppm/℃以上的情况下，如果使用块体状的Au、Cu或焊料等作为凸块的材料，就会出现以下所述的问题。
例如，在块体状的Au被用作凸块的材料的情况下，为了利用凸块稳定地连接具有不同热膨胀系数的半导体基板2和芯片3，就需要将凸块加热到300℃以上的高温，并且在半导体基板2和芯片3之间施加100MPa以上的高压。
另外，在块体状的Cu被用作凸块的材料的情况下，就需要在380℃以上进行加热。如此一来，当使用块体状的Au或Cu作为凸块的材料时，必须在高温和高压下进行凸块的连接，而高温和高压可能会损坏芯片3，并且可能会使电子器件的可靠性降低。
对照地，在焊料被用作凸块的材料的情况下，与Au和Cu的情况相比，可以在较低的温度和较低的压力下进行凸块的连接，但是焊料的耐热性和连接强度不如Au和Cu。因此，当由于搭载在芯片3上的诸如半导体激光器等电子部件的发热而引起芯片3热膨胀时，例如，就存在由于半导体基板2和芯片3之间的热膨胀系数的差别而导致由焊料制成的凸块发生开路故障(open failure)的可能性，并且因此使得电子器件的可靠性降低了。
另外，如上所述，根据本发明的半导体基板2是Si基板，并且具有5.7ppm/℃的热膨胀系数。另一方面，根据本发明的芯片3的基底材料是GaAs，并且具有2.6ppm/℃的热膨胀系数。
如此一来，在电子器件1中，半导体基板2和芯片3之间的热膨胀系数之差远大于0.1ppm/℃。因此，在电子器件1中，当凸块的材料是块体状的Au、Cu或焊料时，就存在出现上述问题并且使得可靠性降低的可能性。
此外，在半导体基板2和芯片3之间的待密封区域的周缘部被具有经过镀敷处理的表面的块体状金属包围、接合且密封的情况下，如果半导体基板2与芯片3之间的热膨胀系数之差例如为0.1ppm/℃以上，那么在被密封部分中就出现裂纹。因此，降低了电子器件的气密性。
此外，如果半导体基板2或芯片3具有厚度不均或翘曲，那么在层叠半导体基板2和芯片3时，在被密封部分中仅可以在镀敷膜的凸面的突起处将半导体基板2和芯片3接合。
结果，在电子器件中，在被密封部分处散布有间隙，故而就使气密性降低了。此外，如果为了防止在被密封部分处产生间隙而通过升高温度和增加压力来将半导体基板2和芯片3接合，那么在电子器件中在相邻的微细凸块之间就存在出现短路故障的可能性。
因此，电子器件1的凸块4例如包括Au的多孔质(porous)金属层41。多孔质金属层41包含粒子直径为0.005μm至1.0μm且纯度为99.9重量％以上的Au粒子。注意，多孔质金属层41的成分可以是例如纯度为99.9重量％以上的Cu、银(Ag)或铂(Pt)。
由于粒子直径的尺寸效果，包含粒子直径为0.005μm至1.0μm的金属粒子的多孔质金属层41可以在比块体状金属的熔点低的温度下进行金属接合。例如，在成分为Au的情况下、在成分为Ag的情况下以及在成分为Cu的情况下，多孔质金属层41可以分别在大约100℃、大约250℃以及大约150℃的温度下将半导体基板2和芯片3连接。因此，电子器件1能够减少由于热引起的对芯片3的损坏，从而能够提高可靠性。
另外，由于多孔质金属层41具有弹性，因此，即使例如由于半导体激光器的发热而使得芯片3以与半导体基板2的热膨胀系数不同的热膨胀系数膨胀时，多孔质金属层41也会弹性变形，因此能够抑制开路故障的发生。于是，与例如使用由焊料制成的凸块的情况相比，电子器件1能够提高可靠性。
电子器件1可以通过如下方式而制造出来：把芯片3层叠到在上表面上设置有凸块4的半导体基板2上，使凸块4的多孔质金属层41在不熔融的状态下连接至连接焊盘31，并且芯片3以倒装芯片方式被安装到半导体基板2上。
另外，电子器件1亦可以通过如下方式而制造出来：把在下表面上设置有包括多孔质金属层41的凸块4的芯片3层叠到半导体基板2上，使凸块4的多孔质金属层41在不熔融的状态下连接至连接焊盘21，并且芯片3以倒装芯片方式被安装到半导体基板2上。注意，可以在层叠之前在半导体基板2和芯片3两者上都设置有包括多孔质金属层41的凸块4。
当凸块4被设置在半导体基板2侧时，该凸块4包括位于多孔质金属层41与半导体基板2侧的连接焊盘21之间的金属膜42。此外，当凸块4被设置在芯片3侧时，该凸块4包括位于多孔质金属层41与芯片3侧的连接焊盘31之间的金属膜42。注意，金属膜42可以设置在多孔质金属层41与半导体基板2侧的连接焊盘21之间和/或多孔质金属层41与芯片3侧的连接焊盘31之间。
在本发明中，通过将金属膜42的膜厚度相对于凸块4的在与半导体基板2的主表面正交的方向上的厚度的比率设定为小于10％，能够实现使凸块4的节距(pitch)为20μm以下的精细化节距。关于该精细化节距，稍后将会与凸块4的形成步骤一起进行说明。
此外，凸块4还包括设置于多孔质金属层41的侧表面(侧周面)上的金属膜42。金属膜42的材料优选地与多孔质金属层41的材料相同。例如，当多孔质金属层41的材料为Au时，金属膜42优选地为Au膜。
藉此，由于多孔质金属层41的侧表面被涂布有金属膜42，因此凸块4能够防止多孔质金属层41的粒子发生崩塌而飞散。于是，凸块4能够防止由于多孔质金属层41的粒子的飞散而导致相邻的凸块4彼此短路。
另外，如果多孔质金属层41的侧表面上未设置有金属膜42，那么表面相对较软的多孔质金属层41的侧表面会出现表面粗糙，并且凸块4彼此出现形状不均。
对照地，由于在凸块4的多孔质金属层41的侧表面上设置有比多孔质金属层41硬的金属膜42，因此抑制了凸块4彼此的形状不均，并且凸块全都具有均一形状。此外，由于凸块4的侧表面被涂布有相对较硬的金属膜42，因此能够实现进一步的微细化，从而能够实现更精细化的节距。
此外，当芯片3以倒装芯片方式安装到半导体基板2上时，虽然凸块4在厚度方向上略微被压坏，但防止了多孔质金属层41的粒子泄漏到金属膜42的外部。因此，在凸块4中，因为金属膜42内部的多孔质金属层41的粒子密度增大了，所以使得连接电阻能够降低。
此外，电子器件1的侧壁部5具有与凸块4相同的结构。具体地，侧壁部5包括Au的多孔质金属层51。多孔质金属层51包含粒子直径为0.005μm至1.0μm并且纯度为99.9重量％以上的Au粒子。注意，例如，多孔质金属层51的成分可以是纯度为99.9重量％以上的Cu、银(Ag)或铂(Pt)。
如前所述，由于粒子直径的尺寸效果，多孔质金属层51可以在比块体状金属的熔点低的温度下进行金属接合。因此，电子器件1能够减少在形成多孔质金属层51时由于热引起的对芯片3的损坏，从而能够提高可靠性。
另外，由于多孔质金属层51具有弹性，因此，即使例如由于半导体激光器的发热而使得芯片3以与半导体基板2的热膨胀系数不同的热膨胀系数膨胀时，多孔质金属层51也会弹性变形，因此能够抑制在侧壁部5中出现裂纹。藉此，电子器件1能够提高需要密封的且设置有连接焊盘21和31及凸块4的区域的气密性。
另外，由于多孔质金属层51能够弹性变形，因此，例如即使在半导体基板2或芯片3存在厚度不均或翘曲的情况下，在将半导体基板2和芯片3接合时，多孔质金属层51也会随着半导体基板2或者芯片3的表面形状而变形。
于是，电子器件1能够抑制在侧壁部5与半导体基板2二者的连接部分处以及在侧壁部5与芯片3二者的连接部分处产生间隙，因而能够提高气密性。
另外，如图2所示，侧壁部5被设置成环状地包围需要密封的且设置有连接焊盘21和31及凸块4的区域。因此，在半导体基板2或芯片3热膨胀时，电子器件1能够减轻施加到设置于角部处的凸块4的机械应力。
具体地，在半导体基板2或芯片3热膨胀的情况下，因温度变化而引起的膨胀量和收缩量从半导体基板2或者芯片3的主表面的中央朝着周缘部是增大的。因此，如果没有侧壁部5，那么机械应力就会被施加到设置于角部处的凸块4。
对照地，在电子器件1中，由于半导体基板2和芯片3的周缘部由侧壁部5密封，因此能够利用侧壁部5来抑制因温度变化而引起的半导体基板2和芯片3的周缘部的膨胀和收缩。因此，电子器件1能够减轻施加到设置于角部处的凸块4的机械应力。
当侧壁部5被设置在半导体基板2侧时，该侧壁部5包括位于多孔质金属层51与半导体基板2的主表面上的连接焊盘21之间的金属膜52。此外，当侧壁部5被设置在芯片3侧时，该侧壁部5包括位于多孔质金属层51与芯片3的主表面上的连接焊盘之间的金属膜52。注意，金属膜52可以被设置在多孔质金属层51与半导体基板2的主表面上的连接焊盘21之间和/或多孔质金属层52与芯片3的主表面上的连接焊盘之间。
在本发明中，通过将金属膜52的膜厚度相对于侧壁部5的在与半导体基板2的主表面正交的方向上的厚度的比率设定为小于10％，就能够在同时形成侧壁部5和凸块4的步骤中，实现使凸块4的节距为20μm以下的精细化节距。
此外，侧壁部5还包括设置于多孔质金属层51的侧表面(侧周面)上的金属膜52。金属膜52的材料优选地与多孔质金属层51的材料相同。例如，当多孔质金属层51的材料为Au时，金属膜52优选地为Au膜。
藉此，由于多孔质金属层51的侧表面被涂布有金属膜52，因此侧壁部5能够防止多孔质金属层51的粒子发生崩塌而飞散。于是，侧壁部5能够防止由于多孔质金属层51的粒子的飞散而导致相邻的凸块4彼此短路。
另外，如果多孔质金属层51的侧表面上未设置有金属膜52，那么表面相对较软的多孔质金属层51的侧表面会出现表面粗糙，并且侧壁部5的侧表面会出现形状不均。
对照地，由于在侧壁部5的多孔质金属层51的侧表面上设置有比多孔质金属层51硬的金属膜52，因此抑制了侧表面的形状不均，并且整个侧表面具有均一的表面形状。此外，由于侧壁部5的侧表面被涂布有相对较硬的金属膜52，因此能够实现进一步的微细化。
电子器件1可以通过如下方式而制造出来：把未设置有凸块4a(参照图10)的芯片3层叠到在上表面上设置有凸块4的半导体基板2上，使凸块4的多孔质金属层41在不熔融的状态下连接至连接焊盘31，并且芯片3以倒装芯片方式被安装到半导体基板2上。
此外，电子器件1亦可以通过如下方式而制造出来：把在下表面上设置有包括多孔质金属层41的凸块4a(参照图10)的芯片3层叠在未设置有凸块4的半导体基板2上，使凸块4a的多孔质金属层41在不熔融的状态下连接至连接焊盘21，并且芯片3以倒装芯片方式被安装到半导体基板2上。注意，可以在层叠之前在半导体基板2、芯片3两者上都设置有包括多孔质金属层41的凸块4、4a。
[2.凸块和侧壁部的形成步骤]
接下来，将会参照图3至图10来说明根据本发明的凸块和侧壁部的形成步骤。图3至图6是示出了根据本发明的在半导体基板上形成凸块和侧壁部的步骤的说明图。图7至图10是示出了根据本发明的在芯片上形成凸块和侧壁部的步骤的说明图。
如图3所示，在半导体基板2上形成凸块4和侧壁部5的情况下，首先，在半导体基板2上的设置于稍后将要形成凸块4的位置处的连接焊盘21的上表面上，形成金属膜22。此时，同时，在设置于稍后将要形成侧壁部5的位置处的连接焊盘21的上表面上，即，在半导体基板2的主表面上的设置于环状地包围稍后将要形成有凸块4的区域的位置处的连接焊盘21的上表面上，也形成金属膜32。作为金属膜22的材料，可以选择与稍后将要层叠的金属膜64(参照图4)具有相同成分的金属。注意，这里，形成了Au的金属膜22。
然后，在半导体基板2的设置有连接焊盘21和金属膜22侧的表面上形成光致抗蚀剂层61。然后，通过光刻技术在光致抗蚀剂层61中的将要形成凸块4的位置处形成通孔62，以使金属膜22的表面露出。同时，在将要形成侧壁部5的位置处形成凹槽63，以使金属膜22的表面露出。
此时，通孔62被形成得使相邻通孔62的中心之间的间隔为20μm(20μm节距)。这些通孔62在后续的步骤中将会被含有作为多孔质金属层41的材料的金属粒子的浆料50填充，但是由于节距为20μm的微细结构，因此当在这种状态下直接用浆料50填充时，则存在着该微细结构可能受损和崩塌的可能性。
因此，如图4所示，在光致抗蚀剂层61的上表面、通孔62的侧面、凹槽63的侧面、以及金属膜22的上表面上，通过例如溅射法形成金属膜64。作为金属膜64的材料，可以选择与随后将要填充到通孔62中的浆料50所含有的金属粒子具有相同成分的金属。注意，这里，形成Au的金属膜64。
籍此，由于通过用金属膜64对表面进行涂布来使光致抗蚀剂层61硬化，因此当用含有金属粒子的浆料50填充通孔62时，就能够防止微细结构崩塌。
另外，如果这里所形成的金属膜64的膜厚度太厚，那么通孔62的开口就变得狭窄，因而就变得难以将含有金属粒子的浆料50填充到通孔62中。因此，这里，形成较薄(例如，厚度小于1μm)的金属膜64，以使得：金属膜64的膜厚度d1相对于通孔62的深度D1的比率，换言之，相对于稍后将要形成的凸块4的在与半导体基板2的主表面正交的方向上的厚度(凸块4的高度D1)的比率小于10％。
例如，在形成以20μm节距排列的且高度为10μm的凸块4的情况下，金属膜64的膜厚度被设定为0.2μm。因此，即使在形成有金属膜64时，也能够防止通孔62的开口变狭窄，于是在后续的步骤中能够将含有金属粒子的浆料50充分地填充至通孔62中。
结果，金属膜64的膜厚度d1相对于凹槽63的深度D2的比率，换言之，相对于稍后将要形成的侧壁部5的在与半导体基板2的主表面正交的方向上的厚度(侧壁部5的高度D2)的比率小于10％。
接着，如图5所示，把含有Au粒子的浆料50填充到形成于光致抗蚀剂层61中的通孔62和凹槽63内，例如，所述Au粒子的纯度为99.9重量％以上且粒子直径为0.005μm至1.0μm。作为把浆料50填充到通孔62和凹槽63中的方法，例如，可以使用诸如丝网印刷或用刮刀把滴落的浆料50铺开的方法等任何方法。
此后，将浆料50干燥并且进行烧结，然后通过使用剥离溶液(strippingsolution)等的剥蚀法(lift-off)将光致抗蚀剂层61剥离。因此，如图6所示，在连接焊盘21的表面上依次层叠了Au的金属膜22、Au的金属膜42及含有粒子直径为0.005μm至1.0μm的Au粒子的多孔质金属层41，于是也就完成了其中在多孔质金属层41的侧表面上也形成有Au的金属膜42的凸块4。
同时，以包围形成有凸块4的区域的方式依次层叠了Au的金属膜22、Au的金属膜52及含有粒子直径为0.005μm至1.0μm的Au粒子的多孔质金属层51，于是也就完成了其中在多孔质金属层51的侧表面上也形成有Au的金属膜52的侧壁部5。
如上所述，凸块4包括位于多孔质金属层41与连接焊盘21上的金属膜22之间的金属膜42，该金属膜42的膜厚度相对于凸块4的高度D1的比率小于10％。此外，凸块4还包括设置于多孔质金属层41的侧表面上的金属膜42。
另外，侧壁部5包括位于多孔质金属层51与连接焊盘21上的金属膜22之间的金属膜52，该金属膜52的膜厚度相对于侧壁部5的高度D2的比率小于10％。此外，侧壁部5还包括设置于多孔质金属层51的侧表面上的金属膜52。
为了防止在光致抗蚀剂层61中予以图案化的凸块4和侧壁部5的微细结构发生崩塌而把金属膜42、52形成在光致抗蚀剂层61的上表面、光致抗蚀剂层61中所形成的通孔62和凹槽63的侧面、以及金属膜22的表面上。籍此，凸块4可以具有使节距为20μm以下的精细化节距。
另外，由于在连接焊盘21的表面上通过溅射法形成金属膜22，因此即使当连接焊盘21是具有与金属膜22的成分不同的成分的金属时，金属膜22也能牢固地接合至连接焊盘21。
另外，金属膜42、52亦可以由具有与多孔质金属层41、51的成分不同的成分的金属来形成，但在由相同成分的Au形成的情况下，多孔质金属41、51与设置于具有不同成分的其他金属膜上的情况相比能够以更牢固的接合力接合至金属膜42、52。注意，当多孔质金属层41、51是除Au以外的成分(例如，Cu、银(Ag)或铂(Pt))时，金属膜42、52亦可以使用与多孔质金属层41、51相同的金属(例如，Cu、银(Ag)或铂(Pt))。
接下来，将会说明在芯片3上形成图10所示的凸块4a和侧壁部5a的步骤。如图7所示，在芯片3上形成凸块4a和侧壁部5的情况下，首先，在芯片3上的设置于稍后将要形成凸块4a的位置处的连接焊盘31的上表面上，形成金属膜32。此时，同时，在设置于稍后将要形成侧壁部5a的位置处的连接焊盘31的上表面上，即，在芯片3的主表面上的设置于环状地包围稍后将要形成有凸块4a的区域的位置处的连接焊盘31的上表面上，也形成金属膜32。作为金属膜32的材料，可以选择与稍后将要层叠的金属膜74(参照图8)具有相同成分的金属。注意，这里，形成了Au的金属膜32。注意，设置于稍后将要形成侧壁部5a的位置处的连接焊盘31不与芯片3内部的电路连接。
此后，在芯片3的设置有连接焊盘31和金属膜32侧的表面上形成光致抗蚀剂层71。然后，通过光刻技术在光致抗蚀剂层71中的将要形成凸块4a的位置处形成通孔72，以使金属膜32的表面露出。同时，在将要形成侧壁部5a的位置处形成凹槽73，以使金属膜32的表面露出。
然后，如图8所示，在光致抗蚀剂层71的上表面、通孔72的侧面、凹槽73的侧面、以及金属膜32的上表面上，通过例如溅射法形成金属膜74。作为金属膜74的材料，可以选择与稍后将要被填充到通孔72中的浆料50所包含的Au粒子具有相同成分的Au。
籍此，由于通过用金属膜43对表面进行涂布来使光致抗蚀剂层71硬化，因此当用含有Au粒子的浆料50填充通孔72时，能够防止微细结构崩塌。
此外，这里，同样也形成较薄(例如，厚度小于1μm)的金属膜74，以使得：金属膜74的膜厚度d1相对于通孔72的深度D1的比率，换言之，相对于稍后将要形成的凸块4a的在与芯片3的主表面正交的方向上的厚度(凸块4a的高度D1)的比率小于10％。
例如，在形成以20μm节距排列的且高度为10μm的凸块4的情况下，金属膜74的膜厚度被设定为0.2μm。因此，即使在形成有金属膜74时，也能够防止通孔72的开口变狭窄，因而在后续的步骤中能够把含有金属粒子的浆料50充分地填充到通孔72中。
结果，金属膜74的膜厚度d1相对于凹槽73的深度D2的比率，换言之，相对于稍后将要形成的侧壁部5a的在与芯片3的主表面正交的方向上的厚度(侧壁部5a的高度D2)的比率小于10％。
接着，如图9所示，把含有Au粒子的浆料50填充到形成于光致抗蚀剂层71中的通孔72和凹槽73内，例如，所述Au粒子的纯度为99.9重量％以上且粒子直径为0.005μm至1.0μm。
然后，将浆料50干燥并且进行烧结，然后通过使用剥离溶液等的剥蚀法将光致抗蚀剂层71剥离。因此，如图10所示，在连接焊盘31的表面上依次层叠了Au的金属膜32、Au的金属膜42及含有粒子直径为0.005μm至1.0μm的Au粒子的多孔质金属层41，于是也就完成了其中在多孔质金属层41的侧表面上也形成有Au的金属膜42的凸块4a。
同时，以包围形成有凸块4a的区域的方式依次层叠了Au的金属膜32、Au的金属膜52及含有粒子直径为0.005μm至1.0μm的Au粒子的多孔质金属层51，于是也就完成了其中在多孔质金属层51的侧表面上也形成有Au的金属膜52的侧壁部5a。
如上所述，凸块4a包括设置于多孔质金属层41与连接焊盘31上的金属膜22之间的金属膜42，该金属膜42的膜厚度相对于凸块4a的高度D1的比率小于10％。此外，凸块4a还包括设置于多孔质金属层41的侧表面上的金属膜42。
另外，侧壁部5a包括设置于多孔质金属层51与连接焊盘31上的金属膜32之间的金属膜52，该金属膜52的膜厚度相对于侧壁部5a的高度D2的比率小于10％。此外，侧壁部5a还包括设置于多孔质金属层51的侧表面上的金属膜52。
为了防止在光致抗蚀剂层71中予以图案化的凸块4a和侧壁部5a的微细结构发生崩塌而把金属膜42、52形成在光致抗蚀剂层71的上表面、光致抗蚀剂层71中所形成的通孔72和凹槽73的侧面、以及金属膜22的表面上。因此，与半导体基板2侧的凸块4类似地，凸块4a可以具有使节距为20μm以下的精细化节距。
在上述实施方案中，已经说明了将未设置有凸块4a和侧壁部5a的芯片3安装到设置有凸块4和侧壁部5的半导体基板2上的情况，以及将设置有凸块4a和侧壁部5a的芯片3安装到未设置有凸块4和侧壁部5的半导体基板2上的情况，但这些都仅仅是示例。
根据本发明的电子器件亦可以具有如下这样的构造：其中，把设置有凸块4a和侧壁部5a的芯片3安装到设置有凸块4和侧壁部5的半导体基板2上。在这种构造的情况下，将金属膜42、52的膜厚度相对于凸块4、4a及侧壁部5、5a的在与半导体基板2及芯片3的主表面正交的方向上的一半厚度的比率设定为小于10％，优选地设定为小于5％。
另外，在上述实施方案中，已经说明了芯片3的基底材料是除Si之外的基底材料的情况，但是只要芯片3的基底材料的热膨胀系数不同于半导体基板2的热膨胀系数，则芯片3的基底材料亦可以是掺杂有杂质的Si。
如上所述的包括半导体激光器的发光部的芯片3和包括用于半导体激光器的驱动电路的半导体基板2例如可以被安装到诸如ToF(飞行时间：Time of flight)传感器或结构光(structured light)等测距装置上。例如，半导体激光器的发光部在安装到测距装置上时就起到ToF传感器的光源或结构光的光源的作用。
[3.效果]
电子器件1包括半导体基板2、芯片3、凸块4和侧壁部5。凸块4将设置于半导体基板2和芯片3的相互面对的主表面上的多个连接焊盘21和31彼此连接。侧壁部5包括环状地包围设置有多个凸块4的区域的多孔质金属层51，并且侧壁部5把半导体基板2和芯片3连接起来。藉此，电子器件1能够提高气密性。
芯片3的热膨胀系数与半导体基板2的热膨胀系数之间的差为0.1ppm/℃以上。藉此，即使当芯片3发热且以与半导体基板2的热膨胀系数不同的热膨胀系数膨胀时，由于侧壁部5的多孔质金属层51会弹性变形，因此电子器件1也能够抑制在侧壁部5中出现的裂纹和相对于侧壁部5而产生的间隙。此外，即使当芯片3或半导体基板2具有厚度不均或翘曲时，侧壁部5也会随着芯片3或半导体基板2的形状而弹性变形，因而能够提高气密性。
芯片3是半导体激光器。半导体基板2包括用于驱动半导体激光器的驱动电路。因此，即使当由于伴随着半导体激光器的发光而产生的热量使得芯片3以与半导体基板2的热膨胀系数不同的热膨胀系数膨胀时，侧壁部5的多孔质金属层51也会弹性变形，因而电子器件1能够提高气密性。
多孔质金属层51包含粒子直径为0.005μm至1.0μm的金属粒子。由于金属粒子的尺寸效果，多孔质金属层51可以在比块体状金属的熔点低的温度下进行金属接合。因此，在电子器件1中，在设置有连接焊盘21和31及凸块4的区域的周缘部处，利用可以在相对较低的温度下进行金属接合的多孔质金属层51将半导体基板2和芯片3连接起来，藉此，因为减少了由热引起的损坏，所以能够提高气密性。
侧壁部5包括金属膜52。所述金属膜52被设置在：多孔质金属层51与设置于半导体基板2上的连接焊盘21之间和/或多孔质金属层51与设置于芯片3上的连接焊盘31之间；以及多孔质金属层51的侧表面上。藉此，利用设置于多孔质金属层51的侧表面上的金属膜52来防止该多孔质金属层51的崩塌，电子器件1就能够提高气密性。
被设置在多孔质金属层51与设置于半导体基板2上的连接焊盘21之间和/或多孔质金属层51与设置于芯片3上的连接焊盘31之间的金属膜52的膜厚度相对于侧壁部5、5a的在与主表面正交的方向上的厚度的比率小于10％。藉此，能够防止用于形成在光致抗蚀剂层61、71中予以图案化的侧壁部5、5a的凹槽63、73由于金属膜52的形成而变狭窄。结果，在光致抗蚀剂层61、71中予以图案化的凹槽63、73内，可以适当地填充含有作为侧壁部5、5a的材料的金属粒子的浆料50。
被设置在多孔质金属层51与设置于半导体基板2上的连接焊盘21之间和/或多孔质金属层51与设置于芯片3上的连接焊盘31之间的金属膜52的膜厚度相对于侧壁部5、5a的在与主表面正交的方向上的一半厚度的比率小于10％。藉此，在通过侧壁部5、5a将半导体基板2和芯片3连接起来的电子器件的情况下，能够防止用于形成在光致抗蚀剂层71、71中予以图案化的侧壁部5、5a的凹槽63、73由于金属膜52的形成而变狭窄。结果，在光致抗蚀剂层61、71中予以图案化的凹槽63、73内，可以适当地填充含有作为侧壁部5、5a的材料的金属粒子的浆料50。
凸块4、4a具有多孔质金属层41和金属膜42。多孔质金属层41由与侧壁部5、5a的多孔质金属层51相同的材料形成。金属膜42被设置在：多孔质金属层41与设置于半导体基板2上的连接焊盘21之间和/或多孔质金属层41与设置于芯片3上的连接焊盘31之间；以及多孔质金属层41的侧表面上。藉此，因为可以同时形成凸块4、4a以及侧壁部5、5a，所以，无需为了接合和密封而增加新步骤，而是可以通过形成侧壁部5、5a来将半导体基板2和芯片3接合且密封。
被设置在多孔质金属层41与连接焊盘21、31之间的金属膜42的膜厚度相对于凸块4、4a的在与半导体基板2的主表面正交的方向上的厚度的比率小于10％。因此，能够防止用于形成在光致抗蚀剂层61、71中予以图案化的凸块4、4a的通孔62、72由于金属膜42的形成而变狭窄。因此，在光致抗蚀剂层61和71中予以图案化的通孔62、72内，可以适当地填充含有作为凸块4、4a的材料的金属粒子的浆料50。
被设置在多孔质金属层41与连接焊盘21、31之间的金属膜42的膜厚度相对于凸块4、4a的在与半导体基板2的主表面正交的方向上的一半厚度的比率小于10％。因此，在通过凸块4、4a将半导体基板2和芯片3连接起来的电子器件的情况下，可以防止用于形成在光致抗蚀剂层61、71中予以图案化的凸块4、4a的通孔62、72由于金属膜42的形成而变狭窄。结果，在光致抗蚀剂层61、71中予以图案化的通孔62、72内，可以适当地填充含有作为凸块4、4a的材料的金属粒子的浆料50。
多孔质金属层41、51以及金属膜42、43的材料是同一种类的金属。藉此，能够提高多孔质金属层41、51与金属膜42、43之间的接合强度。
多孔质金属层41、51的材料是包括纯度为99.9重量％以上的金、银、铂或铜的多孔质金属。因此，能够将半导体基板2的连接焊盘21和芯片3的连接焊盘31之间的连接电阻抑制为较低值。
注意，本说明书中记载的效果仅仅是示例，而不是限制性的，并且可以有其他效果。
注意，本技术还可以具有以下技术方案。
(1)一种电子器件，包括：
半导体基板；
芯片；
凸块，所述凸块将设置于所述半导体基板和所述芯片的相互面对的主表面上的多个连接焊盘彼此连接；以及
侧壁部，所述侧壁部包括多孔质金属层，所述多孔质金属层环状地包围设置有多个所述凸块的区域，并且所述侧壁部将所述半导体基板和所述芯片连接起来。
(2)根据(1)所述的电子器件，其中，
所述芯片的热膨胀系数与所述半导体基板的热膨胀系数之间的差为0.1ppm/℃以上。
(3)根据(1)或(2)所述的电子器件，其中，
所述芯片是半导体激光器，并且
所述半导体基板包括用于驱动所述半导体激光器的驱动电路。
(4)根据(1)至(3)中任一项所述的电子器件，其中，
所述多孔质金属层包含粒子直径为0.005μm至1.0μm的金属粒子。
(5)根据(1)至(4)中任一项所述的电子器件，其中，
所述侧壁部包括金属膜，所述金属膜被设置在：所述多孔质金属层与设置于所述半导体基板上的所述连接焊盘之间和/或所述多孔质金属层与设置于所述芯片上的所述连接焊盘之间；以及所述多孔质金属层的侧表面上。
(6)根据(5)所述的电子器件，其中，
被设置在所述多孔质金属层与设置于所述半导体基板上的所述连接焊盘之间和/或所述多孔质金属层与设置于所述芯片上的所述连接焊盘之间的所述金属膜的膜厚度相对于所述侧壁部的在与所述主表面正交的方向上的厚度的比率小于10％。
(7)根据(5)所述的电子器件，其中，
被设置在所述多孔质金属层与设置于所述半导体基板上的所述连接焊盘之间和/或所述多孔质金属层与设置于所述芯片上的所述连接焊盘之间的所述金属膜的膜厚度相对于所述侧壁部的在与所述主表面正交的方向上的一半厚度的比率小于10％。
(8)根据(1)至(7)中任一项所述的电子器件，其中，所述凸块包括：
由与所述侧壁部的所述多孔质金属层相同的材料形成的多孔质金属层；和
金属膜，所述金属膜被设置在：所述多孔质金属层与设置于所述半导体基板上的所述连接焊盘之间和/或所述多孔质金属层与设置于所述片上的所述连接焊盘之间；以及所述多孔质金属层的侧表面上。
(9)根据(8)所述的电子器件，其中，
被设置在所述多孔质金属层与所述连接焊盘之间的所述金属膜的膜厚度相对于所述凸块的在与所述主表面正交的方向上的厚度的比率小于10％。
(10)根据(8)所述的电子器件，其中，
被设置在所述多孔质金属层与所述连接焊盘之间的所述金属膜的膜厚度相对于所述凸块的在与所述主表面正交的方向上的一半厚度的比率小于10％。
(11)根据(5)至(10)中任一项所述的电子器件，其中，
所述多孔质金属层和所述金属膜的材料是同一种类的金属。
(12)根据(1)至(11)中任一项所述的电子器件，其中，
所述多孔质金属层的材料是含有纯度为99.9重量％以上的金、银、铂或铜的多孔质金属。
附图标记说明
1：电子器件
2：半导体基板
3：芯片
4、4a：凸块
5、5a：侧壁部
50：浆料
21、31：连接焊盘
41、51：多孔质金属层
22、32、42、52、64、74：金属膜
61、71：光致抗蚀剂层
62、72：通孔
63、73：凹槽

Claims (12)

1.一种电子器件，包括：
半导体基板；
芯片；
凸块，所述凸块将设置于所述半导体基板和所述芯片的相互面对的主表面上的多个连接焊盘彼此连接；以及
侧壁部，所述侧壁部包括多孔质金属层，所述多孔质金属层环状地包围设置有多个所述凸块的区域，并且所述侧壁部将所述半导体基板和所述芯片连接起来。
2.根据权利要求1所述的电子器件，其中，
所述芯片的热膨胀系数与所述半导体基板的热膨胀系数之间的差为0.1ppm/℃以上。
3.根据权利要求1所述的电子器件，其中，
所述芯片是半导体激光器，并且
所述半导体基板包括用于驱动所述半导体激光器的驱动电路。
4.根据权利要求1所述的电子器件，其中，
所述多孔质金属层包含粒子直径为0.005μm至1.0μm的金属粒子。
5.根据权利要求1所述的电子器件，其中，
所述侧壁部包括金属膜，所述金属膜被设置在：所述多孔质金属层与设置于所述半导体基板上的所述连接焊盘之间和/或所述多孔质金属层与设置于所述芯片上的所述连接焊盘之间；以及所述多孔质金属层的侧表面上。
6.根据权利要求5所述的电子器件，其中，
被设置在所述多孔质金属层与设置于所述半导体基板上的所述连接焊盘之间和/或所述多孔质金属层与设置于所述芯片上的所述连接焊盘之间的所述金属膜的膜厚度相对于所述侧壁部的在与所述主表面正交的方向上的厚度的比率小于10％。
7.根据权利要求5所述的电子器件，其中，
被设置在所述多孔质金属层与设置于所述半导体基板上的所述连接焊盘之间和/或所述多孔质金属层与设置于所述芯片上的所述连接焊盘之间的所述金属膜的膜厚度相对于所述侧壁部的在与所述主表面正交的方向上的一半厚度的比率小于10％。
8.根据权利要求1所述的电子器件，其中，所述凸块包括：
由与所述侧壁部的所述多孔质金属层相同的材料形成的多孔质金属层；和
金属膜，所述金属膜被设置在：所述多孔质金属层与设置于所述半导体基板上的所述连接焊盘之间和/或所述多孔质金属层与设置于所述芯片上的所述连接焊盘之间；以及所述多孔质金属层的侧表面上。
9.根据权利要求8所述的电子器件，其中，
被设置在所述多孔质金属层与所述连接焊盘之间的所述金属膜的膜厚度相对于所述凸块的在与所述主表面正交的方向上的厚度的比率小于10％。
10.根据权利要求8所述的电子器件，其中，
被设置在所述多孔质金属层与所述连接焊盘之间的所述金属膜的膜厚度相对于所述凸块的在与所述主表面正交的方向上的一半厚度的比率小于10％。
11.根据权利要求5所述的电子器件，其中，
所述多孔质金属层和所述金属膜的材料是同一种类的金属。
12.根据权利要求1所述的电子器件，其中，
所述多孔质金属层的材料是含有纯度为99.9重量％以上的金、银、铂或铜的多孔质金属。
CN202280009141.2A 2021-02-19 2022-01-28 电子器件 Pending CN116711056A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021-025311 2021-02-19
JP2021025311 2021-02-19
PCT/JP2022/003199 WO2022176563A1 (ja) 2021-02-19 2022-01-28 電子機器

Publications (1)

Publication Number Publication Date
CN116711056A true CN116711056A (zh) 2023-09-05

Family

ID=82931539

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202280009141.2A Pending CN116711056A (zh) 2021-02-19 2022-01-28 电子器件

Country Status (7)

Country Link
US (1) US20240113066A1 (zh)
EP (1) EP4297071A1 (zh)
JP (1) JPWO2022176563A1 (zh)
KR (1) KR20230147601A (zh)
CN (1) CN116711056A (zh)
TW (1) TW202247360A (zh)
WO (1) WO2022176563A1 (zh)

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637143A (ja) * 1992-07-15 1994-02-10 Toshiba Corp 半導体装置および半導体装置の製造方法
JPH11168116A (ja) * 1997-12-04 1999-06-22 Mitsui High Tec Inc 半導体チップ用電極バンプ
JP2000077458A (ja) * 1998-08-31 2000-03-14 Matsushita Electric Works Ltd フリップチップ実装方法
JP3827569B2 (ja) * 2001-12-06 2006-09-27 旭化成エレクトロニクス株式会社 微細パターン接続用回路部品およびその形成方法
JP3905041B2 (ja) 2003-01-07 2007-04-18 株式会社日立製作所 電子デバイスおよびその製造方法
JP5320165B2 (ja) * 2009-05-27 2013-10-23 パナソニック株式会社 半導体装置
JP5416153B2 (ja) * 2010-03-18 2014-02-12 古河電気工業株式会社 導電性ペースト、及びその製造方法、並びに導電接続部材
US10177079B2 (en) * 2010-03-19 2019-01-08 Furukawa Electric Co., Ltd. Conductive connecting member and manufacturing method of same
JP2013098514A (ja) * 2011-11-07 2013-05-20 Seiko Epson Corp 半導体装置の製造方法及び半導体装置、電子機器
JP5924235B2 (ja) * 2012-10-30 2016-05-25 株式会社ソシオネクスト 半導体装置およびその製造方法
TWI662657B (zh) * 2015-04-07 2019-06-11 聯華電子股份有限公司 半導體元件的堆疊結構
JP2018160589A (ja) * 2017-03-23 2018-10-11 富士通株式会社 電子装置、及び電子装置の製造方法
WO2020162142A1 (ja) * 2019-02-05 2020-08-13 ソニー株式会社 発光素子組立体、マルチビームレーザチップ組立体及び光造形装置、並びに、部材組立体及びその製造方法

Also Published As

Publication number Publication date
JPWO2022176563A1 (zh) 2022-08-25
EP4297071A1 (en) 2023-12-27
WO2022176563A1 (ja) 2022-08-25
TW202247360A (zh) 2022-12-01
US20240113066A1 (en) 2024-04-04
KR20230147601A (ko) 2023-10-23

Similar Documents

Publication Publication Date Title
TWI277187B (en) Semiconductor device and manufacturing method for the same
KR100750741B1 (ko) 캡 웨이퍼, 이를 구비한 반도체 칩, 및 그 제조방법
US7763985B2 (en) Flip-chip type semiconductor device
US8853865B2 (en) Semiconductor device with overlapped lead terminals
KR100917745B1 (ko) 반도체 장치 및 그 제조 방법
US20110147788A1 (en) Semiconductor device with a light emitting semiconductor die
WO2019124024A1 (ja) 半導体パッケージおよびその製造方法
JP2003060118A (ja) 半導体装置の製造方法
KR20230010170A (ko) 반도체 장비 및 제조방법
US8179686B2 (en) Mounted structural body and method of manufacturing the same
JP4626445B2 (ja) 半導体パッケージの製造方法
JP4637761B2 (ja) 半導体装置およびその製造方法
JP2006351950A (ja) 半導体装置及び半導体装置の製造方法
CN116711056A (zh) 电子器件
US20040266058A1 (en) Method for fabricating a packaging device for semiconductor die and semiconductor device incorporating same
US20040262738A1 (en) Packaging device for semiconductor die, semiconductor device incorporating same and method of making same
WO2024029255A1 (ja) 電子機器
JP2011049354A (ja) 電子装置
US20240038706A1 (en) Electronic device
US6956291B1 (en) Apparatus and method for forming solder seals for semiconductor flip chip packages
KR100503277B1 (ko) 플립칩 패키지 형성 방법
JP4416618B2 (ja) 半導体装置実装体及びその製造方法
JP3525808B2 (ja) 半導体装置の製造方法および半導体装置
JP2883458B2 (ja) 混成集積回路用配線板の製造方法
TW488002B (en) Method of making a flip chip with an isolation protecting layer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination