TWI458140B - 發光裝置封裝元件 - Google Patents

發光裝置封裝元件 Download PDF

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TWI458140B
TWI458140B TW099124277A TW99124277A TWI458140B TW I458140 B TWI458140 B TW I458140B TW 099124277 A TW099124277 A TW 099124277A TW 99124277 A TW99124277 A TW 99124277A TW I458140 B TWI458140 B TW I458140B
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connection pad
wafer
carrier wafer
illuminating device
package component
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TW201131829A (en
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Chung Yu Wang
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Taiwan Semiconductor Mfg
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    • HELECTRICITY
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    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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    • H01L33/64Heat extraction or cooling elements
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/45001Core members of the connector
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
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    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/49105Connecting at different heights
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    • H01L2224/732Location after the connecting process
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    • H01L2224/73265Layer and wire connectors
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    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED

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Description

發光裝置封裝元件
本發明係有關於發光裝置(LED)封裝元件,且特別是有關於一種含基材通孔(though-substrate via;TSV)之LED封裝結構。
近年來,如發光二極體(light-emitting diodes;LED)、雷射二極體及紫外光光學偵測器等光學裝置已被廣泛使用。III族之氮化物,例如氮化鎵(GaN)及其相關合金,已證實適用於形成上述光學裝置。III族之氮化物具有高能帶間隙及高電子飽和速率,亦使其成為高溫與高速之功率電子裝置應用中之極佳選擇。
由於一般成長溫度下之氮的高平衡壓力,因此不容易得到氮化鎵之塊狀結晶。因此,氮化鎵膜層與各別之發光二極體通常形成於能符合氮化鎵特性之其他基材上。藍寶石(sapphire;Al2 O3 )為常用之基材材料。第1圖顯示發光裝置(LED)封裝元件之剖面圖。發光裝置2包含多層形成於藍寶石基材4上之以氮化鎵為主(GaN-based)的膜層。藍寶石基材4更裝設於導線架(lead frame)6上。電極8、10透過金線12使發光裝置2電性連接至導線架6。
然而,經觀察,藍寶石具有低的熱傳導率(thermal conductivity)。因此,由發光裝置2所產生的熱能無法有效地透過藍寶石基板4逸散。反而,熱能需要透過發光裝置2的頂端及金線12散出。然而,既然金線12必需延伸至導線架6而長度較長,透過金線12的散熱效率亦不佳。此外,電極10佔據了晶片區域,而導致發光裝置的光輸出區域未能最佳化。
本發明提供一種發光裝置封裝元件,包括:一發光裝置晶片;以及一承載晶片,包含:一第一連接墊及一第二連接墊,位於此承載晶片之一表面上且以覆晶接合方式與此發光裝置晶片接合;一第三連接墊及一第四連接墊,位於此承載晶片之此表面上且各自與此第一連接墊及此第二連接墊電性連接;及至少一基材通孔(TSV),連接至此第一及此第二連接墊。
本發明更提供一種發光裝置封裝元件,包括:一散熱器;一導線架,位於此散熱器上,且熱耦接(thermally coupled)此散熱器;一承載晶片,位於此導線架上,其中此承載晶片包含複數個虛置基材通孔於其中;一第一熱界面材料,位於此承載晶片及此導線架之間,其中此第一熱界面材料使此導線架電性絕緣於此承載晶片中所有的虛置基材通孔;一第一連接墊及一第二連接墊,位於此承載晶片之一表面上,其中此第一連接墊及此第二連接墊打線連接至此導線架;以及一發光裝置晶片,以覆晶接合方式接合於此承載晶片上,其中此發光裝置晶片之兩電極電性連接至此第一連接墊及此第二連接墊。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:
本發明接下來將會提供許多不同的實施例以說明本發明中不同的特徵。各特定實施例中的構成及配置將會在以下作詳細說明以闡述本發明之精神,但這些實施例並非用於限定本發明。
本發明在此揭示一種新穎的發光裝置(light-emitting device;LED)封裝元件及其製造方法,並將舉例本發明實施例之製造中間過程,也將討論這些實施例之變化。在本發明各種舉例之圖示及實施例中,相似元件符號表示為相似元件。
第2圖顯示為晶圓100,其包含形成於基材20上之發光裝置22。在一實施例中,基材20由藍寶石(透明的Al2 O3 )形成,或者,亦可由其他性質與發光裝置22所使用之膜層(包含III族、V族元素或亦稱為III-V化合物半導體材料)相近的材料形成。基材20亦可為碳化矽基材、覆有碳化矽層之矽基材、矽鍺基材或其他可適用之半導體基材。
在本實施例中,未摻雜之氮化鎵(u-GaN;un-doped GaN)層24形成於基材20上,且可能與其接觸。在一實施例中,未摻雜之氮化鎵層24實質上無氮及鎵以外的其他元素存在。發光裝置22形成於未摻雜之氮化鎵層24上,且可能與其接觸。在本實施例中,每個發光裝置22皆包含n型氮化鎵層(摻雜n型雜質之氮化鎵)26、多重量子井(multiple quantum well;MQW)28、p型氮化鎵層(摻雜p型雜質之氮化鎵)、反射板(reflector)30及頂部電極(亦為連接墊)34。反射板32可由例如金屬形成。多重量子井28可由例如氮化銦鎵(InGaN)形成,並用以作為發光之主動層。上述膜層26、28、30、32、34之形成乃習知技術,故在此不重複贅述。在本實施例中,膜層26、28、30之形成方法包含磊晶成長。可以理解的是,發光裝置22可具有多種設計型態,第2圖僅顯示所有可得之變化例中之其中一種示範例。例如,膜層26、28及30的材料皆可不同於前述的材料,且可包含三元的(ternary)III-V化合物半導體材料,例如GaAsP、GaPN、AlInGaAs、GaAsPN、AlGaAs或其類似物。並且,n型氮化鎵層26及p型氮化鎵層28的位置可作替換。
每個發光裝置22皆更包含連接墊(bond pads)38,用以連接n型氮化鎵層26。因此,連接墊34及38用於施予電壓至各別的發光裝置22,使各別的發光裝置22激發放光。在一實施例中,在發光裝置22運作(發光)時,每個發光裝置22中至少一電極34有電流流經,但亦有一或多個電極34為虛置電極,其在施予電壓時不會有電流流經。
焊料凸塊36(包含主動焊料凸塊36B及虛置焊料凸塊36A)、40形成於發光裝置22上。焊料凸塊36及40可使用常用之焊料,例如無鉛焊料、共晶焊料(eutectic solders)或其類似物。在形成焊料凸塊36及40後,將晶圓100分割成複數個發光裝置晶片(LED chip)44,其中每個發光裝置晶片44皆含有一或多個發光裝置22。
在此實施例中,每個發光裝置晶片44含有多個設置於同一基材20上之發光裝置,這些在同一發光裝置晶片中的發光裝置22稱為LED顯示單元(LED tiles)。自晶圓100分割出發光裝置晶片44後,可在發光裝置晶片44的邊緣形成切割斜角(bevel cuts)(未顯示於第2圖中,請參見第4圖),以使邊緣與其所相對之基材20表面形成斜角(slant angle,不等於90°)。切割斜角42可減少所形成之封裝結構的應力。
參見第3圖,提供承載基材60。承載基材60包含基材62,其可為半導體基材,例如矽基材或介電基材。基材通孔(through-substrate via;TSV)64形成於基材62中,且電性連接位於基材62相反側之元件。基材通孔64可由銅或其他金屬形成,例如鎢或前述之合金。連接墊66(包含66A、66B及66C)形成在承載基材60之一側上並與基材通孔64相連。
雖然可對基材通孔64施予電壓,基材通孔64為虛置基材通孔,非用以導電。在本說明書中,既然虛置基材通孔係用於散熱,則虛置基材通孔64亦可稱為熱基材通孔(thermal TSVs)。同樣地,各別之發光裝置晶片44發光時(在發光裝置晶片44接合該承載晶片上後),有電流流經之連接墊66稱為主動連接墊66B或66C,無電流流經之連接墊稱為虛置連接墊66A。歐姆線68可視需要埋設在承載晶圓60中。歐姆線68可相互連接各個連接墊,以使連接墊可用於調整(regualte)電流流經將要接合在承載晶圓60上之發光裝置晶片44。或者,不形成歐姆線,以電阻極小的金屬線取代之。
參見第4圖,自晶圓100分割出來之多個發光裝置晶片44以覆晶接合方式接合至承載晶圓60上。在接合製程中,回銲焊料凸塊36及40以連接(join)連接墊34及38。可視需要填充底部填膠72至發光裝置晶片44及承載晶圓60之間的空隙中。切割斜角42可減少填入底部填膠72之困難度。
在發光裝置晶片44接合至承載晶圓60之後,發光晶片裝置44可覆蓋(垂直重疊)主動連接墊66B。然而,發光裝置晶片44未覆蓋連接墊66C。換句話說,連接墊66C位在發光裝置晶片44垂直延伸的邊界之外,且未被底部填膠所覆蓋(如有填充)。
參見第5圖,將矽膠透鏡(silicone lenses)塑模(mold)於發光裝置晶片44上。矽膠透鏡74的塑模為習知技術,故在此不重複贅述。每個矽膠透鏡74皆可覆蓋所對應之發光裝置晶片44。在未填充底部填膠72之實施例中,亦可將矽膠(silicone)填充至發光裝置晶片44及承載晶圓60之間的空隙中,發揮與底部填膠相同的功能。連接墊66C係為暴露的,未被矽膠透鏡74所覆蓋。
接著,可沿著切割道63(scribe line)分割承載晶圓60,以使發光裝置封裝元件分離成多個獨立的封裝體。因此,承載晶圓60分離成多個承載晶片60’,且每個承載晶片60’與至少一發光裝置晶片44接合。
如第5圖所示,此封裝體結構包含可用於打線連接的連接墊66C。第6圖顯示已進行打線連接後之封裝體之實施例,其中如第5圖所示之封裝元件更可裝設於導線架上。連接墊66C可透過導線80連接至導線架78。因此,發光裝置晶片44透過導線80電性連接至導線架78。導線80可為金線,或由其他金屬材料形成,例如銀、鋁及其類似物。
承載晶片60’可藉由熱界面材料(thermal interface material;TIM)層79與導線架78黏接。熱界面材料層79可有具有良好導熱能力之介電材料形成。在本實施中,熱界面材料層79之熱傳導係數可大於33 W/mK,且可介於33W/mK至318 W/mK之間。在一實施例中,熱界面材料79係由有機膏體(organic paste)或純的合金或金屬形成,其可填入至導線架78中,並在承載晶片60’設置於導線架78後,加熱回銲及固化。
第6圖更顯示將封裝元件裝設至散熱器(heat sink)82上。在一實施例中,熱界面材料86連接散熱器82及導線架78,熱界面材料86可使用近似於熱界面材料層79之材料。散熱器82可包含內部空氣通道(internal air ducts)84以增加散熱器82之散熱面積。再者,散熱器82可用於支撐設置於其上之封裝元件,並可電性絕緣於電流輸入/輸出單元(current I/Os)。因此,由發光裝置晶片44所產生的熱可發散至承載晶片60’,及發散至散熱器82。可以看出的是,發光裝置晶片44至散熱器82的通道中,無導熱能力不佳的材料存在。因此,在發光裝置晶片44及散熱器82之間的熱阻(thermal resistance)低,使得第6圖所示之封裝元件具有高散熱效率。上述封裝元件因而適於應用於高功率發光裝置,其散熱效果對於裝置發揮最佳效果極為重要。
經發現,當電壓施予至線80及連接墊66C時,虛置焊料凸塊36A無任何電流流經。然而,虛置焊料凸塊36A可幫助傳導發光裝置晶片44所產生的熱通過承載晶片60’至散熱器82。
如第6圖所示之封裝元件可稱為混合式封裝元件。既然發光裝置晶片44首先以覆晶接合方式接合在承載晶片60’上,且所形成之結構更接合至其他電路元件上,例如以導線連接至導線架。此封裝設計可使光僅朝一方向發出(如第6圖之頂部),而熱由相反方向逸散(如第6圖之底部)。因此,如本發明各種實施例所述之發光裝置封裝元件具有良好的發光效率及散熱效率,且優於傳統發光裝置封裝體,該傳統發光裝置封裝體的散熱器中為導熱性差的材料。例如,由發光裝置晶片44所產生的熱可由多個虛置焊料凸塊36A及熱基材通孔64發散至承載晶片60’中。因此,如第6圖所示之發光裝置封裝元件散熱能力得以改善。此外,由發光裝置晶片44所發出的光自基材20發出(本實施例中基材20係為透明的),且不會被任何線或連接墊所阻擋。因此,相較於部分的光會被封裝體元件所阻擋之傳統發光裝置封裝體,光輸出效率得以改善。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作更動、替代與潤飾。再者,本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟,任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟,只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此,本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外,每一申請專利範圍構成個別的實施例,且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
2...發光裝置
4...藍寶石基材
6...導線架
8、10...電極
12...金線
20...基材
22...發光裝置
24...未摻雜之氮化鎵層
26...n型氮化鎵層
28...多重量子井
30...p型氮化鎵層
32...反射板
34...頂部電極
36、40...焊料凸塊
36A...虛置焊料凸塊
36B...主動焊料凸塊
38...連接墊
42...切割斜角
44...發光裝置晶片
60、60’...承載晶圓
62...基材
63...切割道
64...基材通孔
66...連接墊
66A...虛置連接墊
66B、66C...主動連接墊
68...歐姆線
72...底部填膠
74...矽膠透鏡
78...導線架
79...熱界面材料層
80...導線
82...散熱器
84...內部空氣通道
86...熱界面材料
100...晶圓
第1圖顯示形成於藍寶石基材上之傳統發光裝置之剖面圖。
第2至6圖顯示依照本發明之一實施例之含發光裝置之封裝元件於各種中間製造階段之剖面圖。
36、40...焊料凸塊
36A...虛置焊料凸塊
36B...主動焊料凸塊
38...連接墊
42...切割斜角
44...發光裝置晶片
60’...承載晶圓
62...基材
64...基材通孔
66...連接墊
66A...虛置連接墊
66B、66C...主動連接墊
64...基材通孔
66...連接墊
66A...虛置連接墊
66B、66C...主動連接墊
74...矽膠透鏡
78...導線架
79...熱界面材料層
80...導線
82...散熱器
84...內部空氣通道
86...熱界面材料

Claims (10)

  1. 一種發光裝置封裝元件,包括:一發光裝置晶片;以及一承載晶片,包含:一第一連接墊及一第二連接墊,位於該承載晶片之一表面上且以覆晶接合方式與該發光裝置晶片接合;一第三連接墊及一第四連接墊,位於該承載晶片之該表面上且各自與該第一連接墊及該第二連接墊電性連接;及至少一基材通孔(TSV),連接至該第一及該第二連接墊。
  2. 如申請專利範圍第1項所述之發光裝置封裝元件,更包含一透鏡,覆蓋該發光裝置晶片及一部份的該承載基材,且未覆蓋該第三連接墊及該第四連接墊。
  3. 如申請專利範圍第1項所述之發光裝置封裝元件,更包含一第一連接線及一第二連接線,各自打線連接該第一連接墊及第二連接墊至該第三連接墊及該第四連接墊。
  4. 如申請專利範圍第3項所述之發光裝置封裝元件,更包含:一導線架,連接至該第一連接線及該第二連接線;及一熱界面材料(TIM),位於該承載晶片及該導線架之間並將其連接,其中該熱界面材料使該導線架電性絕緣於該承載晶片中所有的基材通孔。
  5. 如申請專利範圍第1項所述之發光裝置封裝元件,更包含一散熱器連接至該承載晶片上,其中該散熱器及該發光裝置晶片位於該承載晶片之相反側。
  6. 如申請專利範圍第1項所述之發光裝置封裝元件,更包含:一虛置基材通孔,位於該承載晶片中;及一虛置焊料凸塊,電性連接該虛置基材通孔及該發光裝置晶片;其中該虛置基材通孔包含一連接至該虛置焊料凸塊之第一終端,及一電性絕緣之第二終端。
  7. 如申請專利範圍第1項所述之發光裝置封裝元件,其中該承載晶片包含一歐姆線,電性耦接該第一連接墊及該第三連接墊。
  8. 一種發光裝置封裝元件,包括:一散熱器;一導線架,位於該散熱器上,且熱耦接(thermally coupled)該散熱器;一承載晶片,位於該導線架上,其中該承載晶片包含複數個虛置基材通孔於其中;一第一熱界面材料,位於該承載晶片及該導線架之間,其中該第一熱界面材料使該導線架電性絕緣於該承載晶片中所有的虛置基材通孔;一第一連接墊及一第二連接墊,位於該承載晶片之一表面上,其中該第一連接墊及該第二連接墊打線連接至該導線架;以及一發光裝置晶片,以覆晶接合方式接合於該承載晶片上,其中該發光裝置晶片之兩電極電性連接至該第一連接墊及該第二連接墊。
  9. 申請專利範圍第8項所述之發光裝置封裝元件,其中該散熱器內部包含空氣通道。
  10. 申請專利範圍第8項所述之發光裝置封裝元件,其中在發光裝置晶片激發發放光時,該承載晶片中之複數個虛置通孔未有電流流經,且其中該複數個虛置基材通孔透過虛置焊料凸塊與該發光裝置晶片上的電極接合。
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Families Citing this family (7)

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Publication number Priority date Publication date Assignee Title
KR101630152B1 (ko) * 2010-02-24 2016-06-14 엘지디스플레이 주식회사 하이브리드 발광다이오드 칩과 이를 포함하는 발광다이오드 소자 및 이의 제조방법
TW201225246A (en) * 2010-12-06 2012-06-16 Ind Tech Res Inst Multi-chip stack structure
CN102800798B (zh) * 2011-10-26 2016-06-08 清华大学 一种led封装结构及其封装方法
CA2854771A1 (en) * 2013-06-21 2014-12-21 J2 Light Inc. Lighting system and method to control a lighting system
US9496297B2 (en) * 2013-12-05 2016-11-15 Optiz, Inc. Sensor package with cooling feature and method of making same
CN108091721A (zh) * 2017-12-11 2018-05-29 阜阳师范学院 一种用于硅基光电集成电路芯片中的光电探测器及制备方法
US11978839B2 (en) * 2019-02-03 2024-05-07 Quanzhou Sanan Semiconductor Technology Co., Ltd. Light-emitting device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030063442A1 (en) * 2000-05-16 2003-04-03 Mitsubishi Denki Kabushiki Kaisha Power module
US20070076391A1 (en) * 2005-10-04 2007-04-05 Shih-Ping Hsu Chip embedded packaging structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040188696A1 (en) * 2003-03-28 2004-09-30 Gelcore, Llc LED power package
US7329905B2 (en) * 2004-06-30 2008-02-12 Cree, Inc. Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices
TWI294694B (en) 2005-06-14 2008-03-11 Ind Tech Res Inst Led wafer-level chip scale packaging
US20090273002A1 (en) * 2008-05-05 2009-11-05 Wen-Chih Chiou LED Package Structure and Fabrication Method
US7989270B2 (en) * 2009-03-13 2011-08-02 Stats Chippac, Ltd. Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030063442A1 (en) * 2000-05-16 2003-04-03 Mitsubishi Denki Kabushiki Kaisha Power module
US20070076391A1 (en) * 2005-10-04 2007-04-05 Shih-Ping Hsu Chip embedded packaging structure

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