TW202215627A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW202215627A
TW202215627A TW110133261A TW110133261A TW202215627A TW 202215627 A TW202215627 A TW 202215627A TW 110133261 A TW110133261 A TW 110133261A TW 110133261 A TW110133261 A TW 110133261A TW 202215627 A TW202215627 A TW 202215627A
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Taiwan
Prior art keywords
pad
capacitor
relay
pads
wire
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TW110133261A
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English (en)
Inventor
齋藤鮎彦
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日商住友電工器件創新股份有限公司
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Publication of TW202215627A publication Critical patent/TW202215627A/zh

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Abstract

一實施形態之半導體裝置具備：半導體晶片，其具有設置於基板上之電晶體及汲極墊；電容器，其具有夾著介電質之上部電極及下部電極；焊墊；及空墊，其設置於半導體晶片之基板上。該半導體裝置進而具備：第1導線，其將焊墊及半導體晶片之汲極墊相互連接；第2導線，其將空墊及電容器之上部電極相互連接；及第3導線，其將焊墊及空墊相互連接。

Description

半導體裝置
本揭示係關於一種半導體裝置。 本申請案係主張基於2020年9月7日之日本申請案第2020-149904號之優先權，並援用上述日本申請案中記載之全部記載內容者。
專利文獻1中，記載有內部匹配型高輸出場效電晶體(內部匹配型FET(Field Effect Transistor：場效應電晶體))。內部匹配型FET具備配置於外圍器內之2個GaAsFET晶片、與輸出入匹配電路用之氧化鋁基板。內部匹配型FET具備輸入側之氧化鋁基板、與輸出側之氧化鋁基板。於輸入側之氧化鋁基板、及輸出側之氧化鋁基板之各者，設置有用以獲得阻抗匹配之匹配電路。 [先前技術文獻] [專利文獻]
專利文獻1：日本特開昭63-86904號公報
一形態之半導體裝置具備：半導體晶片，其具有設置於基板上之電晶體及電極墊；電容器，其具有夾著介電質之上部電極及下部電極；第1中繼墊；及第2中繼墊，其設置於半導體晶片之基板上。該半導體裝置進而具備：第1導線，其將第1中繼墊及半導體晶片之電極墊相互連接；第2導線，其將第2中繼墊及電容器之上部電極相互連接；及第3導線，其將第1中繼墊及第2中繼墊相互連接。
於先前之內部匹配型FET中，GaAsFET晶片與匹配電路藉由焊接線相互連接。然而，於高頻放大器中處理之信號之頻率較低之情形，有時謀求減少汲極墊等半導體晶片之電極墊所連接之導線之條數，且增加各導線之導線長度。於每1條導線之電流較大、且導線長度較長之情形，有致使導線熔斷之虞。
本揭示之目的在於提供一種可縮短連接於半導體晶片之電極墊之導線之半導體裝置。
[本揭示之實施形態之說明] 最初，列舉說明本揭示之實施形態之內容。一實施形態之半導體裝置，具備：半導體晶片，其具有設置於基板上之電晶體及電極墊；電容器，其具有夾著介電質之上部電極及下部電極；第1中繼墊；及第2中繼墊，其設置於半導體晶片之基板上。該半導體裝置進而具備：第1導線，其將第1中繼墊及半導體晶片之電極墊相互連接；第2導線，其將第2中繼墊及電容器之上部電極相互連接；及第3導線，其將第1中繼墊及第2中繼墊相互連接。
該半導體裝置中，半導體晶片於基板上具備電晶體及電極墊，電容器具備夾著介電質之上部電極及下部電極。第1導線將半導體晶片之電極墊與第1中繼墊相互連接。第3導線將第1中繼墊及第2中繼墊相互連接。第2導線將第2中繼墊與電容器之上部電極相互連接。因此，半導體晶片與電容器經由自半導體晶片延伸之第1導線、第1中繼墊、第3導線、半導體晶片上之第2中繼墊、及向電容器延伸之第2導線而相互連接。因此，藉由具備第1導線、第1中繼墊、第3導線、第2中繼墊、及第2導線，可將連接於半導體晶片之電極墊之導線僅作為第1導線。藉由經由第1中繼墊及第2中繼墊將各導線相互連接，可縮短各導線。
第1中繼墊亦可配置於電容器之介電質上之自上部電極離開之位置。第2中繼墊亦可沿半導體晶片之一邊配置。該情形時，可將第1中繼墊配置於電容器之介電質上，且可沿與電容器對向之半導體晶片之一邊配置第2中繼墊。
電極墊可沿半導體晶片之一邊配置。第2中繼墊可與電極墊相鄰配置。該情形時，可以沿與電容器對向之半導體晶片之一邊排列之方式，配置半導體晶片上之電極墊及第2中繼墊。
上述半導體裝置亦可具備沿電容器之一邊排列之複數個第1中繼墊、與沿半導體晶片之一邊排列之複數個第2中繼墊、及複數個電極墊。複數個第2中繼墊之各者亦可與電極墊相鄰配置。該情形時，可沿與半導體晶片對向之電容器之一邊排列複數個第1中繼墊，且沿與電容器對向之半導體晶片之一邊排列電極墊及第2中繼墊。
上述半導體裝置亦可具備複數條第1導線、及複數條第2導線，相互相鄰之複數條第1導線各者亦可連接於共通之第1中繼墊。相互相鄰之複數條第2導線之各者亦可連接於共通之第2中繼墊。該情形時，由於第1中繼墊及第2中繼墊之各者連接有複數條導線，故可將第1中繼墊及第2中繼墊更有效地作為導線之連接部利用。
上述半導體裝置亦可於電容器之介電質之背面具備設置於與第1中繼墊對向之區域以外之區域之背面電極。該情形，藉由不於第1中繼墊之背面設置背面電極，而可抑制第1中繼墊產生之寄生電容。
上述半導體裝置亦可於半導體晶片之背面、或基板之背面，具備設置於與第2中繼墊對向之區域以外之區域之背面電極。該情形時，藉由不於第2中繼墊之背面設置背面電極，可抑制第2中繼墊產生之寄生電容。
第1中繼墊亦可設置於電容器與半導體晶片之間。該情形時，可將第1中繼墊配置於自電容器及半導體晶片之兩者離開之部位。
基板可由碳化矽(SiC)、金剛石、或金屬構成。該情形時，可由放熱性較高之材料構成基板。
[本揭示之實施形態之詳細內容] 以下一面參照圖式一面說明本揭示之半導體裝置之具體例。另，本發明並非限定於下述之例示者，而是如申請專利範圍所示，意欲包含與申請專利範圍均等之範圍內之全部變更。於圖式之說明中，對相同或相當之要件附加相同之符號，且適當省略重複之說明。為容易理解，圖式將一部分簡化或誇大描述，尺寸比例等並非限定於圖式記載者。
圖1係顯示一實施形態之半導體裝置1之內部構成之圖。如圖1所示，半導體裝置1具備輸入端子2、輸出端子3、半導體晶片10、分支電路基板20、合成電路基板30、濾波器電路40、電容器50、及電容器60。半導體裝置1例如具備2個濾波器電路40、2個電容器50、60。
例如，半導體晶片10為包含2個放大元件11之放大元件部。作為一例，每1個放大元件11之輸出為30W，半導體晶片10整體之輸出為60W。半導體裝置1例如為具備封裝4之高頻放大器。封裝4收納半導體晶片10、分支電路基板20、合成電路基板30、濾波器電路40、及電容器50、60。
封裝4為金屬製，連接於基準電位。例如，封裝4之俯視形狀為長方形狀。封裝4具有於第1方向A1中相互對向之端壁4a、4b、與於第2方向A2中相互對向之側壁4c、4d。第1方向A1及第2方向A2相互交叉，且作為一例而相互正交。封裝4具有長方形狀之平坦之底板4e。
底板4e例如具有沿第1方向A1及第2方向A2之兩者延伸之平面。端壁4a、4b沿底板4e之一對邊(沿第2方向A2延伸之邊)直立設置。側壁4c、4d沿底板4e之另一對之邊(沿第1方向A1延伸之邊)直立設置。封裝4進而具有未圖示之蓋部。該蓋部密封由端壁4a、4b及側壁4c、4d形成之開口。
輸入端子2為金屬製之配線圖案，自半導體裝置1之外部輸入高頻信號。高頻信號例如為基於多載波傳送方式之信號，且重疊載波信號之頻率相互不同之複數個信號。載波信號之頻帶例如為500 MHz以下。輸入端子2設置於第2方向A2之端壁4a之中央部。輸入端子2自封裝4之外部延伸至內部。
例如，半導體晶片10配置於封裝4之底板4e上且包含第1方向A1中之封裝4之中央之區域。半導體晶片10之各放大元件11內置電晶體。電晶體為場效電晶體(FET)，作為一例，為高電子遷移率電晶體(HEMT：High Electron Mobility Transistor)。各放大元件11具有閘極墊、源極墊、及汲極墊。
例如，各放大元件11之輸入端子2側之一邊(端邊)交替排列有閘極墊(信號輸入端)及源極墊。各放大元件11之輸出端子3側之端邊排列有汲極墊(信號輸出端)。各源極墊經由貫通孔與封裝4之底板4e電性連接，成為基準電位。該貫通孔將放大元件11沿厚度方向(例如，與圖1之紙面正交之方向)貫通。各放大元件11放大被輸入至各閘極墊之高頻信號，且自各汲極墊輸出放大後之高頻信號。另，其後詳細說明放大元件11之汲極墊之周邊之構成。
分支電路基板20配置於封裝4之底板4e上。分支電路基板20沿第1方向A1與輸入端子2及半導體晶片10排列配置。分支電路基板20位於輸入端子2與半導體晶片10之間。分支電路基板20具有陶瓷製之基板21、與設置於基板21之主面上之分支電路22。例如，基板21之俯視形狀為長方形狀。
例如，分支電路基板20之一側之長邊21a與輸入端子2對向，且分支電路基板20之另一側之長邊21b介隔電容器50與半導體晶片10對向。基板21之背面與封裝4之底板4e對向。基板21之一側之短邊21c與封裝4之側壁4c對向，且基板21之另一側之短邊21d與封裝4之側壁4d對向。
分支電路22包含設置於基板21之主面上之配線圖案23。配線圖案23經由焊接線9a與輸入端子2電性連接。高頻信號自第2方向A2之輸入端子2之中央部經由焊接線9a輸入至配線圖案23。配線圖案23例如相對於沿第1方向A1之基板21之中心線具有線對稱之形狀。
配線圖案23將與焊接線9a之連接點作為起點重複進行2分支，最終到達8個金屬墊23a。8個金屬墊23a沿長邊21b排列配置。相互相鄰之金屬墊23a彼此經由膜電阻相互連接，構成威爾金森型耦合器。藉此，確保半導體晶片10之複數個閘極墊間之隔離，且謀求自輸入端子2觀察之半導體晶片10之輸入阻抗之匹配。圖1作為一例僅顯示有1個膜電阻23b。8個金屬墊23a經由焊接線9b與電容器50電性連接。
電容器50配置於封裝4之底板4e上。電容器50配置於分支電路基板20與半導體晶片10之間。電容器50例如為平行平板型電容器(晶片電容器)，於介電質基板之主面上具有複數個金屬墊(未圖示)。電容器50之金屬墊之數量例如與金屬墊23a之數量相同。電容器50之複數個金屬墊沿第2方向A2排列成一行。該金屬墊與經由焊接線9b對應之金屬墊23a電性連接。該金屬墊經由焊接線9c與半導體晶片10之對應之閘極墊電性連接。
電容器50藉由焊接線9b、9c之電感成分、與連接於該電感成分之間之節點及基準電位(底板4e)之間之金屬墊之電容，構成T型濾波器電路。電容器50藉由該T型濾波器電路進行阻抗轉換。通常，於半導體晶片10中，根據閘極墊推估電晶體內部而得出之阻抗與傳輸線之特性阻抗(例如50 Ω)不同。電容器50為藉由T型濾波器電路，將該阻抗轉換為根據輸入端子2推估電晶體內部得出之50 Ω之比對電路。
電容器60配置於封裝4之底板4e上。電容器60配置於半導體晶片10與合成電路基板30之間。電容器60與電容器50同樣，例如為平行平板電容器(晶片電容器)。電容器60具有夾著介電質之上部電極及下部電極。即，電容器60亦與電容器50同樣，於介電質基板之主面上具有複數個金屬墊(未圖示)。
電容器60之金屬墊之數量例如與金屬墊23a之數量相同。電容器60之複數個金屬墊沿第2方向A2排列成一行。該金屬墊經由後述之導線群70而與半導體晶片10之對應之汲極墊電性連接。該金屬墊經由焊接線9e與合成電路基板30之對應之金屬墊33a電性連接。另，圖1中，將導線群70之圖式簡化。
於電容器60中，藉由導線群70及焊接線9e之電感成分、與連接於該等電感成分之間之節點及基準電位(底板4e)之間的金屬墊之電容，構成T型濾波器電路。電容器60藉由該T型濾波器電路進行阻抗轉換。通常，於半導體晶片10中根據汲極墊推估電晶體內部而得出之阻抗，與傳輸線之特性阻抗(例如50 Ω)不同，多為小於50 Ω之值。電容器60為藉由T型濾波器電路將該阻抗轉換為根據輸入端子3推估電晶體內部得出之50 Ω的比對電路。
合成電路基板30配置於封裝4之底板4e上。合成電路基板30沿第1方向A1排列配置半導體晶片10及輸出端子3。合成電路基板30位於半導體晶片10與輸出端子3之間。合成電路基板30具有陶瓷製之基板31、與設置於基板31之主面上之合成基板32。基板31之俯視形狀例如為長方形狀。
基板31之一長邊31a介隔電容器60與半導體晶片10對向，基板31之另一長邊31b與輸出端子3對向。基板31之背面與封裝4之底板4e對向。基板31之一短邊31c與封裝4之側壁4c對向，基板31之另一短邊31d與封裝4之側壁4d對向。
合成基板32將自半導體晶片10之複數個汲極墊輸出之信號合成為一個輸出信號。合成基板32包含設置於基板31之主面上之配線圖案33。配線圖案33例如相對於沿第1方向A1之基板31之中心線具有線對稱之形狀。配線圖案33包含4個金屬墊33a。4個金屬墊33a沿基板31之長邊31a排列配置。
相互相鄰之金屬墊33a彼此經由膜電阻相互連接，構成威爾金森型耦合器。藉此，確保半導體晶片10之複數個汲極墊間之隔離，且謀求自輸出端子3觀察之半導體晶片10之輸出阻抗之匹配。另，圖1作為一例僅顯示有1個膜電阻33b。
各金屬墊33a經由焊接線9e與電容器60之對應之2個金屬墊電性連接。配線圖案33重複來自4個金屬墊33a之結合，且最終到達與焊接線9f之連接點。配線圖案33經由焊接線9f與輸出端子3電性連接。放大後之高頻信號自第2方向A2之基板31之中央部輸出至輸出端子3。
輸出端子3為金屬製之配線圖案。輸出端子3將放大後之高頻信號向半導體裝置1之外部輸出。輸出端子3設置於第2方向A2中之端壁4b之中央部。輸出端子3自封裝4之內部延伸至外部。
例如，半導體裝置1具備一對濾波器電路40。濾波器電路40例如為減少輸出信號所含之3次相互調變失真而設置。一者之濾波器電路40配置於第2方向A2中之基板31之中央部、與基板31中位於半導體晶片10之相反側之一側之角部31e之間。
另一者之濾波器電路40配置於第2方向A2中之基板31之中央部、與基板31中位於半導體晶片10之相反側之另一側之角部31f之間。即，一者之濾波器電路40配置於相對基板31之主面之中心靠近角部31e之位置。另一者之濾波器電路40配置於相對基板31之主面之中心靠近角部31f之位置。
其次，一面參照圖2一面說明半導體晶片10及電容器60之詳細內容。圖2係顯示半導體晶片10及電容器60之俯視圖。半導體晶片10呈細長延伸之矩形狀。半導體晶片10具有與電容器60對向之長邊12(一邊)。
例如，長邊12沿第2方向A2延伸。半導體晶片10具備基板15、閘極墊、作用區域、汲極墊18(電極墊)、及空墊19(第2中繼墊)。基板15呈具備上述長邊12之長方形狀。
半導體晶片10例如具備複數個汲極墊18、及複數個空墊19。汲極墊18及空墊19之各者以沿與電容器60對向之長邊12排列之方式配置。藉由使半導體晶片10具備空墊19，可縮短導線群70之各導線之導線長度。
如上所述，電容器60具備介電質61、上部電極62、下部電極(未圖示)、及焊墊63(第1中繼墊)。電容器60(介電質61)具有與半導體晶片10對向之長邊64(一邊)。例如，長邊64沿第2方向A2延伸。
上部電極62及焊墊63配置於介電質61上。焊墊63設置於較上部電極62更靠半導體晶片10側。介電質61呈具備上述長邊64之長方形狀。電容器60具備複數個焊墊63。複數個焊墊63設置於上部電極62之半導體晶片10側。例如，沿長邊64排列複數個焊墊63。各焊墊63呈具有沿第2方向A2延伸之長邊之長方形狀。
如上所述，半導體晶片10及電容器60經由導線群70相互電性連接。導線群70包含第1導線71、第2導線72、及第3導線73。第1導線71將焊墊63、及半導體晶片10之汲極墊18相互連接。第2導線72將電容器60之上部電極62及空墊19相互連接。第3導線73將空墊19及焊墊63相互連接。
例如，將汲極墊18及焊墊63相互連接之第1導線71、將空墊19及焊墊63相互連接之第3導線73、以及將空墊19及上部電極62相互連接之第2導線72，以該順序沿第2方向A2排列。第1導線71、第2導線72、及第3導線73之至少任一者之導線長度，作為一例為0.6 mm。另，第2導線72亦可較第1導線71及第3導線73更長。
如此，本實施形態中，將半導體晶片10及電容器60相互連接之導線群70具備第1導線71、第2導線72、及第3導線73。藉此，可縮短構成導線群70之各導線之導線長度。如圖3所例示，藉由使導線長度(L)縮短，各導線之熔斷電流(I)變高。
圖4係顯示半導體晶片10、電容器60、及第3導線73之圖。如圖4所示，半導體晶片10例如包含Ag-P層10b、Au層10c、SiC層10d、及GaN層10f。半導體晶片10具備於Ag-P層10b上設置有Au層10c、於Au層10c上設置有SiC層10d、於SiC層10d上設置有GaN層10f之構成。
空墊19設置於GaN層10f上。空墊19例如包含金(Au)。半導體晶片10自空墊19經由GaN層10f使熱量流入SiC層10d。來自導線群70(例如第3導線73)之熱量被放熱，可抑制因發熱導致之導線群70之熔斷。作為一例，底板4e之厚度T1為1000 μm，Ag-P層10b之厚度T2為30 μm，Au層10c及SiC層10d之厚度T3為100 μm。GaN層10f之厚度T4為0.6 μm，空墊19之厚度T5為10 μm，來自空墊19之焊墊63之立起高度H為100 μm。
例如，半導體晶片10之基板15包含Ag-P層10b、Au層10c及SiC層10d。如上所述，基板15作為將元件產生之熱量放熱之放熱板而發揮功能。基板15例如由放熱性較高之材料構成。例如，基板15亦可具備SiC層10d，同時具備金剛石層或金屬層，或替代SiC層10d而具備金剛石層或金屬層。基板15之金屬層之材料例如為包含銅或金之紅色系金屬材料、或包含銀、鎳或鋁之銀白色系金屬材料。
電容器60例如包含Ag-P層60b、Au層60c、及陶瓷層60d。電容器60具備於Ag-P層60b上設置Au層60c、於Au層60c上設置陶瓷層60d之構成。焊墊63設置於陶瓷層60d上。焊墊63例如包含金(Au)。於電容器60中，來自導線群70(例如第3導線73)之熱量自焊墊63放熱至陶瓷層60d。其結果，可抑制因發熱導致之導線群70之熔斷。
圖5係顯示圖1所示之半導體晶片10、電容器60及導線群70之整體之俯視圖。如圖5所示，導線群70包含複數條第1導線71、複數條第2導線72、及複數條第3導線73。導線群70亦可具備包含第1導線71、第2導線72、及第3導線73之複數個組75。例如，複數個組75沿第2方向A2排列。
例如，於各組75中，以第1導線71、第3導線73及第2導線72按該順序沿第2方向A2排列之方式配置。作為一例，組75之數量為9。例如，空墊19之第2方向A2之長度L1較汲極墊18之第2方向A2之長度L2更長。作為一例，空墊19之長度L1為250 μm，汲極墊18之長度L2為150 μm。自位於第2方向A2之一端之汲極墊18至位於第2方向A2之另一端之汲極墊18之長度X為5.34 mm。
其後，對自實施形態之半導體裝置1獲得之作用效果進行說明。於半導體裝置1中，半導體晶片10於基板15上具備電晶體及汲極墊18。電容器60具備夾著介電質61之上部電極62及下部電極。第1導線71將半導體晶片10之汲極墊18與焊墊63相互連接。第3導線73將焊墊63與空墊19相互連接。第2導線72將空墊19與電容器60之上部電極62相互連接。因此，半導體晶片10與電容器60經由自半導體晶片10延伸之第1導線71、焊墊63、第3導線73、半導體晶片10上之空墊19、及向電容器60延伸之第2導線72相互連接。
藉由具備第1導線71、焊墊63、第3導線73、空墊19、及第2導線72，可將連接於半導體晶片10之汲極墊18之導線僅作為第1導線71。藉由經由焊墊63及空墊19將各導線相互連接，可縮短各導線。
焊墊63可配置於電容60之介電質61上之自上部電極62離開之位置。空墊19可沿半導體晶片10之長邊12配置。該情形，可將焊墊63配置於電容器60之介電質61上。可沿與電容器60對向之半導體晶片10之長邊12配置空墊19。
汲極墊18可沿半導體晶片10之長邊12配置，空墊19可與汲極墊18相鄰配置。該情形時，可以沿與電容器60對向之半導體晶片10之長邊12排列之方式，配置半導體晶片10上之汲極墊18及空墊19。
半導體裝置1亦可具備沿電容器60之長邊64排列之複數個焊墊63、與沿半導體晶片10之長邊12排列之複數個空墊19、及複數個汲極墊18。複數個空墊19之各者可與汲極墊18相鄰配置。該情形，可沿與半導體晶片10對向之電容器60之長邊64排列複數個焊墊63，且可沿與電容器60對向之半導體晶片10之長邊12排列汲極墊18及空墊19。
基板15可由碳化矽(SiC)、金剛石、或金屬構成。該情形時，可由放熱性較高之材料構成基板15。
其後，一面參照圖6一面說明第1變化例之半導體裝置。如圖6所示，第1變化例之半導體裝置具備汲極墊18A、空墊19B、焊墊63A、及導線群70A。汲極墊18A與汲極墊18不同，空墊19B與空墊19不同。焊墊63A與焊墊63不同，導線群70A與導線群70不同。以下，適當省略與上述半導體裝置1之說明重複之說明。
圖7係顯示圖6所示之第1變化例之半導體裝置之半導體晶片10A及電容器60A之第2方向A2之整體之俯視圖。如圖7所示，第1變化例之半導體晶片10A具備空墊19A及空墊19B。空墊19A設置於半導體晶片10A之第2方向A2之兩端之各者。空墊19A之形狀、大小、及功能例如與上述空墊19相同。空墊19B自空墊19A觀察，配置於半導體晶片10A之第2方向A2之中央側。複數個空墊19B被夾於一對空墊19A之間。
第1變化例之半導體裝置中，於汲極墊18A連接有1條或2條第1導線71。於空墊19B連接有2條第2導線72及2條第3導線73，於焊墊63A連接有1條或2條第1導線71及1條或2條第3導線73。於第1變化例之半導體裝置中，空墊19B及焊墊63A作為連接複數條導線之焊墊而共通化。
導線群70A具備複數個第1組75A及複數個第2組75B，且第1組75A與第2組75B中導線之排列順序相互不同。第1組75A及第2組75B，例如沿第2方向A2交替排列。於第1組75A中，第2導線72、第3導線73及第1導線71以按該順序沿第2方向A2排列之方式配置。於第2組75B中，第1導線71、第3導線73及第2導線72以按該順序沿第2方向A2排列之方式配置。作為一例，第1組75A之數量及第2組75B之數量為6。例如，空墊19B之第2方向A2之長度L3、及焊墊63A之第2方向A2之長度為500 μm。
以上，第1變化例之半導體裝置具備複數條第1導線71、及複數條第2導線72。相互相鄰之複數條第1導線71之各者連接於共通之焊墊63A。相互相鄰之複數條第2導線72之各者連接於共通之空墊19B。因此，可將焊墊63A及空墊19B更加有效地作為導線之連接部利用。又，可進而縮短導線群70A之各導線之導線長度。由於導線群70A之各導線之間隔變短且相互電感增加，故可使各導線之導線長度縮短相互電感之增加量。因此，可進而減少導線群70A之各導線之熔斷之可能性。
更具體而言，如圖8所例示，位於第2方向A2之端部之導線W1主要受到單側最接近之導線W2與其次相鄰之導線W3之影響。另一方面，導線W4由於受到兩側之導線W2、導線W3、導線W5及導線W6之影響，故相互電感之有效之導線長度與導線W1比較，有較大變化。若將各導線之長度設為l、各導線之半徑設為r、各導線之距接地之高度設為h、導線之間隔設為d、真空之透磁率設為μ0，則相互電感如下式(1)表示。 [數1]
Figure 02_image001
根據上述式(1)，相互電感M與導線之長度l成正比，且導線之間隔d越狹窄變得越大。因此，由於導線之間隔越狹窄，相互電感M變得越大，故可使導線之長度l較短。
其後，一面參照圖9及圖10一面說明第2變化例之半導體裝置。圖9係顯示圖2之變化例之半導體晶片10C及電容器60C之表面。圖10係顯示半導體晶片10及電容器60C之背面。半導體晶片10C具備汲極墊18A、汲極墊18B、及空墊19A、19B。
本變化例中，汲極墊18A設置於半導體晶片10C之第2方向A2之兩端之各者。於汲極墊18A例如連接有1條第1導線71。於汲極墊18B連接有2條第1導線71。於空墊19B連接有2條第2導線72、及2條第3導線73。
電容器60C具備介電質61、上部電極62、焊墊63A、及焊墊63B。焊墊63B設置於電容器60C之第2方向A2之兩端之各者。焊墊63A連接有2條第1導線71、及2條第3導線73。於焊墊63B連接有1條第1導線71、及1條第3導線73。第2變化例之導線群70C具備沿第2方向A2排列之複數個第1組75A及複數個第2組75B。第2組75B及第1組75A沿第2方向A2交替排列。
半導體晶片10C進而具備背面電極10g，電容器60C進而具備背面電極67。背面電極10g例如呈沿半導體晶片10之長邊12、長邊13及短邊14之長方形狀。背面電極10g設置於閘極墊16及作用區域17之半導體晶片10C之背面。背面電極10g未設置於汲極墊18A、18B及空墊19B之半導體晶片10C之背面。即，背面電極10g自半導體晶片10C之汲極墊18A、18B及空墊19B之背側被削除。
電容器60C之背面電極67設置於上部電極62之背面。背面電極67未設置於焊墊63A及焊墊63B之電容器60C之背面。即，背面電極67自電容器60C之焊墊63A及焊墊63B之背面被削除。
以上，第2變化例之半導體裝置於電容器60C之背面，具備設置於與焊墊63A及焊墊63B對向之區域以外的區域之背面電極67。如此，因不於焊墊63A及焊墊63B之背面設置背面電極67，可抑制焊墊63A及焊墊63B產生之寄生電容。
第2變化例之半導體裝置於半導體晶片10C之背面、或基板15之背面，具備設置於與空墊19B對向之區域以外的區域之背面電極10g。如此，因不於空墊19B之背面設置背面電極10g，可抑制空墊19B產生之寄生電容。
其後，一面參照圖11一面說明第3變化例之半導體裝置。如圖11所示，第3變化例之半導體裝置具備半導體晶片10、電容器60D、及中繼基板80。電容器60D於不具有焊墊63之點上，與上述電容器60不同。第3變化例之半導體裝置具備設置於與半導體晶片10及電容器60D分開之中繼基板80之中繼墊81(第1中繼墊)，來取代焊墊63。
中繼基板80為具有向第2方向A2延伸之長邊、及向第1方向A1延伸之短邊之長方形狀。中繼墊81設為具有沿中繼基板80之長邊延伸之長邊、及沿中繼基板80之短邊延伸之短邊之長方形狀。於中繼墊81連接有自複數個汲極墊18之各者延伸之複數條第1導線71、及自複數個空墊19延伸之複數條第3導線73。
以上，於第3變化例之半導體裝置中，中繼墊81設置於電容器60D與半導體晶片10之間。因此，可將中繼墊81配置於自電容器60D及半導體晶片10之兩者分離之部位。
以上對本揭示之半導體裝置之實施形態進行說明。然而，本發明並不限定於上述之實施形態或變化例。即，熟知本技藝者可容易地辨識本發明可於不變更申請專利範圍所記載之主旨之範圍內進行各種變化及變更。例如，半導體裝置之各零件之形狀、大小、數量、材料及配置態樣，不限於上述內容，可進行適當變更。
例如，於上述實施形態中，對半導體晶片10具備2個放大元件11之例進行說明。然而，放大元件11之數量亦可為1個，又可為3個以上，可適當變更。
於上文中，對具備設置於與半導體晶片10及電容器60D分開之中繼基板80之中繼墊81來取代電容器60之焊墊63之例進行說明。然而，亦可具備設置於與半導體晶片10及電容器60分開之中繼基板之中繼墊來取代半導體晶片10之空墊19。如此，中繼墊可與半導體晶片10或電容器60一體設置，亦可分開設置。中繼墊之配置態樣可適當變更。第1導線71、第2導線72及第3導線73之數量、及配置態樣亦可適當變更。
1:半導體裝置 2:輸入端子 3:輸出端子 4:封裝 4a:端壁 4b:端壁 4c:側壁 4d:側壁 4e:底板 9a:焊接線 9b:焊接線 9c:焊接線 9e:焊接線 9f:焊接線 10:半導體晶片 10A:半導體晶片 10b:Ag-P層 10C:半導體晶片 10c:Au層 10d:SiC層 10f:GaN層 10g:背面電極 11:放大元件 12:長邊(一邊) 13:長邊 14:短邊 15:基板 16:閘極墊 17:作用區域 18:汲極墊(電極墊) 18A:汲極墊(電極墊) 18B:汲極墊(電極墊) 19:空墊(第2中繼墊) 19A:空墊(第2中繼墊) 19B:空墊(第2中繼墊) 20:分支電路基板 21:基板 21a:長邊 21b:長邊 21c:短邊 21d:短邊 22:分支電路 23:配線圖案 23a:金屬墊 23b:膜電阻 30:合成電路基板 31:基板 31a:長邊 31b:長邊 31c:短邊 31d:短邊 31e:角部 31f:角部 32:合成基板 33:配線圖案 33a:金屬墊 33b:膜電阻 40:濾波器電路 50:電容器 60:電容器 60A:電容器 60b:Ag-P層 60C:電容器 60c:Au層 60D:電容器 60d:陶瓷層 61:介電質 62:上部電極 63:焊墊(第1中繼墊) 63A:焊墊(第1中繼墊) 63B:焊墊(第1中繼墊) 64:長邊(一邊) 65:長邊 66:短邊 67:背面電極 70:導線群 70A:導線群 70C:導線群 71:第1導線 72:第2導線 73:第3導線 75:組 75A:第1組 75B:第2組 80:中繼基板 81:中繼墊(第1中繼墊) A1:第1方向 A2:第2方向 d:間隔 H:立起高度 L:導線長度 l:導線長度 L1:長度 L2:長度 L3:長度 M:相互電感 T1:厚度 T2:厚度 T3:厚度 T4:厚度 T5:厚度 W1:導線 W2:導線 W3:導線 W4:導線 W5:導線 W6:導線 X:長度
圖1係顯示一實施形態之半導體裝置之內部構成之俯視圖。 圖2係顯示圖1之半導體裝置之半導體晶片、電容器及導線之俯視圖。 圖3係顯示導線長度與電流之關係之例之圖表。 圖4係顯示圖1之半導體裝置之半導體晶片、電容器、及導線之圖。 圖5係顯示圖1之半導體裝置之半導體晶片、電容器、及導線之俯視圖。 圖6係顯示第1之變化例之半導體裝置之半導體晶片、電容器、及導線之俯視圖。 圖7係顯示圖6之半導體晶片、電容器、及導線之圖。 圖8係將導線放大之立體圖。 圖9係顯示圖2之變化例之半導體裝置之半導體晶片、電容器、及導線之俯視圖。 圖10係顯示圖9之半導體晶片之背面、及電容器之背面之後視圖。 圖11係顯示圖3之變化例之半導體裝置之半導體晶片、第1中繼墊、電容器、及導線之俯視圖。
10:半導體晶片
12:長邊(一邊)
15:基板
18:汲極墊(電極墊)
19:空墊(第2中繼墊)
60:電容器
61:介電質
62:上部電極
63:焊墊(第1中繼墊)
64:長邊(一邊)
70:導線群
71:第1導線
72:第2導線
73:第3導線
75:組
A1:第1方向
A2:第2方向
L1:長度
L2:長度
X:長度

Claims (9)

  1. 一種半導體裝置，其具備： 半導體晶片，其具有設置於基板上之電晶體及電極墊； 電容器，其具有夾著介電質之上部電極及下部電極； 第1中繼墊； 第2中繼墊，其設置於上述半導體晶片之上述基板上； 第1導線，其將上述第1中繼墊及上述半導體晶片之上述電極墊相互連接； 第2導線，其將上述第2中繼墊及上述電容器之上述上部電極相互連接；及 第3導線，其將上述第1中繼墊及上述第2中繼墊相互連接。
  2. 如請求項1之半導體裝置，其中 上述第1中繼墊配置於上述電容器之上述介電質上之與上述上部電極離開之位置； 上述第2中繼墊沿上述半導體晶片之一邊配置。
  3. 如請求項1或2之半導體裝置，其中 上述電極墊沿上述半導體晶片之一邊配置； 上述第2中繼墊與上述電極墊相鄰配置。
  4. 如請求項1至3中任一項之半導體裝置，其具備： 複數個上述第1中繼墊，其等沿上述電容器之一邊排列；及 複數個上述第2中繼墊及複數個上述電極墊，其等沿上述半導體晶片之一邊排列；且 複數個上述第2中繼墊之各者與上述電極墊相鄰配置。
  5. 如請求項1至4中任一項之半導體裝置，其具備： 複數條上述第1導線、及複數條上述第2導線；且 相互相鄰之複數條上述第1導線之各者連接於共通之上述第1中繼墊； 相互相鄰之複數條上述第2導線之各者連接於共通之上述第2中繼墊。
  6. 如請求項1至5中任一項之半導體裝置，其中 於上述電容器之上述介電質之背面，具備設置於與上述第1中繼墊對向之區域以外的區域之背面電極。
  7. 如請求項1至6中任一項之半導體裝置，其中 於上述半導體晶片之背面或上述基板之背面，具備設置於與上述第2中繼墊對向之區域以外的區域之背面電極。
  8. 如請求項1之半導體裝置，其中 上述第1中繼墊設置於上述電容器與上述半導體晶片之間。
  9. 如請求項1至8中任一項之半導體裝置，其中 上述基板由碳化矽(SiC)、金剛石、或金屬構成。
TW110133261A 2020-09-07 2021-09-07 半導體裝置 TW202215627A (zh)

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