TW202215493A - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TW202215493A
TW202215493A TW110113720A TW110113720A TW202215493A TW 202215493 A TW202215493 A TW 202215493A TW 110113720 A TW110113720 A TW 110113720A TW 110113720 A TW110113720 A TW 110113720A TW 202215493 A TW202215493 A TW 202215493A
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TWI786600B (zh
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林孟漢
世海 楊
志安 徐
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台灣積體電路製造股份有限公司
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Abstract

在本公開的一個實施例中，半導體裝置包括相鄰於第一源極/汲極區域的基板中的第一通道區域、在第一通道區域上方的第一閘極、在相鄰於第二源極/汲極區域的基板中的第二通道區域且第二通道區域的頂表面低於第一通道區域的頂表面、在第二通道區域上方的第二閘極、在第一閘極和第二閘極上方的層間介電質、延伸穿過層間介電質並耦接至第一源極/汲極區域的第一接觸，以及延伸穿過層間介電質、耦接至第二源極/汲極區域並具有寬度大於第一接觸的寬度和高度大於第一接觸的高度的第二接觸。

Description

半導體裝置的接觸及其形成方法
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半導體裝置使用在多種電子產品中，例如個人電腦、手機、數位相機和其他電子裝置。半導體裝置的製造通常藉由依序在半導體基板上方沉積絕緣層或介電層、導電層和半導體層的材料，並使用微影技術圖案化多種材料層以在半導體基板上形成電路組件和元件。
半導體工業藉由持續縮減最小特徵尺寸以持續改善多種電子組件(例如電晶體、二極體、電阻器、電容器等)的積體密度，從而允許更多組件集成在給定區域中。
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為了實現提及主題的不同特徵，以下公開內容提供了許多不同的實施例或示例。以下描述組件、配置等的具體示例以簡化本公開。當然，這些僅僅是示例，而不是限制性的。例如，在以下的描述中，在第二特徵之上或上方形成第一特徵可以包括第一特徵和第二特徵以直接接觸形成的實施例，並且還可以包括在第一特徵和第二特徵之間形成附加特徵，使得第一特徵和第二特徵可以不直接接觸的實施例。另外，本公開可以在各種示例中重複參考數字和/或字母。此重複是為了簡單和清楚的目的，並且本身並不表示所討論的各種實施例和/或配置之間的關係。
此外，本文可以使用空間相對術語，諸如「在…下面」、「在…下方」、「下部」、「在…上面」、「上部」等，以便於描述一個元件或特徵與如圖所示的另一個元件或特徵的關係。除了圖中所示的取向之外，空間相對術語旨在包括使用或操作中的裝置的不同取向。裝置可以以其他方式定向(旋轉90度或在其他方向上)，並且同樣可以相應地解釋在此使用的空間相對描述符號。
本公開的多種實施例提供低電壓半導體裝置和高電壓半導體裝置的接觸的形成方法和使用方法所形成的半導體裝置。方法包括在基板的第一區域中形成低電壓半導體裝置和在基板的第二區域中形成高電壓半導體區域。基板的第二區域凹陷低於基板的第一區域。閘極形成在第一區域和第二區域中，其中在第二區域中的閘極具有高度大於在第一區域中的閘極的高度。一或多個層間介電質形成在第一區域和第二區域上方。圖案化光阻形成在層間介電質上方，並使用圖案化光阻形成開口以暴露第一區域中的第一源極/汲極區域、第二區域中的第二源極/汲極區，以及第一區域和第二區域的閘極。
光阻經過圖案化以包括在第一源極/汲極區域上方的第一開口、在第二源極/汲極區域上方的第二開口，以及在閘極上方的第三開口。第二開口可具有寬度大於第一開口和第三開口，且第一開口可具有寬度等同或大於第三開口。當開口的寬度增加，可增加其下方層間介電質的蝕刻速率。因此，開口的不同寬度可用以暴露設置在不同高度的第一源極/汲極區域、第二源極/汲極區域和閘極，避免過度蝕刻第一源極/汲極區域、第二源極/汲極區域或閘極。這減少了裝置缺陷並改善裝置性能。此外，可減去遮罩步驟以減少成本。
本文討論的一些實施例的內容是關於使用後閘極(gate-last)製程所形成的平面場效應電晶體(field effect transistor，FET)。在其他實施例中，可使用前閘極(gate-first)製程。另外，一些實施例可實現用於鰭式場效應電晶體(fin field effect transistor，FinFET)、奈米結構(例如奈米片、奈米導線、閘極全環繞或類似者)場效應電晶體(nanostructure field effect transistor，NSFET)或類似者的態樣。
在第1圖中，提供基板50。基板50可以是半導體基板，例如塊材半導體、絕緣體上半導體(semiconductor-on-insulator，SOI)基板或類似者，其可以是摻雜的(例如，具有p型或n型摻雜)或未摻雜的。基板50可以是晶片，例如矽晶片。通常地，SOI基板是形成在絕緣層上的一層半導體材料。例如，絕緣層可以是埋藏式氧化物(buried oxide，BOX)層、氧化矽層或類似者。絕緣層設置在基板上，通常是矽或玻璃基板。也可使用其他基板，例如多層或漸變基板。在一些實施例中，基板50的半導體材料可包括矽、鍺、化合物半導體(包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銦銻化物)、合金半導體(包括矽鍺、砷磷化鎵、砷化銦鋁、砷化鎵鋁、砷化銦鎵、磷化銦鎵及/或砷磷化鎵銦或是上述的組合。
基板50具有低電壓(low-voltage，LV)裝置區域100和高電壓(high-voltage，HV)裝置區域200。LV裝置區域100是形成低電壓裝置的區域，例如低電壓金屬氧化物半導體(metal-oxide-semiconductor，MOS)裝置。HV裝置區域200是形成高電壓裝置的區域，例如高電壓MOS裝置。LV裝置配置成在操作電壓和電源供應電壓分別低於HV裝置的操作電壓和電源供應電壓的情況下操作。應理解，HV和LV的概念是彼此相對的。LV裝置可以耐受而不造成其損害的最大電壓低於HV裝置可以耐受而不造成其損害的最大電壓。在一些實施例中，HV裝置的操作電壓和電源供應電壓介於約2.5 V和約15 V之間，且LV裝置的操作電壓和電源供應電壓介於約0.5 V和約1 V之間。LV裝置區域100可以物理上和HV裝置區域200分離(如所繪示的分隔層51)，且任何數量的裝置特徵(例如，其他主動裝置、摻雜區域、隔離結構或類似者)可設置在LV裝置區域100和HV裝置區域200之間。
進一步在第1圖中，襯墊層52和遮罩層54形成在基板50上。襯墊層52可包括薄膜的氧化矽或類似者，其可使用熱氧化製程或類似者所形成。在一些實施例中，襯墊層52可包括氮化矽、氧氮化矽、上述的組合或多層結構或是類似者。襯墊層52可以做為基板50和遮罩層54之間的黏附層。襯墊層52也可以做為蝕刻遮罩層54時的蝕刻停止層。在一些實施例中，遮罩層54由氮化矽或類似者形成。在一些實施例中，遮罩層54可包括氧氮化矽、多晶矽、上述的組合或多層或是類似者。遮罩層54可以由化學氣相沉積(chemical vapor deposition，CVD)、原子層沉積(atomic layer deposition，ALD)或類似者所形成。遮罩層54可以在後續微影製程期間做為硬遮罩使用。
在第2圖中，蝕刻遮罩層54、襯墊層52和基板50以形成溝槽56。第一圖案化遮罩(未特別繪示)可形成在遮罩層54上方，例如圖案化光阻。第一圖案化遮罩的形成可藉由使用旋轉塗佈或類似者在遮罩層54上方沉積第一光敏層。第一光敏層可接著藉由將第一光敏層暴露於圖案化能量源(例如，具有圖案的光源)並顯影第一光敏層以移除第一光敏層的暴露或未暴露部分來圖案化，從而形成第一圖案化遮罩。遮罩層54、襯墊層52和基板50可藉由適合的蝕刻製程蝕刻，例如反應離子蝕刻(reactive ion etching，RIE)、中性粒子束蝕刻(neutral beam，NBE)、類似者或上述的組合，以將第一圖案化遮罩的圖案轉移至遮罩層54、襯墊層52和基板50並形成溝槽56。在一些實施例中，蝕刻製程可以是各向異性的。第一圖案化遮罩可接著藉由任何可接受的製程移除，例如灰化製程、剝離製程、類似者或上述的組合。
在第3圖中，淺溝槽隔離(shallow trench isolation，STI)區域58形成在相鄰遮罩層54、襯墊層52和基板50的溝槽56中。淺槽隔離區域58的形成可藉由形成絕緣材料(未特別繪示)填充溝槽56並沿著基板50的頂表面和側表面、襯墊層52的側表面和遮罩層54的頂表面和側表面延伸。絕緣材料可以是氧化物(例如氧化矽)、氮化物、類似者或上述的組合，且可以藉由高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition，HDP-CVD)、可流動化學氣相沉積(flowable CVD，FCVD)(例如，在可控的電漿系統中以化學氣相沉積為主的材料沉積，並使用後固化(post curing)以將沉積材料轉變成另一種材料，例如氧化物)、類似者或上述的組合所形成。也可使用藉由任何可接受的製程所形成的其他絕緣材料。在所繪示的實施例中，絕緣材料是藉由FCVD製程所形成的氧化矽。當形成絕緣材料後，可執行退火製程。在一些實施例中，形成絕緣材料使得多餘的絕緣材料覆蓋遮罩層54。絕緣材料可包括單層或可使用多層。例如，在一些實施例中，內襯層(未特別繪示)可首先沿著基板50、襯墊層52和遮罩層54的表面形成。之後，在內襯層上方形成例如上文討論的填充材料。
接著對絕緣材料執行移除製程以移除在遮罩層54上方的多餘的絕緣材料。在一些實施例中，可使用平坦化製程，例如化學機械研磨(chemical mechanical polish，CMP)、回蝕製程、上述的組合或類似者。移除製程可平坦化絕緣材料和遮罩層54並形成淺槽隔離區域58。移除製程暴露遮罩層54使得在平坦化製程完成後的遮罩層54的頂表面和淺槽隔離區域58的頂表面齊平。
在第4圖中，第二圖案化遮罩60形成在LV裝置區域100和淺槽隔離區域58上方，而HV裝置區域200中的遮罩層54、襯墊層52和基板50經過蝕刻。第二圖案化遮罩60可以是圖案化光阻。第二圖案化遮罩60的形成可以藉由使用旋轉塗佈或類似者以沉積第二光敏層在遮罩層54和淺槽隔離區域58上方。可接著藉由將第二光敏層暴露於圖案化能量源(例如，具有圖案的光源)並顯影第二光敏層以移除第二光敏層的暴露或未暴露部分來圖案化第二光敏層，從而形成覆蓋LV裝置區域100並暴露HV裝置區域200的第二圖案化遮罩60。可接著藉由適合的蝕刻製程來蝕刻HV裝置區域200中的遮罩層54、襯墊層52、基板50和淺槽隔離區域58。蝕刻製程可以是濕式蝕刻製程、乾式蝕刻製程或類似者。在一些實施例中，蝕刻製程可以是反應離子蝕刻、中性粒子束蝕刻、類似者或上述的組合。在一些實施例中，蝕刻製程可以是各向異性的。在一些實施例中，遮罩層54、襯墊層52和基板50可以和淺槽隔離區域58是分開蝕刻的。可以在蝕刻淺槽隔離區域58之前或之後蝕刻遮罩層54、襯墊層52和基板50。
如第4圖中所繪示，在垂直於基板50的主表面的方向上，LV裝置區域100中的遮罩層54和淺槽隔離區域58的頂表面可以設置成高於HV裝置區域200中的基板50和淺槽隔離區域58的頂表面。LV裝置區域100中的遮罩層54和淺槽隔離區域58的頂表面可以設置成以高度H 1高於HV裝置區域200中的基板50和淺槽隔離區域58的頂表面，其中高度H 1介於約50 nm至約350 nm的範圍。隨後形成在HV裝置區域200中的閘極結構可具有高度大於隨後形成在LV裝置區域100中的閘極結構。凹陷HV裝置區域200中的基板50和淺槽隔離區域58允許隨後在LV裝置區域100和HV裝置區域200中形成的閘極結構可以同時形成。
在第5圖中，從LV裝置區域100移除第二圖案化遮罩60、遮罩層54和襯墊層52。第二圖案化遮罩60的移除可藉由任何可接受的製程，例如灰化製程、剝離製程、類似者或上述的組合。在遮罩層54包括氮化矽且襯墊層52包括氧化矽的實施例中，遮罩層54的移除可以藉由使用磷酸(H 3PO 4)或類似者的濕式清洗(wet clean)製程，且襯墊層52的移除可以藉由使用稀釋氫氟酸(diluted hydrofluoric acid，dHF)或類似者的濕式蝕刻製程。亦可凹陷淺槽隔離區域58使得淺槽隔離區域58的頂表面與基板50的頂表面實質上共平面。在一些實施例中，可執行平坦化製程(例如CMP製程)以使LV裝置區域100中的淺槽隔離區域58的頂表面與基板50的頂表面齊平。在一些實施例中，在LV裝置區域100上執行平坦化製程時可遮蔽HV裝置區域200。
在第6圖中，第一阱62形成在LV裝置區域100中的基板50中，且第二阱64形成在HV裝置區域200中的基板50中。在一些實施例中，第一阱62和第二阱64可以由相同或不同的摻雜劑摻雜，且第一阱62和第二阱64可以摻雜至相同或不同的摻雜劑濃度。進一步地，第一阱62和第二阱64中任一者可以使用n型或p型摻雜劑佈植。在不同的摻雜劑或不同摻雜劑濃度的實施例中，可使用光阻或其他遮罩(未特別繪示)實現針對LV裝置區域100和HV裝置區域200的不同佈植步驟。例如，光阻可形成在LV裝置區域100中的基板50和淺槽隔離區域58上方。圖案化光阻以暴露基板50的HV裝置區域200。可使用旋轉塗佈技術形成光阻，並可使用可接受的微影技術進行圖案化。一旦圖案化光阻後，在HV裝置區域200中執行雜質佈植，且光阻可做為遮罩以避免雜質佈植進LV裝置區域100中。雜質可以是磷、砷、銻、硼、氟化硼、銦或類似者，佈植在區域中的濃度可等於或低於1x10 18atoms/cm 3，例如介於約1x10 16atoms/cm 3和約1x10 18atoms/cm 3之間。佈植之後移除光阻，例如使用可接受的灰化製程。
在佈植HV裝置區域200之後，光阻形成在HV裝置區域200中的基板50和淺槽隔離區域58上方。圖案化光阻以暴露基板50的LV裝置區域100。可以使用旋轉塗佈技術形成光阻，並可使用可接受的微影技術進行圖案化。一旦圖案化光阻後，可在LV裝置區域100中執行雜質佈植，且光阻可以做為遮罩以避免雜質佈植進入HV裝置區域200。p型雜質可以是磷、砷、銻、硼、氟化硼、銦或類似者，佈植在區域中的濃度可等於或低於1x10 18atoms/cm 3，例如介於約1x10 16atoms/cm 3和約1x10 18atoms/cm 3之間。在佈植之後可移除光阻，例如使用可接受的灰化製程。在佈植LV裝置區域100和HV裝置區域200之後，可執行退火以修復佈植的損傷且激發佈植的雜質。第一阱62和第二阱64繪示成具有底表面設置低於淺槽隔離區域58的底表面並延伸至淺槽隔離區域58下方。在一些實施例中，第一阱62和第二阱64不延伸至淺槽隔離區域58下方。在一些實施例中，淺槽隔離區域58的底表面設置低於第一阱62及/或第二阱64的底表面。
在第7圖中，第一閘極介電層66形成在淺槽隔離區域58、第一阱62和第二阱64上方。第一閘極介電層66可以是介電材料，其可包括氧化物(例如氧化矽)、氮化物(例如氮化矽)、複合結構(例如氧化物/氮化物/氧化物)、上述的組合或多層，或是類似者。可藉由沉積製程形成第一閘極介電層66，例如CVD、ALD或類似者。在一些實施例中，第一閘極介電層66形成閘極氧化物以在後續形成高電壓電晶體。第一閘極介電層66可具有厚度介於約10 nm和約100 nm之間。
在第8圖中，從LV裝置區域100移除第一閘極介電層66。可藉由可接受的微影和蝕刻製程移除第一閘極介電層66。如第8圖所繪示，HV裝置區域200中第一閘極介電層66的頂表面可以和LV裝置區域100中第一阱62和淺槽隔離區域58的頂表面共平面。從LV裝置區域100移除第一閘極介電層66之後，可以暴露第一阱62和淺槽隔離區域58的頂表面。在一些實施例中，HV裝置區域200中第一閘極介電層66的頂表面可以高於或低於LV裝置區域100中第一阱62和淺槽隔離區域58的頂表面。
在第9圖中，第二閘極介電層70形成在淺槽隔離區域58、第一阱62和第一閘極介電層66上方。例如，第二閘極介電層70可以是氧化矽、氮化矽、上述的組合或類似者，且可根據可接受的技術進行沉積或熱生長。閘極層72形成在第二閘極介電層70上方，且遮罩層74形成在閘極層72上方。閘極層72可沉積在第二閘極介電層70上方並平坦化，例如藉由CMP。遮罩層74可以沉積在閘極層72上方。閘極層72可以是導電或非導電材料，並可選自由非晶矽、多晶矽(polysilicon)、多晶矽鍺(poly-SiGe)、金屬氮化物、金屬矽化物、金屬氧化物和金屬所組成的群組。閘極層72的沉積可藉由物理氣相沉積(physical vapor deposition，PVD)、CVD、濺鍍沉積或其他技術沉積選擇的材料。閘極層72可以由其他材料所形成，其材料和隔離區域(例如淺槽隔離區域58、第一閘極介電層66及/或第二閘極介電層70)的蝕刻相比具有高蝕刻選擇性。遮罩層74可包括一或多個層，例如氮化矽、氮氧化矽或類似者。在第9圖繪示的實施例中，單層的閘極層72和單層的遮罩層74橫跨LV裝置區域100和HV裝置區域200形成。應注意，為了繪圖的目的，所示的第二閘極介電層70覆蓋第一阱62和淺槽隔離區域58。在一些實施例中，可沉積第二閘極介電層70使得第二閘極介電層70只覆蓋第一阱62和第一閘極介電層66。
在第10圖中，可使用可接受的微影和蝕刻技術圖案化遮罩層74(如第7圖所示)以形成遮罩86。遮罩86的圖案可接著轉移至閘極層72以形成閘極84。在一些實施例中，遮罩86的圖案亦可轉移至LV裝置區域100和HV裝置區域200中的第二閘極介電層70以形成第二閘極介電質82，並可轉移至HV裝置區域200中的第一閘極介電層66以形成第一閘極介電質80。可藉由可接受的蝕刻技術轉移遮罩86的圖案。閘極84覆蓋第一阱62和第二阱64個別的通道區域87。遮罩86的圖案物理上分離各個閘極84和其相鄰的閘極。
在圖案化遮罩層74、閘極層72、第二閘極介電層70和第一閘極介電層66以形成遮罩86、閘極84、第二閘極介電質82和第一閘極介電質80後，可針對輕度摻雜源極/汲極(lightly doped source/drain，LDD)區域(未特別繪示)執行佈植。在LV裝置區域100和HV裝置區域200具有不同裝置類型的實施例中，類似於上文第6圖中討論的佈植，可形成遮罩(例如光阻)在HV裝置區域200上方同時暴露LV裝置區域100，並可將適當類型(例如，n型或p型)雜質佈植進LV裝置區域100中暴露的第一阱62。接著可移除遮罩。隨後地，可形成遮罩(例如光阻)在LV裝置區域100上方同時暴露HV裝置區域200，並可將適當類型雜質(例如，n型或p型)佈植進HV裝置區域200中暴露的第二阱64。接著可移除遮罩。n型雜質可以是先前討論的任何n型雜質，而p型雜質可以是先前討論的任何p型雜質。輕度摻雜源極/汲極區域可具有雜質濃度從約10 15atoms/cm 3至約10 19atoms/cm 3。可使用退火以修補佈植的損傷並且激發佈植的雜質。
應注意，上方揭露的內容普遍描述形成間隔物和LDD區域的製程。可以使用其他製程和順序。例如，可使用更少或更多的間隔物。在一些實施例中，可沿著遮罩86、閘極84、第二閘極介電質82和第一閘極介電質80的側壁形成閘極封裝間隔物(未特別繪示)，且可在形成閘極封裝間隔物之後形成LDD區域。另外，可使用不同結構和步驟形成n型和p型裝置。例如，可在形成閘極封裝間隔物之前形成n型裝置的LDD區域，而在形成閘極封裝間隔物之後形成p型裝置的LDD區域。
在第11圖中，沿著遮罩86、閘極84、第二閘極介電質82和第一閘極介電質80的側壁形成閘極間隔物88。可藉由共形沉積絕緣材料並接續絕緣材料的各向異性蝕刻形成閘極間隔物88。閘極間隔物88的絕緣材料可以是氧化矽、氮化矽、氮氧化矽、碳氮化矽、上述的組合或類似者。
在第12圖中，源極/汲極區域90A和源極/汲極區域90B分別形成在第一阱62和第二阱64中。源極/汲極區域90A和源極/汲極區域90B的形成可以藉由佈植製程、蝕刻製程和接續的磊晶生長製程，或是類似者。源極/汲極區域90A形成在第一阱62中，使得LV裝置區域100中的閘極84設置在個別的相鄰成對源極/汲極區域90A之間。相似地，源極/汲極區域90B形成在第二阱64中，使得HV裝置區域200中的閘極84設置在個別的相鄰成對源極/汲極區域90B之間。在一些實施例中，閘極間隔物88用於使源極/汲極區域90A和源極/汲極區域90B與閘極84以適當的橫向距離分離，使得源極/汲極區域90A和源極/汲極區域90B不會造成最後FET中後續形成的閘極短路。
在源極/汲極區域90A和源極/汲極區域90B藉由磊晶生長製程所形成的實施例中，LV裝置區域100中的源極/汲極區域90A的形成可藉由遮蔽HV裝置區域200並蝕刻LV裝置區域100中第一阱62的源極/汲極區域以形成第一阱62中的凹槽。接著在凹槽中磊晶生長LV裝置區域100中的源極/汲極區域90A。源極/汲極區域90A可包括任何可接受的材料，例如矽、碳化矽、摻雜磷的碳化矽、磷化矽、矽鍺、摻雜硼的矽鍺、鍺、鍺錫或類似者。可選擇源極/汲極區域90A的材料以在個別通道區域87中施加應力，從而改善性能。在一些實施例中，LV裝置區域100中的源極/汲極區域90A可具有從個別第一阱62的表面凸起的表面，並可具有晶面(facet)。
HV裝置區域200中的源極/汲極區域90B的形成可藉由遮蔽LV裝置區域100並蝕刻HV裝置區域200中第二阱64的源極/汲極區域以形成第二阱64中的凹槽。接著在凹槽中磊晶生長HV裝置區域200中的源極/汲極區域90B。源極/汲極區域90B可包括任何可接受的材料，例如矽、碳化矽、摻雜磷的碳化矽、磷化矽、矽鍺、摻雜硼的矽鍺、鍺、鍺錫或類似者。可選擇源極/汲極區域90B的材料以在個別通道區域87中施加應力，從而改善性能。在一些實施例中，HV裝置區域200中的源極/汲極區域90B可具有從個別第二阱64的表面凸起的表面，並可具有晶面。
在源極/汲極區域90A和源極/汲極區域90B藉由佈植或磊晶生長形成的實施例中，源極/汲極區域90A和源極/汲極區域90B、第一阱62及/或第二阱64可使用摻雜劑佈植以形成源極/汲極區域，其類似於前文討論針對形成輕度摻雜源極/汲極區域的製程，並可隨後執行退火。源極/汲極區域90A和源極/汲極區域90B可具有雜質濃度介於約10 19atoms/cm 3和約10 21atoms/cm 3之間。源極/汲極區域90A和源極/汲極區域90B的n型及/或p型雜質可以是任何前文討論的雜質。在一些實施例中，源極/汲極區域90A和源極/汲極區域90B可以在生長期間原位摻雜。
進一步在第12圖中，矽化物區域92A和矽化物區域92B分別形成在LV裝置區域100和HV裝置區域200中的源極/汲極區域90A和源極/汲極區域90B上方。矽化物區域92A和矽化物區域92B的形成可藉由形成金屬層(未特別繪示)在源極/汲極區域90A和源極/汲極區域90B上方、執行退火以形成矽化物區域92A和矽化物區域92B，並移除金屬層的未反應部分。
在第13圖中，移除遮罩86並蝕刻閘極間隔物88。在一些實施例中，可執行平坦化製程(例如CMP)以將閘極84的頂表面與閘極間隔物88的頂表面齊平。在一些實施例中，可藉由一或多個適合的蝕刻製程移除遮罩86和蝕刻閘極間隔物88，其可以是各向同性或各向異性的。在一些實施例中，遮罩86和閘極間隔物88的蝕刻可以是乾式蝕刻製程，相對於閘極84、淺槽隔離區域58和矽化物區域92A和矽化物區域92B的材料，蝕刻製程對遮罩86和閘極間隔物88的材料具有高蝕刻選擇性。閘極間隔物88的頂表面可高於或低於閘極84的頂表面。蝕刻遮罩86和閘極間隔物88可減少相鄰閘極堆疊之間的開口的高寬比(例如，高度對寬度的比例)，其幫助後續層間介電質的沉積(例如下文關於第14圖的討論中的第一層間介電質96)。這減少了裝置缺陷並改善裝置性能。
在第14圖中，第一層間介電質(interlayer dielectric，ILD)96沉積在第13圖中繪示的結構上方。第一層間介電質96可以由介電材料形成，且可藉由任何適合的方法沉積，例如CVD、電漿增強化學氣相沉積(plasma-enhanced CVD，PECVD)或FCVD。介電材料可包括磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼矽酸鹽玻璃(borosilicate glass，BSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)、未摻雜的矽玻璃(undoped silicate glass，USG)或類似者。可使用藉由任何可接受的製程形成的其他絕緣材料形成。在一些實施例中，接觸蝕刻停止層(contact etch stop layer，CESL)94設置在第一層間介電質96以及矽化物區域92A和矽化物區域92B、淺槽隔離區域58、閘極間隔物88和閘極84之間。接觸蝕刻停止層94可包括相對於下方第一層間介電質96的材料具有低蝕刻速率的介電材料，例如氮化矽、氧化矽、氮氧化矽或類似者。
在第15圖中，執行平坦化製程(例如CMP)以將第一層間介電質96的頂表面與閘極84的頂表面齊平。在平坦化製程後，閘極84、閘極間隔物88、第一層間介電質96和接觸蝕刻停止層94的頂表面齊平。因此，通過第一層間介電質96和接觸蝕刻停止層94暴露閘極84的頂表面。
在第16圖中，藉由適合的蝕刻製程移除閘極84以形成凹槽102。亦可移除凹槽102中的部分第二閘極介電質82。在一些實施例中，只移除閘極84，而由凹槽102暴露保留的第二閘極介電質82。HV裝置區域200中的第一閘極介電質80可相對未蝕刻並保留。在一些實施例中，藉由各向異性乾式蝕刻製程移除閘極84。例如，蝕刻製程可包括使用反應氣體的乾式蝕刻製程，其中反應氣體選擇性蝕刻閘極84且少許或不蝕刻第一層間介電質96、閘極間隔物88或接觸蝕刻停止層94。LV裝置區域100中的凹槽102暴露及/或覆蓋第一阱62的通道區域87。HV裝置區域200的凹槽102暴露及/或覆蓋第一閘極介電質80。在移除期間，第二閘極介電質82在蝕刻閘極84時可做為蝕刻停止層。接著在移除閘極84後可選地移除第二閘極介電質82。
在第17圖中，為了替代閘極形成閘極介電層104和閘極電極106。閘極介電層104可包括一或多個層沉積在凹槽102中，例如在第一阱62的頂表面、第一閘極介電質80的頂表面和閘極間隔物88的側壁上。形成的閘極介電層104亦可沿著第一層間介電質96、接觸蝕刻停止層94和閘極間隔物88的頂表面延伸。在一些實施例中，閘極介電層104包括一或多個介電層，例如一或多個層的氧化矽、氮化矽、金屬氧化物、金屬矽化物或類似者。例如，在一些實施例中，閘極介電層104包括熱氧化或化學氧化形成的氧化矽以及其上層的高介電常數介電材料(例如鉿、鋁、鋯、鑭、錳、鋇、鈦、鉛的金屬氧化物或矽化物或是上述的組合)之間的介面層。閘極介電層104可包括具有介電常數大於約7.0的介電層。閘極介電層104的形成方法可包括分子束沉積(molecular beam deposition，MBD)、ALD、PECVD和類似者。在部分第二閘極介電質82保留在凹槽102中的實施例中，閘極介電層104可包括第二閘極介電質82的材料(例如，SiO 2)。
閘極電極106沉積在閘極介電層104上方並填充凹槽102的保留部分。閘極電極106可包括具有金屬的材料，例如氮化鈦、氧化鈦、氮化鉭、碳化鉭、鈷、釕、鋁、鎢、上述的組合或多層。儘管第17圖中繪示的是單層閘極電極106，閘極電極106可包括任何數量的內襯層、任何數量的功函數調整層和填充材料。在填充凹槽102後，可執行平坦化製程(例如CMP)以移除閘極介電層104和閘極電極106的多餘部分，其中多餘部分在第一層間介電質96的頂表面上方。閘極電極106和閘極介電層104的保留部分形成所得FET的替代閘極。LV裝置區域100中的閘極電極106和閘極介電層104以及HV裝置區域200中的閘極電極106、閘極介電層104和第一閘極介電質80可整體地稱為「閘極堆疊」。閘極堆疊可沿著第一阱62和第二阱64的通道區域87的頂表面延伸。
LV裝置區域100和HV裝置區域200中的閘極介電層104可同時形成，使得各區域中的閘極介電層104由相同的材料形成，並且閘極電極106可同時形成使得各區域中的閘極電極106由相同的材料形成。在一些實施例中，各區域中的閘極介電層104可由個別的製程形成，使得閘極介電層104可以是不同的材料，及/或各區域中的閘極電極106可由個別的製程形成，使得閘極電極106可以是不同的材料。當使用個別製程時，可使用多個遮罩步驟以遮蔽和暴露適當區域。
在第18圖中，閘極遮罩110形成在閘極堆疊上方。閘極遮罩110可設置在閘極間隔物88的相對部分之間。在一些實施例中，形成閘極遮罩110包括凹陷閘極堆疊的閘極介電層104和閘極電極106，使得凹槽形成在閘極堆疊的保留部分正上方以及閘極間隔物88的相對部分之間。接著將包括一或多個層的介電材料(例如氮化矽、氮氧化矽或類似者)的閘極遮罩110填充在凹槽中，隨後藉由平坦化製程移除延伸在第一層間介電質96上方的介電材料的多餘部分。
進一步在第18圖中，第二層間介電質108沉積在第一層間介電質96上方。在一些實施例中，第二層間介電質108是由可流動CVD製程形成的可流動薄膜。在一些實施例中，第二層間介電質108由介電材料形成，例如PSG、BSG、BPSG、USG或類似者，且可藉由任何適合的方法沉積，例如CVD、PECVD或類似者。隨後形成閘極接觸(例如下文關於第21A圖至第21C圖討論的閘極接觸130)可穿透第二層間介電質108和閘極遮罩110以接觸凹陷的閘極電極106的頂表面。
在第19A圖至第19C圖中，包括開口114、開口116和開口118的圖案化光阻112形成在第二層間介電質108上方。第19C圖繪示俯視圖並進一步繪示第19A圖和第19B圖所用的參考截面。截面A-A′在垂直於閘極堆疊的縱軸方向上延伸穿過開口114和開口116，並且第1圖至第19A圖、第20A圖和第21A圖繪示的截面圖是沿著截面A-A′所繪示。截面B-B′平行於截面A-A′且延伸穿過開口118，並且第19B圖、第20B圖和第21B圖繪示的截面圖是沿著截面B-B′所繪示。如第19B圖所繪示，閘極堆疊可延伸在經過第一阱62和第二阱64的側表面的淺槽隔離區域58上方。
圖案化光阻112的形成可藉由使用旋轉塗佈或類似者沉積光敏層在第二層間介電質108上方。接著可將光敏層暴露於圖案化能量源(例如具有圖案的光源)並顯影光敏層以移除光敏層的暴露或未暴露部分來圖案化光敏層，從而形成圖案化光阻112。暴露第二層間介電質108的開口114、開口116和開口118延伸穿過圖案化光阻112。圖案化光阻112的圖案對應於將形成在第二層間介電質108、第一層間介電質96、接觸蝕刻停止層94和閘極遮罩110中的接觸，這將在關於第21A圖至第21C圖的下文討論。
第19D圖和第19E圖繪示蝕刻負載效應(etching loading effect)，其將隨後用於以圖案化光阻112做為遮罩的第二層間介電質108、第一層間介電質96、接觸蝕刻停止層94和閘極遮罩110的蝕刻，防止過度蝕刻和損傷矽化物區域92A、源極/汲極區域90A和閘極電極106。在第19D圖中，提供基板202，且形成包括開口206的圖案化光阻204在基板202上方。基板202的材料可以相同於和類似於第二層間介電質108、第一層間介電質96及/或閘極遮罩110的材料。在一些實施例中，基板202可以由氧化物形成，例如氧化矽或類似者。圖案化光阻204可以由類似於和相同於形成圖案化光阻112的材料和製程所形成。在第19E圖中，使用圖案化光阻204做為遮罩的同時，開口206延伸進基板202。如第19E圖所繪示，當圖案化光阻204中的開口206的寬度增加，開口206延伸進基板202的深度增加。例如，各個開口206的寬度和開口206的深度的比例可在從約0.02至約1。針對開口114、開口116和開口118，可選擇開口114、開口116和開口118的寬度以控制開口114、開口116和開口118經由圖案化穿透的開口深度(例如關於第20A圖至第20C圖的下文中討論的開口120、開口122和開口124)，從而避免矽化物區域92A、源極/汲極區域90A和閘極電極106的過度蝕刻。
回到第19A圖至第19C圖，開口114可以形成具有寬度W 1，開口116可以形成具有寬度W 2，且開口118可以形成具有寬度W 3。寬度W 2可以大於寬度W 1和寬度W 3兩者。在一些實施例中，寬度W 2對寬度W 1的比例可在從約1.5至約50或從約1.5至約15的範圍內，且寬度W 2對寬度W 3的比例可在從約1.5至約50或從約1.5至約15的範圍內。在一些實施例中，寬度W 1可等於或大於寬度W 3。在一些實施例中，寬度W 1可在從約10 nm至約100 nm的範圍內，寬度W 2可在從約15 nm至約500 nm的範圍內，且寬度W 3可在從約10 nm至約100 nm的範圍內。如下文中關於第20A圖至第20C圖的進一步詳細討論，圖案化光阻112可做為遮罩用以延伸開口114、開口116和開口118，從而分別暴露矽化物區域92A、矽化物區域92B和閘極電極106。提供具有先前描述的寬度和關係的開口114、開口116和開口118可用於控制開口114、開口116和開口118延伸的深度，避免矽化物區域92A、源極/汲極區域90A和閘極電極106的過度蝕刻，同時允許矽化物區域92B的暴露。提供具有寬度W 2大於先前描述數值的開口116可能造成不希望的面積損失(area penalty)，需要形成更大的源極/汲極區域90B和矽化物區域92B，這可能減少裝置密度。提供具有寬度W 2小於先前描述數值的開口116可能不足以避免矽化物區域92A、源極/汲極區域90A和閘極電極106的過度蝕刻，並且可能造成裝置性能的減少。
在第20A圖至第20C圖中，圖案化光阻112做為遮罩用以蝕刻第二層間介電質108、第一層間介電質96、接觸蝕刻停止層94和閘極遮罩110，延伸開口114、開口116和開口118以分別形成開口120、開口122和開口124。開口120可蝕刻穿過LV裝置區域100中的第二層間介電質108、第一層間介電質96和接觸蝕刻停止層94並暴露矽化物區域92A。開口122可蝕刻穿過HV裝置區域200中的第二層間介電質108、第一層間介電質96和接觸蝕刻停止層94並暴露矽化物區域92B。開口124可蝕刻穿過LV裝置區域100和HV裝置區域200中的第二層間介電質108和閘極遮罩110並暴露LV裝置區域100和HV裝置區域200兩者中的閘極電極106。可使用任何可接受的蝕刻製程蝕刻第二層間介電質108、第一層間介電質96、接觸蝕刻停止層94和閘極遮罩110，例如反應離子蝕刻、中性粒子束蝕刻、類似者或上述的組合。蝕刻製程可以是各向異性的。
開口120、開口122和開口124可以同時蝕刻。由於開口114、開口116和開口118分別形成在具有先前描述的寬度W 1、寬度W 2和寬度W 3的圖案化光阻112中，開口120、開口122和開口124可以同時蝕刻且延伸至不同的深度。這允許各個矽化物區域92A、矽化物區域92B和閘極電極106的暴露，避免矽化物區域92A和閘極電極106的過度蝕刻。這改善了裝置性能並減少裝置缺陷。另外，不需要額外的遮蔽製程以形成具有不同高度的開口120、開口122和開口124。這減少了成本。
開口120可具有頂部的寬度W 1和第二層間介電質108的頂表面齊平，開口120的寬度W 1等於圖案化光阻112中開口114的寬度W 1。開口120可具有從約50 nm至約1000 nm的範圍內的高度H 2，以及與接觸蝕刻停止層94的底表面齊平且從約10 nm至約100 nm的範圍內的底部的寬度W 1′。開口122可具有頂部的寬度W 2和第二層間介電質108的頂表面齊平，開口122的寬度W 2等於圖案化光阻112中開口116的寬度W 2。開口122可具有從約100 nm至約1,500 nm的範圍內的高度H 3，以及與接觸蝕刻停止層94的底表面齊平且從約15 nm至約500 nm的範圍內的底部的寬度W 2′。開口124可具有頂部的寬度W 3和第二層間介電質108的頂表面齊平，開口124的寬度W 3等於圖案化光阻112中開口118的寬度W 3。開口124可具有從約50 nm至約1,000 nm的範圍內的高度H 4，以及與閘極遮罩110的底表面齊平且從約10 nm至約100 nm的範圍內的底部的寬度W 3′。高度H 3可大於高度H 2，且高度H 2可大於高度H 4。在一些實施例中，高度H 3對高度H 2的比例可在從約1.5至約50(H 3/H 2)的範圍內，且高度H 3對高度H 4的比例可在從約1.5至約50(H 3/H 4)的範圍內。在一些實施例中，寬度W2′可等於或大於寬度W1′。形成具有寬度W2′大於寬度W1′的開口122可減少後續形成於開口122中的接觸的接觸電阻，這可改善裝置性能。
在第21A圖至第21C圖中，移除圖案化光阻112，並分別形成LV接觸126、HV接觸128和閘極接觸130在開口120、開口122和開口124中。第21C圖繪示移除第二層間介電質108和第一層間介電質96的俯視圖以示出其下方的結構。可藉由任何可接受的灰化或剝離製程移除圖案化光阻112，例如使用氧氣電漿或類似者。LV接觸126、HV接觸128和閘極接觸130的形成可藉由在開口120、開口122和開口124中沉積內襯層(未特別繪示)，例如擴散阻障層、黏附層或類似者，且沉積導電材料在內襯層上方並填充開口120、開口122和開口124。內襯層可包括鈦、氮化鈦、鉭、氮化鉭或類似者。導電材料可以是銅、銅合金、銀、金、鎢、鈷、鋁、鎳或類似者。可執行平坦化製程(例如CMP)以從第二層間介電質108的表面移除多餘的材料。保留的內襯層和導電材料形成LV接觸126、HV接觸128和閘極接觸130。LV接觸126穿過矽化物區域92A物理性且電性耦接至源極/汲極區域90A。HV接觸128穿過矽化物區域92B物理性且電性耦接至源極/汲極區域90B。閘極接觸130物理性且電性耦接至閘極電極106。LV接觸126、HV接觸128和閘極接觸130可在不同的製程中形成，或是可在相同製程中形成。
LV接觸126、HV接觸128和閘極接觸130可分別具有和開口120、開口122和開口124相同的尺寸。例如，LV接觸126可具有寬度W 1、寬度W 1′和高度H 2，HV接觸128可具有寬度W 2、寬度W 2′和高度H 3，且閘極接觸130可具有寬度W 3、寬度W 3′和高度H 4。閘極接觸130的寬度W 3和高度H 4可相同於LV裝置區域100和HV裝置區域200。寬度W 1對高度H 2的比例可在從約0.01至約0.2的範圍內，寬度W 2對高度H 3的比例可在從約0.01至約0.2的範圍內，且寬度W 3對高度H 4的比例可在從約0.01至約0.2的範圍內。
第21D圖繪示HV接觸128和矽化物區域92B之間的接觸電阻(contact resistance，Rc)的累積機率函數。折線300繪示的實施例中，形成的HV接觸128具有寬度大於LV接觸126的寬度。折線302繪示的實施例中，形成的HV接觸128具有寬度等於LV接觸126的寬度。如第21D圖所繪示，提供具有越大寬度的HV接觸128會減少HV接觸128的接觸電阻並減少HV接觸128的接觸電阻的變異。具體地，折線300繪示的實施例的接觸電阻比折線302繪示的實施例的接觸電阻低15%或更多百分比。這改善裝置性能並減少裝置缺陷。
本公開的實施例可實現多種優勢。例如，在圖案化光阻112中形成具有不同寬度的開口114、開口116和開口118允許同時形成開口120、開口122和開口124，且避免設置高於矽化物區域92B的矽化物區域92A、源極/汲極區域90A和閘極電極106的過度蝕刻。這避免裝置的缺陷、改善裝置的性能，且減少圖案化開口120、開口122和開口124所需的遮罩數量以減少成本。另外，可形成具有更大寬度的HV接觸128，減少接觸電阻並進一步改善裝置性能。
本文揭露的平面FET實施例也可應用於鰭式裝置(例如鰭式場效應電晶體)、奈米結構裝置(例如奈米結構(例如奈米片、奈米導線、閘極全環繞或類似者)場效應電晶體)或類似者。在奈米結構場效應電晶體的實施例中，由奈米結構替代鰭片，奈米結構的形成可藉由圖案化通道層和犧牲層交替的堆疊。虛擬閘極堆疊和源極/汲極區域的形成方式類似於上文描述的實施例。移除虛擬閘極堆疊後，可部分或完全移除通道區域中的犧牲層。替代閘極結構的形成方式類似於上文描述的實施例，替代閘極結構可部分或完全填入移除犧牲層後留下的開口，且替代閘極結構可部分或完全環繞奈米結構場效應電晶體裝置的通道區域中的通道層。接觸替代閘極結構和源極/汲極區域的層間介電質和接的形成方式類似於上文描述的實施例。
根據本公開的實施例，一種半導體裝置包括在相鄰於第一源極/汲極區域的半導體基板中的第一通道區域、在第一通道區域上方的第一閘極堆疊、在相鄰於第二源極/汲極區域的半導體基板中的第二通道區域，其中第二通道區域的頂表面設置低於第一通道區域的頂表面。半導體裝置包括在第二通道區域上方的第二閘極堆疊、在第一閘極堆疊、第二閘極堆疊、第一源極/汲極區域和第二源極/汲極區域上方的層間介電質、延伸穿過層間介電質並電性耦接至第一源極/汲極區域的第一源極/汲極接觸，其中第一源極/汲極接觸具有第一寬度和第一高度。半導體裝置包括延伸穿過層間介電質並電性耦接至第二源極/汲極區域的第二源極/汲極接觸，其中第二源極/汲極接觸具有大於第一寬度的第二寬度和大於第一高度的第二高度。在一個實施例中，半導體裝置進一步包括電性耦接至第一閘極堆疊的第一閘極接觸，以及電性耦接至第二閘極堆疊的第二閘極接觸，第一閘極接觸具有第三寬度和第三高度，第二閘極接觸具有等於第三寬度的第四寬度和等於第三高度的第四高度。在一個實施例中，第二寬度大於各個第三寬度和第四寬度，且其中第二高度大於各個第三高度和第四高度。在一個實施例中，第一源極/汲極接觸、第二源極/汲極接觸、第一閘極接觸和第二閘極接觸的頂表面彼此齊平，第二源極/汲極接觸的底表面設置低於第一源極/汲極接觸的底表面，且第一源極/汲極接觸的底表面設置低於第一閘極接觸和第二閘極接觸的底表面。在一個實施例中，第一寬度等於各個第三寬度和第四寬度。在一個實施例中，第一高度大於各個第三高度和第四高度。在一個實施例中，第二寬度對第一寬度的比例介於1.5至50。
根據本公開的實施例，一種半導體裝置包括第一電晶體，第一電晶體包括在半導體基板上方具有第一高度的第一閘極堆疊、相鄰第一閘極堆疊的第一源極/汲極區域、電性耦接至第一閘極堆疊的第一閘極接觸、電性耦接至第一源極/汲極區域的第一源極/汲極接觸，第一閘極接觸的頂表面具有第一寬度，第一源極/汲極接觸的頂表面具有大於第一寬度的第二寬度。半導體裝置包括第二電晶體，第二電晶體包括在半導體基板上方具有第二高度小於第一高度的第二閘極堆疊、相鄰第二閘極堆疊的第二源極/汲極區域、電性耦接至第二源極/汲極區域的第二源極/汲極接觸，第二源極/汲極接觸的頂表面具有小於第二寬度的第三寬度。在一個實施例中，第二寬度對第一寬度的比例介於1.5至50，且第二寬度對第三寬度的比例介於1.5至50。在一個實施例中，第一電晶體進一步包括第一通道區域，第一閘極堆疊包括第一介電材料接觸第一通道區域，第二電晶體進一步包括第二通道區域，且其中第二閘極堆疊包括第一介電材料由閘極氧化物層與第二通道區域分隔。在一個實施例中，在垂直於半導體基板的主表面的方向上，第一通道區域的頂表面設置以第一距離高於第二通道區域的頂表面，且閘極氧化物層的厚度等於第一距離。在一個實施例中，第一閘極堆疊的頂表面與第二閘極堆疊的頂表面齊平。在一個實施例中，第一源極/汲極接觸的底表面具有第四寬度大於第二源極/汲極接觸的底表面的第五寬度。在一個實施例中，第一源極/汲極接觸的頂表面、第二源極/汲極接觸的頂表面和第一閘極接觸的頂表面彼此齊平，第一源極/汲極接觸具有第一高度大於第二源極/汲極接觸的第二高度，且第二高度大於第一閘極接觸的第三高度。
根據本公開的實施例，一種形成半導體裝置的方法包括在半導體基板上方形成第一電晶體和第二電晶體，第一電晶體包括第一閘極堆疊和相鄰於第一閘極堆疊的第一源極/汲極區域，第二電晶體包括第二閘極堆疊和相鄰於第二閘極堆疊的第二源極/汲極區域。方法包括在第一電晶體和第二電晶體上方形成層間介電質、在層間介電質上方沉積光阻、圖案化光阻以形成圖案化光阻，圖案化光阻包括在第一源極/汲極區域正上方的第一開口、在第二源極/汲極區域正上方的第二開口，以及在第一閘極堆疊正上方的第三開口，第一開口具有第一寬度，第二開口具有第二寬度，第三開口具有第三寬度，第一寬度大於各個第二寬度和第三寬度。方法包括使用圖案化光阻做為遮罩蝕刻層間介電質，以及形成電性耦接至第一源極/汲極區域的第一接觸、電性耦接至第二源極/汲極區域的第二接觸和電性耦接至第一閘極堆疊的第三接觸，第一接觸具有第一高度大於各個第二接觸的第二高度和第三接觸的第三高度。在一個實施例中，形成第一電晶體和第二電晶體包括相對於半導體基板的第二區域，凹陷半導體基板的第一區域，第一電晶體形成在第一區域中且第二電晶體形成在第二區域中。在一個實施例中，形成第一電晶體和第二電晶體進一步包括在第一區域和第二區域上方形成閘極氧化物層，以及從第二區域移除閘極氧化物層，第一閘極堆疊包括閘極氧化物層的保留部分。在一個實施例中，方法進一步包括平坦化第一閘極堆疊、第二閘極堆疊和層間介電質的頂表面。在一個實施例中，形成第一接觸、第二接觸和第三接觸進一步包括平坦化第一接觸、第二接觸、第三接觸和層間介電質的頂表面。在一個實施例中，第三寬度等於第二寬度。
前面概述一些實施例的特徵，使得本領域技術人員可更好地理解本公開的觀點。本領域技術人員應該理解，他們可以容易地使用本公開作為設計或修改其他製程和結構的基礎，以實現相同的目的和/或實現與本文介紹之實施例相同的優點。本領域技術人員還應該理解，這樣的等同構造不脫離本公開的精神和範圍，並且在不脫離本公開的精神和範圍的情況下，可以進行各種改變、替換和變更。
50:基板 51:分隔層 52:襯墊層 54:遮罩層 56:溝槽 58:淺槽隔離區域 60:第二圖案化遮罩 62:第一阱 64:第二阱 66:第一閘極介電層 70:第二閘極介電層 72:閘極層 74:遮罩層 80:第一閘極介電質 82:第二閘極介電質 84:閘極 86:遮罩 87:通道區域 88:閘極間隔物 90A,90B:源極/汲極區域 92A,92B:矽化物區域 94:接觸蝕刻停止層 96:第一層間介電質 100:LV裝置區域 102:凹槽 104:閘極介電層 106:閘極電極 108:第二層間介電質 110:閘極遮罩 112:圖案化光阻 114,116,118:開口 120,122,124:開口 126:LV接觸 128:HV接觸 130:閘極接觸 200:HV裝置區域 202:基板 204:圖案化光阻 206:開口 300,302:折線 A-A′,B-B′:截面 H 1,H 2,H 3,H 4:高度 W 1,W 1′,W 2,W 2′,W 3,W 3′:寬度
當結合附圖閱讀時，從以下詳細描述中可以最好地理解本公開的各方面。應注意，根據工業中的標準方法，各種特徵未按比例繪製。實際上，為了清楚地討論，可任意增加或減少各種特徵的尺寸。 第1圖、第2圖、第3圖、第4圖、第5圖、第6圖、第7圖、第8圖、第9圖、第10圖、第11圖、第12圖、第13圖、第14圖、第15圖、第16圖、第17圖、第18圖、第19A圖、第19B圖、第19C圖、第19D圖、第19E圖、第20A圖、第20B圖、第20C圖、第21A圖、第21B圖和第21C圖是根據一些實施例的場效應電晶體的製造中間階段的截面圖和俯視圖。 第21D圖繪示根據一些實施例的接觸的材料性質圖表。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
50:基板
58:淺槽隔離區域
62:第一阱
64:第二阱
80:第一閘極介電質
87:通道區域
88:閘極間隔物
90A,90B:源極/汲極區域
92A,92B:矽化物區域
94:接觸蝕刻停止層
96:第一層間介電質
100:LV裝置區域
104:閘極介電層
106:閘極電極
108:第二層間介電質
110:閘極遮罩
126:LV接觸
128:HV接觸
200:HV裝置區域
H2,H3:高度
W1,W1',W2,W2':寬度

Claims (20)

  1. 一種半導體裝置，包括： 一第一通道區域，在相鄰於一第一源極/汲極區域的一半導體基板中； 一第一閘極堆疊，在該第一通道區域上方； 一第二通道區域，在相鄰於一第二源極/汲極區域的該半導體基板中，其中該第二通道區域的一頂表面設置低於該第一通道區域的一頂表面； 一第二閘極堆疊，在該第二通道區域上方； 一層間介電質，在該第一閘極堆疊、該第二閘極堆疊、該第一源極/汲極區域和該第二源極/汲極區域上方； 一第一源極/汲極接觸，延伸穿過該層間介電質並電性耦接至該第一源極/汲極區域，該第一源極/汲極接觸具有一第一寬度和一第一高度；以及 一第二源極/汲極接觸，延伸穿過該層間介電質並電性耦接至該第二源極/汲極區域，該第二源極/汲極接觸具有大於該第一寬度的一第二寬度和大於該第一高度的一第二高度。
  2. 如請求項1所述之半導體裝置，進一步包括： 一第一閘極接觸，電性耦接至該第一閘極堆疊；以及 一第二閘極接觸，電性耦接至該第二閘極堆疊，該第一閘極接觸具有一第三寬度和一第三高度，該第二閘極接觸具有等於該第三寬度的一第四寬度和等於該第三高度的一第四高度。
  3. 如請求項2所述之半導體裝置，其中該第二寬度大於各個該第三寬度和該第四寬度，且其中該第二高度大於各個該第三高度和該第四高度。
  4. 如請求項2所述之半導體裝置，其中該第一源極/汲極接觸、該第二源極/汲極接觸、該第一閘極接觸和該第二閘極接觸的頂表面彼此齊平，其中該第二源極/汲極接觸的一底表面設置低於該第一源極/汲極接觸的一底表面，且其中該第一源極/汲極接觸的該底表面設置低於該第一閘極接觸和該第二閘極接觸的底表面。
  5. 如請求項2所述之半導體裝置，其中該第一寬度等於各個該第三寬度和該第四寬度。
  6. 如請求項5所述之半導體裝置，其中該第一高度大於各個該第三高度和該第四高度。
  7. 如請求項1所述之半導體裝置，其中該第二寬度對該第一寬度的比例介於1.5至50。
  8. 一種半導體裝置，包括： 一第一電晶體，包括： 一第一閘極堆疊，在一半導體基板上方，該第一閘極堆疊具有一第一高度； 一第一源極/汲極區域，相鄰該第一閘極堆疊； 一第一閘極接觸，電性耦接至該第一閘極堆疊，該第一閘極接觸的一頂表面具有一第一寬度；以及 一第一源極/汲極接觸，電性耦接至該第一源極/汲極區域，該第一源極/汲極接觸的一頂表面具有大於該第一寬度的一第二寬度；以及 一第二電晶體，包括： 一第二閘極堆疊，在該半導體基板上方，該第二閘極堆疊具有小於該第一高度的一第二高度； 一第二源極/汲極區域，相鄰該第二閘極堆疊；以及 一第二源極/汲極接觸，電性耦接至該第二源極/汲極區域，該第二源極/汲極接觸的一頂表面具有小於該第二寬度的一第三寬度。
  9. 如請求項8所述之半導體裝置，其中該第二寬度對該第一寬度的比例介於1.5至50，且該第二寬度對該第三寬度的比例介於1.5至50。
  10. 如請求項8所述之半導體裝置，其中該第一電晶體進一步包括一第一通道區域，其中該第一閘極堆疊包括一第一介電材料接觸該第一通道區域，其中該第二電晶體進一步包括一第二通道區域，且其中該第二閘極堆疊包括該第一介電材料由一閘極氧化物層與該第二通道區域分隔。
  11. 如請求項10所述之半導體裝置，其中在垂直於該半導體基板的一主表面的方向上，該第一通道區域的一頂表面設置以一第一距離高於該第二通道區域的一頂表面，且其中該閘極氧化物層的厚度等於該第一距離。
  12. 如請求項8所述之半導體裝置，其中該第一閘極堆疊的一頂表面與該第二閘極堆疊的一頂表面齊平。
  13. 如請求項8所述之半導體裝置，其中該第一源極/汲極接觸的一底表面具有一第四寬度大於該第二源極/汲極接觸的一底表面的一第五寬度。
  14. 如請求項8所述之半導體裝置，其中該第一源極/汲極接觸的該頂表面、該第二源極/汲極接觸的該頂表面和該第一閘極接觸的該頂表面彼此齊平，其中該第一源極/汲極接觸具有一第一高度大於該第二源極/汲極接觸的一第二高度，且其中該第二高度大於該第一閘極接觸的一第三高度。
  15. 一種形成半導體裝置的方法，包括： 在一半導體基板上方形成一第一電晶體和一第二電晶體，該第一電晶體包括一第一閘極堆疊和相鄰於該第一閘極堆疊的一第一源極/汲極區域，該第二電晶體包括一第二閘極堆疊和相鄰於該第二閘極堆疊的一第二源極/汲極區域； 在該第一電晶體和該第二電晶體上方形成一層間介電質； 在該層間介電質上方沉積一光阻； 圖案化該光阻以形成一圖案化光阻，該圖案化光阻包括在該第一源極/汲極區域正上方的一第一開口、在該第二源極/汲極區域正上方的一第二開口，以及在該第一閘極堆疊正上方的一第三開口，該第一開口具有一第一寬度，該第二開口具有一第二寬度，該第三開口具有一第三寬度，其中該第一寬度大於各個該第二寬度和該第三寬度； 使用該圖案化光阻做為遮罩，蝕刻該層間介電質；以及 形成電性耦接至該第一源極/汲極區域的一第一接觸、電性耦接至該第二源極/汲極區域的一第二接觸和電性耦接至該第一閘極堆疊的一第三接觸，該第一接觸具有一第一高度大於各個該第二接觸的一第二高度和該第三接觸的一第三高度。
  16. 如請求項15所述之方法，其中形成該第一電晶體和該第二電晶體包括相對於該半導體基板的一第二區域，凹陷該半導體基板的一第一區域，其中該第一電晶體形成在該第一區域中且該第二電晶體形成在該第二區域中。
  17. 如請求項16所述之方法，其中形成該第一電晶體和該第二電晶體進一步包括： 在該第一區域和該第二區域上方形成一閘極氧化物層；以及 從該第二區域移除該閘極氧化物層，其中該第一閘極堆疊包括該閘極氧化物層的保留部分。
  18. 如請求項17所述之方法，進一步包括平坦化該第一閘極堆疊、該第二閘極堆疊和該層間介電質的頂表面。
  19. 如請求項15所述之方法，其中形成該第一接觸、該第二接觸和該第三接觸進一步包括平坦化該第一接觸、該第二接觸、該第三接觸和該層間介電質的頂表面。
  20. 如請求項15所述之方法，其中該第三寬度等於該第二寬度。
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