CN106910737B - 半导体元件及其形成方法 - Google Patents

半导体元件及其形成方法 Download PDF

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CN106910737B
CN106910737B CN201510974251.4A CN201510974251A CN106910737B CN 106910737 B CN106910737 B CN 106910737B CN 201510974251 A CN201510974251 A CN 201510974251A CN 106910737 B CN106910737 B CN 106910737B
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layer
gate
substrate
forming
semiconductor device
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CN106910737A (zh
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李信宏
陈冠全
李年中
李文芳
王智充
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US15/057,130 priority patent/US9653460B1/en
Priority to US15/475,097 priority patent/US9972539B2/en
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Abstract

本发明公开一种半导体元件及其形成方法。其中，该半导体元件包含基底、第一栅极以及第二栅极。该第一栅极是设置在该基底之上，并且包含第一间隙壁以及依序堆叠于该基底上的栅极绝缘层、多晶硅层、第一金属硅化物层以及帽盖层，该第一间隙壁环绕该栅极绝缘层、该多晶硅层、该第一金属硅化物层以及该帽盖层。该第二栅极同样是设置在该基底之上，并且包含第二间隙壁以及依序堆叠于该基底上的高介电常数介电层、功函数金属层以及导电层。该第二间隙壁环绕该高介电常数介电层、该功函数金属层以及该导电层。

Description

半导体元件及其形成方法
技术领域
本发明涉及一种半导体元件及其形成方法，特别是涉及一种具有高压金属氧化物半导体晶体管(high voltage metal-oxide semiconductor transistor)的半导体元件及其形成方法。
背景技术
高压元件是使用在电子产品中需要以高电压操作的部分，如闪存存储器(flashmemory)或平面显示器(flat panel display)的控制电路，用以维持高电压环境下的正常运作，其中，高压金属氧化物半导体(high-voltage metal-oxide semiconductor,HV-MOS)晶体管因具有开关的特性，而被广泛地应用在中央处理器电源供应(CPU power supply)、电管理系统(power management system)、直流/交流转换器(AC/DC converter)、液晶显示器(liquid crystal display,LCD)与等离子体电视驱动器、车用电子、电脑周边、小尺寸直流马达控制器以及消费性电子产品等领域。
目前高压元件和低压元件相容的半导体制作工艺中，其低压元件多采用0.28微米的制作工艺制作。然而，随着元件尺寸日益缩小，除了制作工艺复杂度增加之外，如何能维持元件的品质与可靠性也为现今半导体产业的一大课题。因此，亟需改良高压金属氧化物半导体晶体管现有的形成方式，以符合实务上的需求。
发明内容
本发明的一目的在于提供一种半导体元件及其形成方法，其可更有效地控制栅极的高度，因而可得到更佳的元件效能。
为达上述目的，本发明的一实施例提供一种半导体元件，其包含一基底、一第一栅极以及一第二栅极。该第一栅极是设置在该基底之上，并且包含第一间隙壁以及依序堆叠于该基底上的一栅极绝缘层、一多晶硅层、一第一金属硅化物层以及一帽盖层，该第一间隙壁环绕该栅极绝缘层、该多晶硅层、该第一金属硅化物层以及该帽盖层。该第二栅极同样是设置在该基底之上并且包含第二间隙壁以及依序堆叠于该基底上的一高介电常数介电层、一功函数金属层以及一导电层。该第二间隙壁环绕该高介电常数介电层、该功函数金属层以及该导电层。
为达上述目的，本发明的另一实施例提供一种半导体元件的形成方法，其包含以下步骤。首先，在一基底上形成一第一栅极，其中该第一栅极包含第一间隙壁以及依序堆叠于该基底上的一栅极绝缘层以及一多晶硅层，该第一间隙壁环绕该栅极绝缘层以及该多晶硅层。接着，部分移除该多晶硅层，以形成一沟槽。然后，在该沟槽内的该多晶硅层上以及该第一栅极两侧的该基底上分别形成一金属硅化物层。最后，在该多晶硅层上的金属硅化物层上形成一帽盖层，以填满该沟槽。
利用本发明的形成方式可有效率地在不同的晶体管区内形成临界尺寸(dimension)不同的栅极结构，并有效控制其栅极高度(gate height)，以避免该栅极结构在后续制作工艺中发生凹陷(dishing)的情形，而影响整体效能。由此，位于该二晶体管区内的栅极结构可分别具有不同的临界电压，以在半导体元件中形成高临界电压(highthreshold voltage,HVT)与低临界电压(low threshold voltage, LVT)，或是高临界电压与标准临界电压(standard voltage threshold,SVT)的P型晶体管或N型晶体管等。
附图说明
图1至图9为本发明优选实施例中形成半导体元件的方法的步骤剖面示意图。
主要元件符号说明
101、102 晶体管区
200 浅沟隔离
210 图案化光致抗蚀剂层
220 接触洞蚀刻停止材料层
221 接触洞蚀刻停止层
230 层间介电材料层
231 层间介电层
300 基底
301、302 栅极结构
310 沟槽
311、312 栅极绝缘层
313 栅极
314 虚置栅极
315、316 帽盖层
317、318 间隙壁
317a、318a 第一间隙壁
317b、318b 第二间隙壁
319、320 源极/漏极
321、322、323 金属硅化物层
324 高介电常数介电层
325 帽盖层
326 功函数金属层
328 导电层
330 栅极沟槽
H1、H2 高度
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的数个优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
请参考图1至图9，所绘示者为本发明一优选实施例中半导体元件的形成方法示意图。首先，如图1所示，提供一基底300。基底300例如是一硅基底、一含硅基底或一硅覆绝缘(silicon-on-insulator, SOI)基底等半导体基底。在一实施例中，基底300上可形成有至少一个浅沟隔离(shallow trenchisolation,STI)200，以在基底300定义出二个晶体管区101、102，优选为相同导电型式的晶体管区，例如都是PMOS晶体管区或都是NMOS晶体管区，且二个晶体管区101、102分别预定为后续制作不同临界电压的栅极结构。然而，在其他实施样态中，二个晶体管区101、102也可选择包含不同导电型式的晶体管区，例如晶体管区101为PMOS晶体管区而晶体管区102为NMOS晶体管区。
具体来说，基底300的二个晶体管区101、102分别形成有栅极结构301、302。栅极结构301包含一栅极绝缘层(gate insulating layer)311、一栅极313、一帽盖层(cappinglayer)315、一间隙壁(spacer)317以及源极/漏极319。其中，栅极绝缘层311例如可包含二氧化硅(SiO2)、氮化硅(SiN)或氮氧化硅(SiON)等；栅极313例如包含一多晶硅(polysilicon)层，其可包含不具有任何掺质(undoped)的多晶硅材料、具有掺质的多晶硅材料或非晶硅材料等，但也可以是由上述材料的组合；帽盖层315则例如包含二氧化硅、氮化硅、碳化硅(SiC)、碳氮化硅(SiCN)或上述材料的组合等。间隙壁317可选择包含复合膜层的结构，例如由一第一间隙壁317a及一第二间隙壁317b所组成，且第一及第二间隙壁317a、317b可包含高温氧化硅层(high temperature oxide,HTO)、氮化硅、氧化硅、氮氧化硅或使用六氯二硅烷(hexachlorodisilane,Si2Cl6)形成的氮化硅(HCD-SiN)，如图1所示。然而，在另一实施例中，该间隙壁也可选择具单一膜层的结构(未绘示)。
另一方面，栅极结构302则包含一栅极绝缘层312、一虚置栅极314、一帽盖层316、一间隙壁318以及源极/漏极320。其中，栅极绝缘层312、虚置栅极314及帽盖层316可分别包含类似于栅极绝缘层311、栅极313及帽盖层315的材质，但不以此为限。而间隙壁318可同样选择包含复合膜层的结构，例如由一第一间隙壁318a及一第二间隙壁318b所组成，且其组成材质大体上与间隙壁317相同，如图1所示，但不以此为限。
在本发明的一实施例中，栅极结构301、302的形成步骤，例如包含在基底300的晶体管区101及、102分别形成一第一绝缘材料层(未绘示)及一第二绝缘材料层(未绘示)。例如是选择进行一热氧化制作工艺，以在基底300的晶体管区101上形成该第一绝缘材料层，其中，该第一绝缘材料层具有一定的厚度，例如是约为95至140埃(Angstroms)但不以此为限。并且，该第一绝缘材料层一部分，例如是下半部(大体上约占整体厚度的二分之一)，是形成在基底300内，如图1所示。另一方面，进行一沉积制作工艺，以在基底300的晶体管区102上形成该第二绝缘材料层，该第二绝缘材料层优选具有相同于该第一绝缘材料层的材质，并具有小于该第一绝缘材料层的厚度，如图1所示。然而，在另一实施例中，该第二绝缘材料层也可选择具有不同于该第一绝缘材料层的材质，例如包含高介电常数(highdielectric constant,high-k)材质。
然后，依序在基底300上形成相互堆叠的一栅极材料层(未绘示)及一帽盖材料层(未绘示)，再进行一图案化制作工艺，进而在晶体管区101、102内分别形成一栅极堆叠结构(未绘示)。接着，形成分别环绕该栅极堆叠结构的第一间隙壁317a、318a，再于该栅极堆叠结构两侧的基底300中形成源极/漏极319、320，最后再于第一间隙壁317a、318a的侧壁上分别形成第二间隙壁317b、318b，由此即形成本实施例的栅极结构301、302。
在本实施例中，所形成的栅极结构301、302大体上具有相同的一高度H1，例如是约为500至550埃，并且优选是具有不同临界尺寸的通道区(channel region,未绘示)，如图2所示。举例来说，第一栅极301例如是具有约为300至350纳米(nanometer,nm)的通道区，而第二栅极302则具有约为28纳米的通道区，但不以此为限。此外，本领域者应可轻易了解，本发明的栅极结构也可能以其他方式形成，并不限于前述的制作步骤。举例来说，在另一实施例中，基底300还可以形成有至少一鳍状结构(未绘示)，而栅极结构302则可部分形成在该鳍状结构之上(未绘示)。或者，在另一实施例中，也可选择在形成栅极结构301、302后，进行一应变存储制作工艺(stress memorization technique,SMT)，例如是额外在基底300上形成一应力应变层(stress memorization layer,未绘示)，再进行一热制作工艺；或是在基底300内额外形成一外延层(epitaxial layer,未绘示)，以提供所需应力。
在形成分别位于晶体管区101、102的栅极结构301、302之后，可形成一图案化光致抗蚀剂层210，覆盖大部分的基底300及栅极结构302，而仅暴露出栅极结构301，如图2所示。而后，则可以图案化光致抗蚀剂层210作为蚀刻掩模，进行一蚀刻制作工艺，例如是干蚀刻、湿蚀刻或依序进行干蚀刻及湿蚀刻制作工艺，利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(tetramethylammonium hydroxide,TMAH)等蚀刻溶液来去除帽盖层315以及部分的栅极313，而形成一沟槽310。也就是说，该蚀刻制作工艺可使栅极313被暴露出，并被进一步蚀刻，直至栅极313的高度H2小于虚置栅极314的高度，例如是约为380埃至400埃，如图3所示。
在完全移除图案化光致抗蚀剂层210后，进行一金属硅化物制作工艺(silicidation)，以在栅极313、源极/漏极319、320的顶表面上分别形成金属硅化物层321、323、322，如图4所示。需注意的是，在本实施例中，在进行该金属硅化物制作工艺之前，先形成一金属硅化物阻挡(silicide-block,SAB)层(未绘示)，例如是包含氮化硅，以阻挡不需形成金属硅化物层的区域。该金属硅化物制作工艺例如包含全面地形成一金属层(未绘示)，例如是由钴(cobalt,Co)、钛(titanium,Ti)、镍(nickel,Ni)或钼(molybdenum,Mo)，接着进行一快速热处理制作工艺(rapid thermal processing,RTP)，使该金属层与栅极313、源极/漏极319、320的硅原子发生反应，而分别形成金属硅化物层321、323、322。其中，金属硅化物层321具有低于间隙壁317的顶表面，如图4所示。
然后，完全移除该金属硅化物阻挡层。例如是进行另一蚀刻制作工艺，例如是干蚀刻、湿蚀刻或依序进行干蚀刻及湿蚀刻制作工艺，以移除该金属硅化物阻挡层。需注意的是，该金属硅化物阻挡层优选具有相同于帽盖层316的材质，由此，在移除该金属硅化物阻挡层时，可同时移除栅极结构302的帽盖层316，如图4所示。此外，在移除该金属硅化物阻挡层及帽盖层316时，部分的间隙壁317、318也会一并被移除，如图4所示。
然后，依序在基底300上全面地形成一接触洞蚀刻停止材料层(contact etchingstop material layer)220以及一层间介电材料层(interlayer dielectric materiallayer)230，分别如图5及图6所示。需注意的是，因在前述蚀刻制作工艺中，帽盖层316以及部分的间隙壁317、318已被移除，因此，接触洞蚀刻停止材料层220可直接覆盖在栅极结构302的虚置栅极314上，并且接触洞蚀刻停止材料层220的一部分可填入沟槽310内，并覆盖在金属硅化物层321之上，如图5所示。
之后，则进行一平坦化制作工艺，例如是化学机械研磨(chemical mechanicalpolishing,CMP)及/或回蚀刻(etching back)制作工艺，以平坦化层间介电材料层230及接触洞蚀刻停止材料层220，进而形成接触洞蚀刻停止层(contact etching stop layer,CESL)221及层间介电层231，以分别暴露出栅极结构301、302的顶部。具体来说，接触洞蚀刻停止层221及层间介电层231是直接覆盖在栅极结构301、302的间隙壁317、317以及金属硅化物层323、322上，并且，在进行该平坦化制作工艺时，填入沟槽310内的接触洞蚀刻停止材料层220即可形成一帽盖层325，覆盖在金属硅化物层321之上，如图7所示。由此，层间介电层231的顶表面即可与栅极结构301的帽盖层325、栅极结构302的虚置栅极314齐平，如图7所示。
后续，则可继续进行另一蚀刻制作工艺，例如是干蚀刻、湿蚀刻或依序进行干蚀刻及湿蚀刻制作工艺，利用氨水或氢氧化四甲铵等蚀刻溶液来去除虚置栅极314及栅极绝缘层312，以在层间介电层231内形成一栅极沟槽330，如图8所示。
最后，即可依序在栅极沟槽330中分别形成一介质层(未绘示)、U型的一高介电常数介电层324、U型的一底部金属阻隔层(未绘示)、U型的一功函数金属层326以及U型的一顶部金属阻隔层(未绘示)。最后，则填入导电层328。其形成方法，例如是包含在基底300的晶体管区102上形成一介质材料层(未绘示)，并且全面性地形成一高介电常数介电材料层(未绘示)、一底部金属阻隔材料层(未绘示)、一功函数材料层(未绘示)、一顶部金属阻隔材料层(未绘示)及导电材料层(未绘示)，再进行一平坦化制作工艺，例如是化学机械研磨或蚀刻制作工艺，移除位于层间介电层231表面上的该介质材料层、该高介电常数介电材料层、该底部金属阻隔材料层、该功函数材料层、该导电材料层及该顶部金属阻隔材料层，但不以此为限。
在一实施例中，该介质层例如是包含氧化硅或氮化硅。高介电常数介电层324例如是包含介电常数大于4的介电材料，例如是选自氧化铪(hafnium oxide,HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)或氧化铝(aluminum oxide,Al2O3)等。该底部及顶部金属阻隔层可选择为一单层或双层结构，例如是包含钛(Ti)、钽(Ta)、氮化钛(TiN)或氮化钽(TaN)，但不限于此。功函数金属层326的组成优选依据适用的晶体管型态而不同材质。例如，若晶体管为N型晶体管，功函数金属层326可包含功函数为3.9电子伏特(eV)至4.3电子伏特的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)等，但不以此为限。反之，若晶体管为P型晶体管，功函数金属层326则包含功函数为4.8电子伏特至5.2电子伏特的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等。导电层328则例如是包含铝(Al)、钨(W)、钛铝合金(TiAl)或钴钨磷化物(cobalt tungsten phosphide,CoWP)等低电阻材料，但不以此为限。
由此即可完成本发明优选实施例的半导体元件。在本实施例中，形成在两晶体管区内的栅极结构优选是具有相同导电型式，例如均为P型栅极或均为N型栅极。该二栅极结构可通过先形成一图案化光致抗蚀剂层作为蚀刻掩模来调整其中一栅极结构的栅极高度，后续再利用金属栅极置换制作工艺，以在另一栅极结构中形成金属栅极。也就是说，形成在一晶体管区内的一栅极结构包含依序堆叠的一栅极绝缘层、一多晶硅层、一第一金属硅化物层以及一帽盖层；形成在另一晶体管区内的另一栅极结构则包含依序堆叠的一高介电常数介电层、一功函数金属层以及一导电层。其中，该栅极的顶表面低于该导电层的一顶表面，并且，该栅极绝缘层具有大于该高介电常数介电层的厚度。
利用本发明的形成方式可有效率地在不同的晶体管区内形成临界尺寸不同的栅极结构，并有效控制其栅极高度，以避免该栅极结构在后续制作工艺中发生影响其栅极高度的情形，而损害整体效能。由此，位于该二晶体管区内的栅极结构可分别具有不同的临界电压，以在半导体元件中形成高临界电压(high threshold voltage,HVT)与低临界电压(low threshold voltage,LVT)，或是高临界电压与标准临界电压(standard voltagethreshold,SVT)的P型晶体管或N型晶体管等。
然而，本领域者应可轻易了解，本发明的半导体元件也可能以其他方式形成，并不限于前述的制作步骤。举例来说，本实施例中的栅极结构302虽是采用“后栅极(gate-last)制作工艺”并搭配“后高介电常数介电层(high-k last)制作工艺”为实施样态进行说明，但并不以此为限，在其他实施例中，也可选择直接于该基底上形成一金属栅极结构(未绘示)，该金属栅极结构至少包含一功函数金属层(work function layer)及一金属栅极。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (16)

1.一种半导体元件，其特征在于包含：
基底；
第一栅极，设置在该基底之上，该第一栅极包含：
依序堆叠于该基底上的一栅极绝缘层、一多晶硅层、一第一金属硅化物层以及一帽盖层；以及
第一间隙壁，环绕该栅极绝缘层、该多晶硅层、该第一金属硅化物层以及该帽盖层，其中该第一金属硅化物层低于该第一间隙壁的顶表面；
第二栅极，设置在该基底之上，该第二栅极包含：
依序堆叠于该基底上的一高介电常数介电层、一功函数金属层以及一导电层；以及
第二间隙壁，环绕该高介电常数介电层、该功函数金属层以及该导电层；
蚀刻停止层，设置在基底上，覆盖该第一栅极及该第二栅极；以及
层间介电层，设置在该蚀刻停止层上，其中该层间介电层的顶表面与该第一栅极及第二栅极的顶表面齐平，
其中，该帽盖层是该蚀刻停止层的一部分。
2.依据权利要求1所述的半导体元件，其特征在于还包含：
第一源极/漏极，设置在该第一栅极两侧的该基底中；以及
第二金属硅化物层，设置在该第一源极/漏极上。
3.依据权利要求2所述的半导体元件，其特征在于还包含：
蚀刻停止层，设置在基底上，覆盖该第一间隙壁及该第二金属硅化物层。
4.依据权利要求1所述的半导体元件，其特征在于该栅极绝缘层具有一厚度，该厚度大于该高介电常数介电层的厚度。
5.依据权利要求1所述的半导体元件，其特征在于该第一栅极的临界尺寸大于该第二栅极的临界尺寸。
6.依据权利要求1所述的半导体元件，其特征在于还包含：
第二源极/漏极，设置在该第二栅极两侧的该基底内；以及
第三金属硅化物层，设置在该第二源极/漏极上。
7.依据权利要求1所述的半导体元件，其特征在于该栅极绝缘层的一部分设置在该基底内。
8.一种半导体元件的形成方法，其特征在于包含：
在一基底上形成一第一栅极，其中该第一栅极包含：
依序堆叠于该基底上的一栅极绝缘层以及一多晶硅层；以及
第一间隙壁，环绕该栅极绝缘层以及该多晶硅层；
部分移除该多晶硅层，以形成一沟槽；
在该沟槽内的多晶硅层上以及该第一栅极两侧的该基底上分别形成一金属硅化物层；
在该基底上形成一蚀刻停止层及一层间介电层；以及
在该多晶硅层上的金属硅化物层上形成一帽盖层，以填满该沟槽，其中该帽盖层是该蚀刻停止层的一部分，该第一间隙壁环绕该帽盖层。
9.依据权利要求8所述的半导体元件的形成方法，其特征在于还包含：
在该第一栅极两侧的该基底内形成第一源极/漏极，其中该金属硅化物层覆盖在该第一源极/漏极上。
10.依据权利要求8所述的半导体元件的形成方法，其特征在于还包含：
在该基底上形成一蚀刻停止材料层，并且填入该沟槽内；
在该蚀刻停止材料层上形成一层间介电材料层；以及
进行一平坦化制作工艺，以形成该层间介电层及该蚀刻停止层。
11.依据权利要求8所述的半导体元件的形成方法，其特征在于还包含：
形成一第二栅极，设置在该基底上，该第二栅极包含：
依序堆叠于该基底上的一高介电常数介电层、一功函数金属层以及一导电层；以及
第二间隙壁，环绕该高介电常数介电层、一功函数金属层以及一导电层。
12.依据权利要求11所述的半导体元件的形成方法，其特征在于该第二栅极与该层间介电层及该第一栅极齐平。
13.依据权利要求11所述的半导体元件的形成方法，其特征在于形成该第二栅极的步骤包含：
在该基底上形成一虚置栅极，该第二间隙壁环绕该虚置栅极；以及
在该蚀刻停止层及该层间介电层形成后，进行一金属栅极置换制作工艺，以形成该第二栅极。
14.依据权利要求13所述的半导体元件的形成方法，其特征在于该虚置栅极及该第一栅极是同时形成。
15.依据权利要求13所述的半导体元件的形成方法，其特征在于该多晶硅层是部分移除至低于该虚置栅极。
16.依据权利要求8所述的半导体元件的形成方法，其特征在于该栅极绝缘层是利用一热氧化制作工艺而形成。
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