TW202205459A - 電子機器 - Google Patents
電子機器 Download PDFInfo
- Publication number
- TW202205459A TW202205459A TW110118226A TW110118226A TW202205459A TW 202205459 A TW202205459 A TW 202205459A TW 110118226 A TW110118226 A TW 110118226A TW 110118226 A TW110118226 A TW 110118226A TW 202205459 A TW202205459 A TW 202205459A
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- Prior art keywords
- metal layer
- semiconductor substrate
- bumps
- porous metal
- bump
- Prior art date
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 183
- 239000002184 metal Substances 0.000 claims abstract description 183
- 239000004065 semiconductor Substances 0.000 claims abstract description 119
- 239000000758 substrate Substances 0.000 claims abstract description 109
- 239000002245 particle Substances 0.000 claims description 22
- 239000002923 metal particle Substances 0.000 claims description 12
- 239000010931 gold Substances 0.000 description 30
- 229920002120 photoresistant polymer Polymers 0.000 description 21
- 239000000463 material Substances 0.000 description 18
- 239000010949 copper Substances 0.000 description 15
- 239000011295 pitch Substances 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 239000000203 mixture Substances 0.000 description 10
- 229910052737 gold Inorganic materials 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 9
- 229910052709 silver Inorganic materials 0.000 description 6
- 238000005336 cracking Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 230000005476 size effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
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Abstract
本揭示之電子機器(1)具備半導體基板(2)、晶片(3)、及凸塊(4)。晶片(3)之熱膨脹係數與半導體基板(2)不同。凸塊(4)將設置於半導體基板(2)及晶片(3)之對向之主面的連接焊墊(21、31)彼此連接。凸塊(4)具有多孔質金屬層(41)、及金屬膜(42、43)。金屬膜(42、43)設置於:設置於半導體基板(2)之連接焊墊(21)與多孔質金屬層(41)之間、及設置於晶片(3)之連接焊墊(31)與多孔質金屬層(41)之間中之至少任一者,且設置於多孔質金屬層(41)之側面。
Description
本揭示係關於一種電子機器。
作為將電子零件之晶片安裝於半導體基板上之技術,例如有一面將凸設於半導體基板之上表面之金屬製之凸塊、與設置於晶片之下表面之連接焊墊壓接,一面過熱連接之覆晶安裝(例如,參照專利文獻1)。作為凸塊之材料,一般使用塊狀之金、銅、及焊錫等。
[先前技術文獻]
[專利文獻]
[專利文獻1]日本專利特開2011-077308號公報
[發明所欲解決之問題]
然而,於使用塊狀之金或銅作為凸塊之材料,且將熱膨脹係數與半導體基板不同之晶片覆晶安裝於半導體基板之情形時,必須以高溫高壓進行凸塊之連接,引起晶片受損電子機器之可靠性降低。
另一方面,於使用焊錫作為凸塊之材料之情形,可以相對較低之低溫低壓將半導體基板與晶片連接,但因連接強度與金或銅之凸塊相比較低,故於半導體基板與晶片之熱膨脹係數不同之情形時,於連接強度之點上,可靠性降低。
又,隨著電子機器之細微化,於覆晶安裝時,問題在於如何藉由細間距之凸塊將半導體基板與晶片電性連接。
因此,本揭示提案一種將熱膨脹係數與半導體基板不同之晶片藉由細間距之凸塊覆晶安裝於半導體基板之高可靠性之電子機器。
[解決問題之技術手段]
根據本揭示,提供一種電子機器。電子機器具備半導體基板、晶片、及凸塊。上述晶片之熱膨脹係數與上述半導體基板不同。上述凸塊將設置於上述半導體基板及上述晶片之對向之主面的連接焊墊彼此連接。上述凸塊具有多孔質金屬層及金屬膜。上述金屬膜設置於:設置於上述半導體基板之上述連接焊墊與上述多孔質金屬層之間、及設置於上述晶片之上述連接焊墊與上述多孔質金屬層之間中之至少任一者,且設置於上述多孔質金屬層之側面。
以下,對本揭示之實施形態基於圖式詳細地進行說明。另,於以下各實施形態中,藉由對相同部位標註相同之符號及相同之陰影線而省略重複之說明。
[1.電子機器之剖面構造]
如圖1所示,本揭示之電子機器1具備半導體基板2、晶片3、及將設置於半導體基板2及晶片3之對向之主面之連接焊墊21、31彼此連接的連接部(以下,記載為凸塊4)。
晶片3例如為半導體雷射,於GaAs(砷化鎵)之基材之內部形成連接焊墊31或半導體雷射之發光部32等。發光部32具備出射雷射光之2維配置之複數個發光元件321。另,形成於晶片3之機材之電子零件亦可為半導體雷射之發光部32以外之任意電子零件。又,晶片3之基材亦可為例如InP(磷化銦)等之半絕緣性基材。
半導體基板2為例如Si(矽)基板,於內部形成驅動半導體雷射之驅動電路22。另,形成於半導體基板2之內部之電子電路,亦可為半導體雷射之驅動電路22以外之任意之電子電路。
電子機器1於半導體基板2覆晶安裝晶片3,且藉由凸塊4將半導體基板2內之驅動電路22、與半導體雷射即晶片3電性連接。
此處,於一般覆晶安裝中,藉由一面將設置於半導體基板或晶片之對向之主面之塊狀之Au(金)、Cu(銅)、及焊錫等金屬製之凸塊壓接一面加熱,而將晶片安裝於半導體基板。
然而,於半導體基板與晶片之熱膨脹係數例如相差0.1 ppm/℃以上之情形時,若使用塊狀之Au、Cu、及焊錫等作為凸塊之材料,則會發生如下之問題。
例如,於使用塊狀之Au作為凸塊之材料之情形時,為了藉由凸塊將熱膨脹係數不同之半導體基板與晶片穩定連接,必須加熱至300℃以上之高溫,且對半導體基板與晶片之間施加100 MPa以上之高壓。
又,於使用塊狀之Cu作為凸塊之材料之情形時,必須加熱至380℃以上。如此,於使用塊狀之Au或Cu作為凸塊之材料之情形時,必須以高溫高壓進行凸塊之連接,有時該高溫高壓會對晶片造成損傷,有時會導致電子機器之可靠性降低。
另一方面,使用焊錫作為凸塊之材料之情形時,與Au或Cu相比,可以低溫低壓進行凸塊之連接,但焊錫之耐熱性及連接強度較Au或Cu差。因此,焊錫製之凸塊係例如當晶片因搭載於晶片之半導體雷射等電子零件之發熱而熱膨脹時,有因半導體基板與晶片之熱膨脹係數之不同而產生開路故障,使電子機器之可靠性降低之虞。
此處,如上所述,本揭示之半導體基板2為Si基板,熱膨脹係數為5.7 ppm/℃。另一方面,本揭示之晶片3之基材為GaAs,熱膨脹係數為2.6 ppm/℃。
如此,電子機器1之半導體基板2與晶片3之熱膨脹係數之差遠大於0.1 ppm/℃。因此,電子機器1於凸塊之材料為塊狀之Au、Cu或焊錫之情形,有產生如上所述之問題致使可靠性降低之虞。
因此,電子機器1之凸塊4例如包含Au之多孔質金屬層41。多孔質金屬層41包含粒徑為0.005 μm~1.0 μm之Au粒子。另,多孔質金屬層41之成分例如亦可為Cu、Ag(銀)、或Pt(鉑)。
包含粒徑為0.005 μm~1.0 μm之金屬粒子之多孔質金屬層41藉由粒徑之尺寸效應,可以較塊狀金屬之熔點低之溫度進行金屬接合。例如,多孔質金屬層41於成分為Au之情形時,可以100℃左右、於Ag之情形時,可以250℃左右、於Cu之情形時,可以150℃左右之溫度,將半導體基板2與晶片3連接。藉此,電子機器1因可減少熱對晶片3之損傷,故能提高可靠性。
又,因多孔質金屬層41具有彈性,即便例如晶片3因半導體雷射之發熱而以與半導體基板2不同之熱膨脹係數膨脹,亦發生彈性變形,故可抑制產生開路故障。藉此,電子機器1例如與使用焊錫製之凸塊之情形相比,能提高可靠性。
該電子機器1藉由以下而製造:將晶片3積層於上表面設置有凸塊4之半導體基板2,且不使凸塊4之多孔質金屬層41熔融地與連接焊墊31連接,而將晶片3覆晶安裝於半導體基板2。
又,電子機器1亦可藉由以下而製造:將於下表面設置有包含多孔質金屬層41之凸塊之晶片3積層於半導體基板2,且不使凸塊之多孔質金屬層41熔融地與連接焊墊21連接,而將晶片3覆晶安裝於半導體基板2。另,凸塊亦可設置於積層前之半導體基板2及晶片3之兩者。
凸塊4設置於半導體基板2側之情形,於多孔質金屬層41與半導體基板2側之連接焊墊21之間,具備金屬膜42。又,凸塊設置於晶片3側之情形,於多孔質金屬層41與晶片3側之連接焊墊31之間具備金屬膜42。
於本揭示中,藉由將金屬膜42之膜厚相對於凸塊4中與半導體基板2之主面正交之方向之厚度的比例設為未達10%,可實現將凸塊4之間距設為20 μm以下之細間距化。關於該細間距化,搭配凸塊4之形成步驟稍後敘述。
再者,凸塊4於多孔質金屬層41之側面(側周面),亦具備金屬膜42。金屬膜42之材料期望與多孔質金屬層41相同。例如,多孔質金屬層41之材料為Au之情形時,期望金屬膜42為Au膜。
藉此,凸塊4因多孔質金屬層41之側面由金屬膜42塗覆,而可防止多孔質金屬層41之粒子崩裂並飛散。因此,凸塊4可防止因多孔質金屬層41之粒子之飛散致使相鄰之凸塊4彼此短路。
又,於多孔質金屬層41之側面未設置金屬膜42之情形時,因表面相對較軟,故於多孔質金屬層41之側面產生表面粗糙,而於凸塊4間,形狀上產生差異。
與此相對,凸塊4於多孔質金屬層41之側面設置較多孔質金屬層41硬之金屬膜42,因而抑制凸塊4間之形狀之差異,全部成為均一之形狀。且,凸塊4因由相對較硬之41塗覆側面,故可進而細微化,可實現更細間距化。
又,凸塊4於對半導體基板2覆晶安裝晶片3之情形時,雖於厚度方向被略微壓碎,但防止多孔質金屬層41之粒子漏出至金屬膜42之外部。其結果,凸塊4因金屬膜42內部之多孔質金屬層41之粒子密度增大,故可減少連接電阻。
[2.凸塊之形成步驟]
其次,參照圖2A~圖3D,說明本揭示之凸塊之形成步驟。圖2A~圖2D顯示於本揭示之半導體基板2形成凸塊4之步驟之說明圖。圖3A~圖3D係顯示於本揭示之晶片3形成凸塊4a(參照圖3D)之步驟之說明圖。
如圖2A所示,於半導體基板2形成凸塊4之情形時,首先於半導體基板2之設置有連接焊墊21之側之表面形成光阻層51。其後,藉由光微影技術,於光阻層51中後續形成凸塊4之位置形成貫通孔,使連接焊墊21之表面露出。
此時,以相鄰設置之貫通孔之中心間之間隔為20 μm(20 μm間距)之方式,形成貫通孔。該貫通孔於後續步驟中被填充包含作為多孔質金屬層41之材料之金屬粒子的糊料40,但因係所謂20 μm間距之細微構造,故若直接於該狀態下填充糊料40,則有細微構造受損而崩裂之虞。
因此,如圖2B所示,於光阻層51之上表面、貫通孔之側面、及連接焊墊21之上表面,例如藉由濺鍍形成金屬膜42。作為金屬膜42之材料,選擇與後續填充至貫通孔之糊料40所含之金屬粒子相同成分之金屬。另,此處,形成Au金屬膜42。
藉此,光阻層51之表面因由金屬膜42塗覆而硬化,故於將包含金屬粒子之糊料40填充至貫通孔時,可防止細微構造崩裂。
又,若此處形成之金屬膜42之膜厚過厚,則貫通孔之開口變窄,難以將包含金屬粒子之糊料40填充至貫通孔。因此,此處,形成較薄(例如厚度未達1 μm)的金屬膜42,該金屬膜42之膜厚d相對於貫通孔之深度D、換言之即後續形成之凸塊4在與半導體基板2之主面正交之方向之厚度(凸塊4之高度D)的比例未達10%。
例如,於形成以20 μm間距排列且高度10 μm之凸塊4之情形時,將金屬膜42之膜厚設為0.2 μm。藉此,即便形成金屬膜42,亦可防止貫通孔之開口變窄,因而可於後續步驟中將包含金屬粒子之糊料40充分填充至貫通孔。
繼而,如圖2C所示,在形成於光阻層51之貫通孔中,例如填充包含純度為99.9重量%以上且粒徑為0.005 μm~1.0 μm之Au粒子的糊料40。作為於貫通孔中填充糊料40之方法,例如可使用網版印刷、以刮刀塗抹滴下之糊料40之方法等任意方法。
其後,使糊料40乾燥及燒結後,藉由使用剝離液等之剝離法將光阻層51剝離。藉此,如圖2D所示,完成以下之凸塊4:於連接焊墊21之表面依序積層Au之金屬膜42、及包含粒徑為0.005 μm~1.0 μm之Au粒子的多孔質金屬層41,進而於多孔質金屬層41之側面亦形成金屬膜42。
如此,凸塊4於連接焊墊21與多孔質金屬層41之間,具備膜厚相對於凸塊4高度之比例未達10%之金屬膜42。再者,凸塊4於多孔質金屬層41之側面亦設置金屬膜42。
該金屬膜42係為了防止於光阻層51圖案化之凸塊4之細微構造之崩裂,而形成於光阻層51之上表面、形成於光阻層51之貫通孔之側面、及連接焊墊21之表面者。藉此,凸塊4可進行將間距設為20 μm以下之細間距化。
又,金屬膜42因藉由濺鍍而形成於連接焊墊21之表面,故即便連接焊墊21為與金屬膜42不同成分之金屬,亦可與連接焊墊21強固地接合。
又,金屬膜42亦可由與積層於表面之多孔質金屬層41不同成分之金屬形成,但於藉由相同成分之Au形成之情形時,較設置於不同成分之其他金屬膜上之情形,多孔質金屬層41以更強固之接合力與金屬膜42接合。另,於凸塊4為Au以外之成分(例如,Cu、Ag(銀)或Pt(鉑))之情形時,金屬膜42亦同樣,可使用Au以外之成分(例如,Cu、Ag(銀)或Pt(鉑))。
接著,對將圖3D所示之凸塊4a形成於晶片3之步驟進行說明。如圖3A所示,於將凸塊4a形成於晶片3之情形時,首先於晶片3之設置有連接焊墊31之側之表面形成光阻層52。其後,藉由光微影技術,於光阻層52中後續形成凸塊4a之位置形成貫通孔,使連接焊墊31之表面露出。
其後,如圖3B所示,於光阻層52之上表面、貫通孔之側面、及連接焊墊31之上表面,例如藉由濺鍍形成金屬膜43。作為金屬膜43之材料,選擇與後續填充至貫通孔之糊料40所含之Au粒子相同成分之Au。
藉此,光阻層52之表面因由金屬膜43塗覆而硬化,故於將包含Au粒子之糊料40填充至貫通孔之情形時,可防止細微構造之崩裂。
又,此處,亦形成較薄(例如厚度未達1 μm)之金屬膜43,該金屬膜43之膜厚d相對於貫通孔之深度D,換言之,後續形成之凸塊4a中與晶片3之主面正交之方向之厚度(凸塊4a之高度D)的比例未達10%。
例如,於形成與半導體基板2側之凸塊4相同,以20 μm間距排列且高度10 μm之凸塊之情形時,將金屬膜43之膜厚設為0.2 μm。藉此,即便形成金屬膜43亦可防止貫通孔之開口變窄,因而可於後續步驟中將包含Au粒子之糊料40充分填充至貫通孔。
繼而,如圖3C所示,在形成於光阻層52之貫通孔,例如填充包含純度為99.9重量%以上且粒徑為0.005 μm~1.0 μm之Au粒子的糊料40。
其後,使糊料40乾燥及燒結後,藉由剝離液等將光阻層52剝離。藉此,如圖3D所示,以下之凸塊4a完成:於連接焊墊31之表面依序積層Au之金屬膜43、及包含粒徑為0.005 μm~1.0 μm之Au粒子之多孔質金屬層41,進而於多孔質金屬層41之側面形成金屬膜43。
如此,凸塊4a於連接焊墊31與多孔質金屬層41之間,具備膜厚相對於凸塊4a之高度之比例未達10%之金屬膜43。再者,凸塊4a於多孔質金屬層41之側面亦設置金屬膜43。藉此,凸塊4a與半導體基板2側之凸塊4同樣,可實現將間距設為20 μm以下之細間距化。
又,根據凸塊4a,可與半導體基板2側之凸塊4同樣,使金屬膜43與連接焊墊31強固地接合,可使金屬膜43與多孔質金屬層41強固地接合。
於上述實施形態中,已對於設置有凸塊4之半導體基板2安裝未設置凸塊4a之晶片3之情形、及於未設置凸塊4之半導體基板2安裝設置有凸塊4a之晶片3之情形進行說明,但其僅為一例。
本揭示之電子機器亦可為於設置有凸塊4之半導體基板2安裝設置有凸塊4a之晶片3之構成。該構成時,金屬膜42、43之膜厚相對於作為連接半導體基板2與晶片3之連接部之凸塊4及凸塊4a之積層體中與半導體基板2及晶片3之主面正交之方向之厚度之一半的比例未達10%,較佳為未達5%。
又,於上述實施形態中,已對晶片3之基材為Si以外之基材之情形進行說明,但晶片3之基材只要為熱膨脹係數與半導體基板2不同者,亦可為於Si摻雜有雜質者。
具備上述之半導體雷射之發光部32之晶片3、及具備半導體雷射之驅動電路22之半導體基板2例如搭載於ToF(Time of Flight:飛行時間)感測器或結構光等測距裝置。半導體雷射之發光部32於搭載於測距裝置之情形時,例如作為ToF感測器之光源或結構光之光源發揮功能。
[3.效果]
電子機器1具有半導體基板2、晶片3、及連接部(凸塊4)。晶片3之熱膨脹係數與半導體基板2不同。凸塊4包含將設置於半導體基板2及晶片3之對向之主面之連接焊墊21、31彼此連接之多孔質金屬層41。電子機器1具備半導體基板2、晶片3、及凸塊4、4a。晶片3之熱膨脹係數與半導體基板2不同。凸塊4、4a將設置於半導體基板2及晶片3之對向之主面之連接焊墊21、31彼此連接。凸塊4、4a具有多孔質金屬層41、及金屬膜42、43。金屬膜42、43設置於在半導體基板2設置之連接焊墊21與多孔質金屬層41之間、及設置於晶片3之連接焊墊31與多孔質金屬層41之間中之至少任一者、與多孔質金屬層41之側面。
藉此,與藉由塊狀之金屬製之凸塊連接半導體基板2及晶片3之連接焊墊21、31彼此之情形相比,電子機器1可以低溫低壓之處理連接半導體基板2及晶片3之連接焊墊21、31彼此。又,電子機器1可藉由設置於多孔質金屬層41之側面之金屬膜42、43防止多孔質金屬層41之崩裂。因此,電子機器1成為將熱膨脹係數與半導體基板2不同之晶片3藉由細間距之凸塊4、4a覆晶安裝於半導體基板2之高可靠性之電子機器。
又,晶片3之熱膨脹係數與半導體基板2相差0.1 ppm/℃以上。藉此,電子機器1係即便例如晶片3發熱且以與半導體基板2不同之熱膨脹係數膨脹,因多孔質金屬層41發生彈性變形,故亦可抑制因凸塊4產生開路故障。
又,晶片3為半導體雷射,半導體基板2具有驅動半導體雷射之驅動電路22。藉此,電子機器1係即便因伴隨半導體雷射之發光之發熱,使晶片3以與半導體基板2不同之熱膨脹係數膨脹,因多孔質金屬層41發生彈性變形,故亦可抑制因凸塊4而產生開路故障。
又,多孔質金屬層41包含粒徑為0.005 μm~1.0 μm之金屬粒子。該多孔質金屬層41藉由金屬粒子之尺寸效應,可以較塊狀金屬之熔點更低之溫度進行金屬接合。藉此,電子機器1因半導體基板2及晶片3之連接焊墊21、31彼此乃藉由能以相對較低之溫度進行金屬接合之多孔質金屬層41而連接,故可減少熱損傷從而提高可靠性。
設置於連接焊墊21、31與多孔質金屬層41之間的金屬膜42、43,其膜厚相對於凸塊4、4a在與半導體基板2及晶片3之主面正交之方向之厚度的比例未達10%。藉此,可防止用以形成使光阻層51、52圖案化之凸塊4、4a的貫通孔因金屬膜42、43之形成而變窄。其結果,可於使光阻層51、52圖案化之貫通孔中,適當填充包含作為凸塊4、4a材料之金屬粒子的糊料40。
又,若為將半導體基板2及晶片3藉由凸塊4與凸塊4a連接之電子機器,設置於連接焊墊21、31與多孔質金屬層41之間之金屬膜42、43,其膜厚相對於凸塊4a在與半導體基板2及晶片3之主面正交之方向之厚度之一半的比例未達10%。藉此,可防止用以形成使光阻層51、52圖案化之凸塊4、4a的貫通孔因金屬膜42、43之形成而變窄。其結果,可於使光阻層51、52圖案化之貫通孔中,適當填充包含作為凸塊4、4a材料之金屬粒子的糊料40。
又,電子機器1具備半導體基板2與凸塊4。凸塊4設置在半導體基板2之主面上所設置之連接焊墊21之表面。凸塊4具有多孔質金屬層41與金屬膜42。金屬膜42設置於多孔質金屬層41與連接焊墊21之間、及多孔質金屬層41之側面。金屬膜42之膜厚相對於凸塊4在與半導體基板2之主面正交之方向之厚度的比例未達10%。
藉此,半導體基板2可實現凸塊4之細間距化,且能夠藉由與使用塊狀之金屬製凸塊相比更低溫低壓之處理,實現熱膨脹係數與半導體基板2不同之晶片3之覆晶安裝。
電子機器1具備晶片3與凸塊4a。凸塊4a在設置於晶片3之主面之連接焊墊31之表面設置。凸塊4a具有多孔質金屬層41、與金屬膜43。金屬膜43設置於多孔質金屬層41與連接焊墊31之間及多孔質金屬層41之側面。金屬膜42之膜厚相對於凸塊4a在與晶片3之主面正交之方向之厚度之比例未達10%。
藉此,晶片3可實現凸塊4a之細間距化,且藉由與使用塊狀之金屬製凸塊之情形相比更低溫低壓之處理,可實現對熱膨脹係數與晶片3不同之半導體基板2之覆晶安裝。
另,本說明書所記載之效果僅為例示,並非限定者,又,亦可有其他效果。
另,本技術亦可採取如下之構成。
(1)
一種電子機器,其具備:
半導體基板;
晶片,其熱膨脹係數與上述半導體基板不同;及
凸塊,其將設置於上述半導體基板及上述晶片之對向之主面的連接焊墊彼此連接;且
上述凸塊具有:
多孔質金屬層;及
金屬膜,其設置於:設置於上述半導體基板之上述連接焊墊與上述多孔質金屬層之間、及設置於上述晶片之上述連接焊墊與上述多孔質金屬層之間中之至少任一者,且設置於上述多孔質金屬層之側面。
(2)
如上述技術方案(1)之電子機器,其中
上述晶片之熱膨脹係數與上述半導體基板相差0.1 ppm/℃以上。
(3)
如上述技術方案(1)或(2)之電子機器,其中
上述晶片為半導體雷射;
上述半導體基板具有驅動上述半導體雷射之驅動電路。
(4)
如上述技術方案(1)至(3)中任一項之電子機器,其中
上述多孔質金屬層包含粒徑為0.005 μm~1.0 μm之金屬粒子。
(5)
如上述(1)至(4)中任一項之電子機器,其中
設置於上述連接焊墊與上述多孔質金屬層之間之上述金屬膜,
其膜厚相對於上述凸塊在與上述主面正交之方向之厚度的比例未達10%。
(6)
如上述技術方案(1)至(4)中任一項之電子機器,其中
設置於上述連接焊墊與上述多孔質金屬層之間之上述金屬膜,
其膜厚相對於上述凸塊在與上述主面正交之方向之厚度之一半的比例未達10%。
(7)
一種電子機器,其具備:
半導體基板;及
凸塊,其設置於連接焊墊之表面,該連接焊墊設置於上述半導體基板之主面;且
上述凸塊具有:
多孔質金屬層;及
金屬膜,其設置於上述多孔質金屬層與上述連接焊墊之間及上述多孔質金屬層之側面;且
上述金屬膜之膜厚相對於上述凸塊在與上述主面正交之方向之厚度的比例未達10%。
(8)
一種電子機器,其具備:
晶片;及
凸塊,其設置於連接焊墊之表面,該連接焊墊設置於上述晶片之主面;且
上述凸塊具有:
多孔質金屬層;及
金屬膜,其設置於上述多孔質金屬層與上述連接焊墊之間、及上述多孔質金屬層之側面;且
上述金屬膜之膜厚相對於上述凸塊在與上述主面正交之方向之厚度的比例未達10%。
1:電子機器
2:半導體基板
3:晶片
4:凸塊
4a:凸塊
21:連接焊墊
22:驅動電路
31:連接焊墊
32:發光部
40:糊料
41:多孔質金屬層
42:金屬膜
43:金屬膜
51:光阻層
52:光阻層
321:發光元件
D:深度(高度)
d:膜厚
圖1係顯示本揭示之電子機器之剖面之說明圖。
圖2A係顯示本揭示之將凸塊形成於半導體基板之步驟之說明圖。
圖2B係顯示本揭示之將凸塊形成於半導體基板之步驟之說明圖。
圖2C係顯示本揭示之將凸塊形成於半導體基板之步驟之說明圖。
圖2D係顯示本揭示之將凸塊形成於半導體基板之步驟之說明圖。
圖3A係顯示本揭示之將凸塊形成於晶片之步驟之說明圖。
圖3B係顯示本揭示之將凸塊形成於晶片之步驟之說明圖。
圖3C係顯示本揭示之將凸塊形成於晶片之步驟之說明圖。
圖3D係顯示本揭示之將凸塊形成於晶片之步驟之說明圖。
1:電子機器
2:半導體基板
3:晶片
4:凸塊
21:連接焊墊
22:驅動電路
31:連接焊墊
32:發光部
41:多孔質金屬層
42:金屬膜
321:發光元件
Claims (8)
- 一種電子機器,其具備: 半導體基板; 晶片,其熱膨脹係數與上述半導體基板不同;及 凸塊,其將設置於上述半導體基板及上述晶片之對向之主面的連接焊墊彼此連接;且 上述凸塊具有: 多孔質金屬層;及 金屬膜,其設置於:設置於上述半導體基板之上述連接焊墊與上述多孔質金屬層之間、及設置於上述晶片之上述連接焊墊與上述多孔質金屬層之間中之至少任一者,且設置於上述多孔質金屬層之側面。
- 如請求項1之電子機器,其中 上述晶片之熱膨脹係數與上述半導體基板相差0.1 ppm/℃以上。
- 如請求項1之電子機器,其中 上述晶片為半導體雷射; 上述半導體基板具有驅動上述半導體雷射之驅動電路。
- 如請求項1之電子機器,其中 上述多孔質金屬層包含粒徑為0.005 μm~1.0 μm之金屬粒子。
- 如請求項1之電子機器,其中 設置於上述連接焊墊與上述多孔質金屬層之間之上述金屬膜, 其膜厚相對於上述凸塊在與上述主面正交之方向之厚度的比例未達10%。
- 如請求項1之電子機器,其中 設置於上述連接焊墊與上述多孔質金屬層之間之上述金屬膜, 其膜厚相對於上述凸塊在與上述主面正交之方向之厚度之一半的比例未達10%。
- 一種電子機器,其具備: 半導體基板;及 凸塊,其設置於連接焊墊之表面,該連接焊墊設置於上述半導體基板之主面;且 上述凸塊具有: 多孔質金屬層;及 金屬膜,其設置於上述多孔質金屬層與上述連接焊墊之間、及上述多孔質金屬層之側面;且 上述金屬膜之膜厚相對於上述凸塊在與上述主面正交之方向之厚度的比例未達10%。
- 一種電子機器,其具備: 晶片;及 凸塊,其設置於連接焊墊之表面,該連接焊墊設置於上述晶片之主面;且 上述凸塊具有: 多孔質金屬層;及 金屬膜,其設置於上述多孔質金屬層與上述連接焊墊之間、及上述多孔質金屬層之側面;且 上述金屬膜之膜厚相對於上述凸塊在與上述主面正交之方向之厚度的比例未達10%。
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EP (1) | EP4191644A4 (zh) |
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JP2751912B2 (ja) * | 1996-03-28 | 1998-05-18 | 日本電気株式会社 | 半導体装置およびその製造方法 |
JPH11168116A (ja) * | 1997-12-04 | 1999-06-22 | Mitsui High Tec Inc | 半導体チップ用電極バンプ |
JP4661122B2 (ja) * | 2004-05-18 | 2011-03-30 | ソニー株式会社 | 部品実装配線基板および配線基板への部品の実装方法 |
JP5363839B2 (ja) * | 2008-05-12 | 2013-12-11 | 田中貴金属工業株式会社 | バンプ及び該バンプの形成方法並びに該バンプが形成された基板の実装方法 |
JP5176750B2 (ja) * | 2008-07-24 | 2013-04-03 | ソニー株式会社 | 発光素子組立体、面状光源装置、及び、液晶表示装置組立体 |
JP2011077308A (ja) | 2009-09-30 | 2011-04-14 | Fujitsu Ltd | 半導体装置の実装方法 |
JP2011165871A (ja) * | 2010-02-09 | 2011-08-25 | Denso Corp | 電子装置およびその製造方法 |
WO2011114751A1 (ja) * | 2010-03-19 | 2011-09-22 | 古河電気工業株式会社 | 導電接続部材、及び導電接続部材の作製方法 |
JP5782823B2 (ja) * | 2011-04-27 | 2015-09-24 | 日亜化学工業株式会社 | 窒化物半導体発光素子およびその製造方法 |
US8569109B2 (en) * | 2011-06-30 | 2013-10-29 | Infineon Technologies Ag | Method for attaching a metal surface to a carrier, a method for attaching a chip to a chip carrier, a chip-packaging module and a packaging module |
JP6379342B2 (ja) * | 2014-07-09 | 2018-08-29 | 三菱マテリアル株式会社 | 半導体装置及びその製造方法 |
TWI662657B (zh) * | 2015-04-07 | 2019-06-11 | 聯華電子股份有限公司 | 半導體元件的堆疊結構 |
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