CN115868015A - 电子设备 - Google Patents
电子设备 Download PDFInfo
- Publication number
- CN115868015A CN115868015A CN202180043642.8A CN202180043642A CN115868015A CN 115868015 A CN115868015 A CN 115868015A CN 202180043642 A CN202180043642 A CN 202180043642A CN 115868015 A CN115868015 A CN 115868015A
- Authority
- CN
- China
- Prior art keywords
- chip
- semiconductor substrate
- bump
- metal layer
- porous metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 183
- 239000002184 metal Substances 0.000 claims abstract description 183
- 239000004065 semiconductor Substances 0.000 claims abstract description 120
- 239000000758 substrate Substances 0.000 claims abstract description 107
- 239000002245 particle Substances 0.000 claims description 22
- 239000002923 metal particle Substances 0.000 claims description 12
- 239000010931 gold Substances 0.000 description 27
- 238000000034 method Methods 0.000 description 23
- 239000000463 material Substances 0.000 description 21
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 239000011295 pitch Substances 0.000 description 14
- 239000010949 copper Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 229910052737 gold Inorganic materials 0.000 description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000000203 mixture Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000005476 size effect Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
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Abstract
根据本公开的电子设备(1)包括半导体基板(2)、芯片(3)和凸块(4)。所述芯片(3)具有与所述半导体基板(2)的热膨胀系数不同的热膨胀系数。所述凸块(4)将设置在所述半导体基板(2)和所述芯片(3)的相对主面上的连接焊盘(21,31)进行连接。所述凸块(4)具有多孔金属层(41)和金属膜(42,43)。所述金属膜(42,43)设置在设于所述半导体基板(2)上的连接焊盘(21)和所述多孔金属层(41)之间的部分以及设于所述芯片(3)上的连接焊盘(31)和所述多孔金属层(41)之间的部分中的至少一者上,并且设置在所述多孔金属层(41)的侧面上。
Description
技术领域
本公开涉及一种电子设备。
背景技术
作为将电子部件的芯片安装在半导体基板上的技术,例如,存在一种倒装芯片安装,其中从半导体基板的上表面突出的金属凸块与芯片的下表面上设置的连接焊盘在过热的同时彼此连接并彼此紧压(例如,参见专利文献1)。块状的金、铜、焊料等通常被用作凸块的材料。
引用文献列表
专利文献
专利文献1:JP 2011-077308 A
发明内容
技术问题
然而,当热膨胀系数与半导体基板不同的芯片使用块状的金或铜作为凸块的材料被倒装芯片安装在半导体基板上时,需要在高温高压下通过凸块进行连接,这会损坏芯片并降低电子设备的可靠性。
另一方面,当焊料被用作凸块的材料时,半导体基板和芯片可以在相对低温和低压下彼此连接,但连接强度低于金或铜的凸块的连接强度。因此,如果半导体基板和芯片之间的热膨胀系数不同,则在连接强度方面可靠性会降低。
另外,随着电子设备小型化,使用微细间距的凸块以电气连接到半导体基板和芯片是倒装安装的课题。
因此,本公开提出了一种高度可靠的电子设备,其中热膨胀系数与半导体基板不同的芯片通过微细间距的凸块被倒装芯片安装在半导体基板上。
问题的解决方案
根据本公开,提供一种电子设备。根据本公开的电子设备包括半导体基板、芯片和凸块。所述芯片具有与所述半导体基板的热膨胀系数不同的热膨胀系数。所述凸块将设置在所述半导体基板和所述芯片的相对主面上的连接焊盘进行连接。所述凸块具有多孔金属层和金属膜。所述金属膜设置在设于所述半导体基板上的连接焊盘和所述多孔金属层之间的部分以及设于所述芯片上的连接焊盘和所述多孔金属层之间的部分中的至少一者上,并且设置在所述多孔金属层的侧面上。
附图说明
图1是示出根据本公开的电子设备的断面的说明图。
图2A是示出根据本公开在半导体基板上形成凸块的过程的说明图。
图2B是示出根据本公开在半导体基板上形成凸块的过程的说明图。
图2C是示出根据本公开在半导体基板上形成凸块的过程的说明图。
图2D是示出根据本公开在半导体基板上形成凸块的过程的说明图。
图3A是示出根据本公开在芯片上形成凸块的过程的说明图。
图3B是示出根据本公开在芯片上形成凸块的过程的说明图。
图3C是示出根据本公开在芯片上形成凸块的过程的说明图。
图3D是示出根据本公开在芯片上形成凸块的过程的说明图。
具体实施方式
在下文中,本公开的实施方案将参照附图进行详细说明。注意,在以下的实施方案中,由相同的附图标记和相同的剖面线表示相同的部件,从而可以省略冗余的说明。
[1.电子设备的截面结构]
如图1所示,根据本公开的电子设备1包括半导体基板2、芯片3和将设置在半导体基板2和芯片3的相对主面上的连接焊盘21和31进行连接的连接部(在下文中,被称为凸块4)。
芯片3例如是半导体激光器,其中连接焊盘31和半导体激光器的发光单元32等形成在砷化镓(GaAs)的基材的内部。发光单元32包括二维布置的多个发光元件321,以发射激光。可选择地,在芯片3的基材上形成的电子部件可以是半导体激光器的发光单元32以外的任何电子部件。另外,芯片3的基材例如可以是诸如磷化铟(InP)等半绝缘性基材。
例如,半导体基板2是硅(Si)基板,其内部形成有驱动半导体激光器的驱动电路22。可选择地,在半导体基板2的内部形成的电子电路可以是半导体激光器的驱动电路22以外的任何电子电路。
在电子设备1中,芯片3是安装在半导体基板2上的倒装芯片,半导体基板2内的驱动电路22与作为半导体激光器的芯片3通过凸块4彼此电气连接。
这里,在一般的倒装芯片安装中,在紧压设置在半导体基片或芯片相对主面上的由诸如金(Au)、铜(Cu)或焊料等金属制成的块状凸块的同时,芯片通过加热而被安装在半导体基片上。
然而,如果半导体基板和芯片的热膨胀系数彼此相差例如0.1ppm/℃以上,则当块状的Au、Cu、焊料等被用作凸块的材料时,就会出现以下问题。
例如,当块状的Au被用作凸块的材料时,需要将凸块加热到300℃以上的高温,并在半导体基板和芯片之间施加100MPa以上的高压,以使热膨胀系数不同的半导体基板和芯片通过凸块稳定地彼此连接。
当块状的Cu被用作凸块的材料时,需要将凸块加热到380℃以上。因此,当块状的Au或Cu被用作凸块的材料时,凸块的连接需要在高温高压下进行,并且这种高温高压可能会损坏芯片,这可能会降低电子设备的可靠性。
另一方面,当焊料被作为凸块的材料时,与Au和Cu相比,凸块的连接可以在低温低压下进行,但焊料在耐热性和连接强度方面不如Au和Cu。为此,在焊料的凸块的情况下,例如,当芯片由于安装在芯片上的诸如半导体激光器等电子部件产生热量而热膨胀时,由于半导体基板和芯片之间的热膨胀系数的差异,可能会发生开路故障,这可能会降低电子设备的可靠性。
这里,如上所述,根据本公开的半导体基板2是具有5.7ppm/℃的热膨胀系数的Si基板。另一方面,根据本公开的芯片3的基材是具有2.6ppm/℃的热膨胀系数的GaAs。
因此,在电子设备1中,半导体基板2和芯片3之间的热膨胀系数之差远远大于0.1ppm/℃。为此,在电子设备1中,当凸块的材料是块状的Au、Cu或焊料时,就可能会发生上述问题,并且可能会降低可靠性。
为了解决该问题,例如,电子设备1的凸块4包括Au的多孔金属层41。多孔金属层41包含粒径为0.005μm~1.0μm的Au粒子。可选择地,例如,多孔金属层41的成分可以是Cu、银(Ag)或铂(Pt)。
由于粒径的尺寸效应,包含粒径为0.005μm~1.0μm的金属粒子的多孔金属层41可以在低于块状金属的熔点的温度下进行金属接合。例如,多孔金属层41可以在成分为Au时约100℃、成分为Ag时约250℃、成分为Cu时约150℃的温度下连接半导体基板2和芯片3。这使得电子设备1减少了由于热量对芯片3的损坏,并由此提高了可靠性。
另外,多孔金属层41具有弹性,因此例如,即使芯片3由于半导体激光器产生的热量而以与半导体基板2不同的热膨胀系数膨胀,也发生弹性变形,这也可以抑制开路故障的发生。这使得电子设备1与例如使用焊料的凸块的情况相比提高了可靠性。
电子设备1通过如下过程制造:将芯片3堆叠在上表面上设置有凸块4的半导体基板2上;在未熔融多孔金属层41的情况下将凸块4的多孔金属层41连接到连接焊盘31;并且将芯片3倒装芯片安装在半导体基板2上。
可选择地,电子设备1可以通过如下过程制造:将在下表面上设置有包括多孔金属层41的凸块的芯片3堆叠在半导体基板2上;在未熔融多孔金属层41的情况下将凸块的多孔金属层41连接到连接焊盘21;并且将芯片3倒装芯片安装在半导体基板2上。凸块可以设置在堆叠前的半导体基板2和芯片3两者上。
当被设置在半导体基板2侧时,凸块4在多孔金属层41和半导体基板2侧的连接焊盘21之间包括金属膜42。当被设置在芯片3侧时,凸块在多孔金属层41和芯片3侧的连接焊盘31之间包括金属膜42。
在本公开中,金属膜42的膜厚与凸块4的在与半导体基板2的主面正交的方向上的厚度之比被设定为小于10%,从而允许凸块4具有20μm以下的微细间距。这种微细间距将与凸块4的形成过程一起在后面进行说明。
此外,凸块4还包括在多孔金属层41的侧面(侧周面)上的金属膜42。金属膜42的材料期望与多孔金属层41的材料相同。例如,当多孔金属层41的材料为Au时,金属膜42期望为Au膜。
通过这种构成,由于凸块4的多孔金属层41的侧面涂覆有金属膜42,因此可以防止多孔金属层41的粒子崩塌和飞散。因此,凸块4可以防止相邻凸块4之间的在多孔金属层41的粒子飞散时发生的短路。
另外,当在多孔金属层41的侧面上未设置金属膜42时,表面粗糙会出现在表面相对较软的多孔金属层41的侧面上,并且凸块4之间的形状会发生变化。
另一方面,当在凸块4的多孔金属层41的侧面上设置比多孔金属层41更硬的金属膜42时,凸块4之间的形状变化被抑制,由此所有凸块4具有一致的形状。此外,由于凸块4的侧面涂覆有相对较硬的多孔金属层41,因此凸块4可以被进一步小型化,从而使凸块4具有进一步的微细间距。
另外,当芯片3被倒装芯片安装在半导体基板2上时,凸块4在厚度方向上被轻微碾碎,但防止了多孔金属层41的粒子泄漏到金属膜42的外部。结果,金属膜42的内部的多孔金属层41的粒子密度在凸块4中增大,这可以降低连接电阻。
[2.凸块形成过程]
接下来,根据本公开的凸块形成过程将参照图2~3D进行说明。图2A~2D是示出根据本公开在半导体基板2上形成凸块4的过程的说明图。图3A~3D是示出根据本公开在芯片3上形成凸块4a(参见图3D)的过程的说明图。
如图2A所示,当在半导体基板2上形成凸块4的情况下,首先,在半导体基板2的设置有连接焊盘21的一侧的表面上形成光致抗蚀剂层51。然后,通过光刻技术,在光致抗蚀剂层51上后面将形成凸块4的位置处形成贯通孔,以露出连接焊盘21的表面。
此时,贯通孔的形成使相邻贯通孔的中心之间的间隔为20μm(20μm间距)。贯通孔中填充有在后续步骤中将要用作多孔金属层41的材料的包含金属粒子的糊状物40,但由于20μm间距的结构是微细的,因此如果贯通孔中原样地填充有糊状物40,则可能会损坏和崩塌微细结构。
然后,如图2B所示,例如,通过溅射在光致抗蚀剂层51的上表面、贯通孔的侧面和连接焊盘21的上表面上形成金属膜42。作为金属膜42的材料,选择与后面放置到贯通孔中的糊状物40中所包含的金属粒子具有相同成分的金属。这里,形成了Au的金属膜42。
通过这种构成,光致抗蚀剂层51在其表面涂覆有金属膜42的同时被硬化,当贯通孔用包含金属粒子的糊状物40填充时,这可以防止微细结构崩塌。
另外,如果这里形成的金属膜42的厚度太大,则贯通孔的开口就很窄,从而难以用包含金属粒子的糊状物40填充贯通孔。为了解决这个问题,这里,形成薄的金属膜42(例如,厚度小于1μm),使得金属膜42的膜厚d与贯通孔的深度D,换句话说,后面形成的凸块4的在与半导体基板2的主面正交的方向上的厚度(凸块4的高度D)之比小于10%。
例如,当形成以20μm间距排列并具有10μm高度的凸块4时,金属膜42的膜厚被设定为0.2μm。即使当形成金属膜42时,这也可以防止贯通孔的开口变窄,从而允许贯通孔在后续步骤中被充分填充包含金属粒子的糊状物40。
随后,如图2C所示,形成在光致抗蚀剂层51中的贯通孔填充有包含例如纯度为99.9wt%以上和粒径为0.005μm~1.0μm的Au粒子的糊状物40。作为用糊状物40填充贯通孔的方法,例如,可以使用诸如丝网印刷或用抹刀将滴下的糊状物40抹平等任何方法。
然后,将糊状物40干燥并烧结,随后使用剥离液等通过提拉将光致抗蚀剂层51剥离。如图2D所示,完成了凸块4,其中在连接焊盘21的表面上依次堆叠Au的金属膜42和包含粒径为0.005μm~1.0μm的Au粒子的多孔金属层41,并且还在多孔金属层41的侧面上形成金属膜42。
以这种方式,凸块4在连接焊盘21和多孔金属层41之间包括膜厚与凸块4的高度之比小于10%的金属膜42。此外,凸块4还在多孔金属层41的侧面上设置有金属膜42。
金属膜42形成在光致抗蚀剂层51的上表面、光致抗蚀剂层51中形成的贯通孔的侧面和连接焊盘21的表面上,以防止在光致抗蚀剂层51上图案化的凸块4的微细结构崩塌。这能够使凸块4具有20μm以下的微细间距。
另外,由于金属膜42通过溅射形成在连接焊盘21的表面上,因此即使连接焊盘21是具有与金属膜42的成分不同的成分的金属,金属膜42也牢固地接合到连接焊盘21。
此外,尽管金属膜42可以由具有与堆叠在表面上的多孔金属层41的成分不同的成分的金属形成,但如果金属膜42是由相同成分的Au形成,则多孔金属层41以比被设置在具有不同成分的另一金属膜上时更强的接合力接合到金属膜42。可选择地,当凸块4具有Au以外的成分(例如,Cu、Ag(银)或Pt(铂))时,也可以将Au以外的成分(例如,Cu、Ag(银)或Pt(铂))用于金属膜42。
接下来,将说明在芯片3上形成图3D所示的凸块4a的过程。如图3A所示,当在芯片3上形成凸块4a的情况下,首先,在芯片3的设置有连接焊盘31的一侧的表面上形成光致抗蚀剂层52。然后,通过光刻技术,在光致抗蚀剂层52上后面将形成凸块4a的位置处形成贯通孔,以露出连接焊盘31的表面。
然后,如图3B所示,例如,通过溅射在光致抗蚀剂层52的上表面、贯通孔的侧面和连接焊盘31的上表面上形成金属膜43。作为金属膜43的材料,选择具有与后面放置到贯通孔中的糊状物40中所包含的Au粒子具有相同成分的Au。
通过这种构成,光致抗蚀剂层52在其表面涂覆有金属膜43的同时被硬化,当贯通孔用包含Au粒子的糊状物40填充时,这可以防止微细结构崩塌。
这里,同样,形成薄的金属膜43(例如,厚度小于1μm),使得金属膜43的膜厚d与贯通孔的深度D,换句话说,后面形成的凸块4a的在与芯片3的主面正交的方向上的厚度(凸块4a的高度D)之比小于10%。
例如,如同半导体基板2侧的凸块4中那样,当形成以20μm间距排列并具有10μm高度的凸块时,金属膜43的膜厚被设定为0.2μm。即使当形成金属膜43时,这也可以防止贯通孔的开口变窄,从而允许贯通孔在后续步骤中被充分填充包含Au粒子的糊状物40。
随后,如图3C所示,形成在光致抗蚀剂层52中的贯通孔填充有包含例如纯度为99.9wt%以上和粒径为0.005μm~1.0μm的Au粒子的糊状物40。
然后,将糊状物40干燥并烧结,随后使用剥离液等将光致抗蚀剂层52剥离。如图3D所示,完成了凸块4a,其中在连接焊盘31的表面上依次堆叠Au的金属膜43和包含粒径为0.005μm~1.0μm的Au粒子的多孔金属层41,并且还在多孔金属层41的侧面上形成金属膜43。
以这种方式,凸块4a在连接焊盘31和多孔金属层41之间包括膜厚与凸块4a的高度之比小于10%的金属膜43。此外,凸块4a还在多孔金属层41的侧面上设置有金属膜43。如同半导体基板2侧的凸块4中那样,这能够使凸块4a具有20μm以下的微细间距。
另外,在凸块4a中,如同半导体基板2侧的凸块4中那样,金属膜43和连接焊盘31可以牢固地接合,并且金属膜43和多孔金属层41可以牢固地接合。
在上述实施方案中,已经对下述情况进行了说明:未设置凸块4a的芯片3被安装在设置有凸块4的半导体基板2上;和设置有凸块4a的芯片3被安装在未设置凸块4的半导体基板2上;然而,这些情况仅是示例。
根据本公开的电子设备可以具有以下构成,其中设置有凸块4a的芯片3被安装在设置有凸块4的半导体基板2上。在这种构成的情况下,金属膜42、43的膜厚与用作连接半导体基板2和芯片3的连接部的凸块4和4a的堆叠体的在与半导体基板2和芯片3的主面正交的方向上的厚度的一半之比小于10%,优选小于5%。
另外,在上述实施方案中,已经对下述情况进行了说明:芯片3的基材为Si以外的基材;然而,芯片3的基材可以是掺杂有杂质的Si,只要其热膨胀系数与半导体基板2的热膨胀系数不同即可。
如上所述的包括半导体激光器的发光单元32的芯片3和包括半导体激光器的驱动电路22的半导体基板2被安装在例如诸如ToF传感器或结构光器件等测距装置上。当被安装在测距装置上时,半导体激光器的发光单元32用作例如ToF传感器的光源或结构光器件的光源。
[3.效果]
电子设备1包括半导体基板2、芯片3和连接部(凸块4)。芯片3具有与半导体基板2的热膨胀系数不同的热膨胀系数。凸块4包括连接设置在半导体基板2和芯片3的相对主面上的连接焊盘21和31的多孔金属层41。电子设备1包括半导体基板2、芯片3和凸块4、4a。芯片3具有与半导体基板2的热膨胀系数不同的热膨胀系数。凸块4、4a连接设置在半导体基板2和芯片3的相对主面上的连接焊盘21和31。凸块4、4a具有多孔金属层41和金属膜42、43。金属膜42、43设置在设于半导体基板2上的连接焊盘21和多孔金属层41之间的部分以及设于芯片3上的连接焊盘31和多孔金属层41之间的部分中的至少一者上,并且设置在多孔金属层41的侧面上。
通过这种构成,与半导体基板2和芯片3的连接焊盘21和31通过块状的金属凸块彼此连接的情况相比,电子设备1可以通过低温低压处理来连接半导体基板2和芯片3的连接焊盘21和31。另外,电子设备1可以使用设置在多孔金属层41的侧面上的金属膜42和43来防止多孔金属层41的崩塌。因此,电子设备1是高度可靠的电子设备,其中热膨胀系数与半导体基板2不同的芯片3通过微细间距的凸块4、4a被倒装芯片安装在半导体基板2上。
另外,芯片3具有与半导体基板2的热膨胀系数相差0.1ppm/℃以上的热膨胀系数。即使这会导致电子设备1的芯片3被加热并以与半导体基板2的热膨胀系数不同的热膨胀系数膨胀,多孔金属层41也会弹性变形,从而可以抑制凸块4中开路故障的发生。
芯片3是半导体激光器,并且半导体基板2具有驱动半导体激光器的驱动电路22。即使这会导致电子设备1的芯片3由于与半导体激光器的发光相关联的发热而以与半导体基板2的热膨胀系数不同的热膨胀系数膨胀,多孔金属层41也会弹性变形,从而可以抑制凸块4中开路故障的发生。
多孔金属层41包含粒径为0.005μm~1.0μm的金属粒子。由于金属粒子的尺寸效应,多孔金属层41可以在低于块状金属的熔点的温度下进行金属接合。这允许电子设备1使用可以在相对较低的温度下进行金属接合的多孔金属层41来连接半导体基板2和芯片3的连接焊盘21和31,从而降低由于热量造成的损坏并提高可靠性。
在连接焊盘21、31和多孔金属层41之间设置的金属膜42、43中,膜厚与凸块4、4a的在与半导体基板2和芯片3的主面正交的方向上的厚度之比小于10%。这可以防止用于形成在光致抗蚀剂层51、52上图案化的凸块4、4a的贯通孔由于金属膜42、43的形成而变窄。结果,在光致抗蚀剂层51、52中图案化的贯通孔可以适宜地填充有将被用作凸块4、4a的材料的包含金属粒子的糊状物40。
在其中半导体基板2和芯片3通过凸块4和4a彼此连接的电子设备的情况下,设置在连接焊盘21、31和多孔金属层41之间的金属膜42、43的膜厚与凸块4、4a的在与半导体基板2和芯片3的主面正交的方向上的厚度的一半之比小于10%。这可以防止用于形成在光致抗蚀剂层51、52上图案化的凸块4、4a的贯通孔由于金属膜42、43的形成而变窄。结果,在光致抗蚀剂层51、52中图案化的贯通孔可以适宜地填充有将被用作凸块4、4a的材料的包含金属粒子的糊状物40。
电子设备1包括半导体基板2和凸块4。凸块4设置在设于半导体基板2的主面上的连接焊盘21的表面上。凸块4具有多孔金属层41和金属膜42。金属膜42设置在多孔金属层41和连接焊盘21之间以及多孔金属层41的侧面上。金属膜42的膜厚与凸块4的在与半导体基板2的主面正交的方向上的厚度之比小于10%。
这使得半导体基板2上的凸块4具有微细间距,并且与使用块状的金属凸块的情况相比,这允许通过低温低压处理对热膨胀系数与半导体基板2不同的芯片3进行倒装芯片安装。
电子设备1包括芯片3和凸块4a。凸块4a设置在设于芯片3的主面上的连接焊盘31的表面上。凸块4a具有多孔金属层41和金属膜43。金属膜43设置在多孔金属层41和连接焊盘31之间以及多孔金属层41的侧面上。金属膜43的膜厚与凸块4a的在与芯片3的主面正交的方向上的厚度之比小于10%。
这使得芯片3上的凸块4a具有微细间距,并且与使用块状的金属凸块的情况相比,这允许通过低温低压处理将芯片3倒装芯片安装在热膨胀系数与芯片3不同的半导体基板2上。
本文记载的效果仅为示例而非限制,并且还可以提供其他效果。
本技术还可以具有以下构成。
(1)一种电子设备,包括:
半导体基板;
芯片,其具有与所述半导体基板的热膨胀系数不同的热膨胀系数;和
凸块,其将设置在所述半导体基板和所述芯片的相对主面上的连接焊盘进行连接,其中,
所述凸块包括:
多孔金属层;和
金属膜,其设置在设于所述半导体基板上的连接焊盘和所述多孔金属层之间的部分以及设于所述芯片上的连接焊盘和所述多孔金属层之间的部分中的至少一者上,并且设置在所述多孔金属层的侧面上。
(2)根据(1)所述的电子设备,其中,
所述芯片具有与所述半导体基板的热膨胀系数相差0.1ppm/℃以上的热膨胀系数。
(3)根据(1)或(2)所述的电子设备,其中,
所述芯片是半导体激光器,和
所述半导体基板具有驱动所述半导体激光器的驱动电路。
(4)根据(1)~(3)中任一项所述的电子设备,其中,
所述多孔金属层包含粒径为0.005μm~1.0μm的金属粒子。
(5)根据(1)~(4)中任一项所述的电子设备,其中,
设置在所述连接焊盘和所述多孔金属层之间的所述金属膜的膜厚与所述凸块的在与所述主面正交的方向上的厚度之比小于10%。
(6)根据(1)~(4)中任一项所述的电子设备,其中,
设置在所述连接焊盘和所述多孔金属层之间的所述金属膜的膜厚与所述凸块的在与所述主面正交的方向上的厚度的一半之比小于10%。
(7)一种电子设备,包括:
半导体基板;和
凸块,其设置在设于所述半导体基板的主面上的连接焊盘的表面上,其中,
所述凸块包括:
多孔金属层;和
金属膜,其设置在所述多孔金属层和所述连接焊盘之间以及所述多孔金属层的侧面上,和
所述金属膜的膜厚与所述凸块的在与所述主面正交的方向上的厚度之比小于10%。
(8)一种电子设备,包括:
芯片;和
凸块,其设置在设于所述芯片的主面上的连接焊盘的表面上,其中,
所述凸块包括:
多孔金属层;和
金属膜,其设置在所述多孔金属层和所述连接焊盘之间以及所述多孔金属层的侧面上,和
所述金属膜的膜厚与所述凸块的在与所述主面正交的方向上的厚度之比小于10%。
附图标记列表
1 电子设备
2 半导体基板
21 连接焊盘
22 驱动电路
3 芯片
31 连接焊盘
32 发光单元
321 发光元件
4 凸块
4a 凸块
41 多孔金属层
42 金属膜
43 金属膜
Claims (8)
1.一种电子设备,包括:
半导体基板;
芯片,其具有与所述半导体基板的热膨胀系数不同的热膨胀系数;和
凸块,其将设置在所述半导体基板和所述芯片的相对主面上的连接焊盘进行连接,其中,
所述凸块包括:
多孔金属层;和
金属膜,其设置在设于所述半导体基板上的连接焊盘和所述多孔金属层之间的部分以及设于所述芯片上的连接焊盘和所述多孔金属层之间的部分中的至少一者上,并且设置在所述多孔金属层的侧面上。
2.根据权利要求1所述的电子设备,其中,
所述芯片具有与所述半导体基板的热膨胀系数相差0.1ppm/℃以上的热膨胀系数。
3.根据权利要求1所述的电子设备,其中,
所述芯片是半导体激光器,和
所述半导体基板具有驱动所述半导体激光器的驱动电路。
4.根据权利要求1所述的电子设备,其中,
所述多孔金属层包含粒径为0.005μm~1.0μm的金属粒子。
5.根据权利要求1所述的电子设备,其中,
设置在所述连接焊盘和所述多孔金属层之间的所述金属膜的膜厚与所述凸块的在与所述主面正交的方向上的厚度之比小于10%。
6.根据权利要求1所述的电子设备,其中,
设置在所述连接焊盘和所述多孔金属层之间的所述金属膜的膜厚与所述凸块的在与所述主面正交的方向上的厚度的一半之比小于10%。
7.一种电子设备,包括:
半导体基板;和
凸块,其设置在设于所述半导体基板的主面上的连接焊盘的表面上,其中,
所述凸块包括:
多孔金属层;和
金属膜,其设置在所述多孔金属层和所述连接焊盘之间以及所述多孔金属层的侧面上,和
所述金属膜的膜厚与所述凸块的在与所述主面正交的方向上的厚度之比小于10%。
8.一种电子设备,包括:
芯片;和
凸块,其设置在设于所述芯片的主面上的连接焊盘的表面上,其中,
所述凸块包括:
多孔金属层;和
金属膜,其设置在所述多孔金属层和所述连接焊盘之间以及所述多孔金属层的侧面上,和
所述金属膜的膜厚与所述凸块的在与所述主面正交的方向上的厚度之比小于10%。
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JP2751912B2 (ja) * | 1996-03-28 | 1998-05-18 | 日本電気株式会社 | 半導体装置およびその製造方法 |
JPH11168116A (ja) * | 1997-12-04 | 1999-06-22 | Mitsui High Tec Inc | 半導体チップ用電極バンプ |
JP4661122B2 (ja) * | 2004-05-18 | 2011-03-30 | ソニー株式会社 | 部品実装配線基板および配線基板への部品の実装方法 |
JP5363839B2 (ja) * | 2008-05-12 | 2013-12-11 | 田中貴金属工業株式会社 | バンプ及び該バンプの形成方法並びに該バンプが形成された基板の実装方法 |
JP5176750B2 (ja) * | 2008-07-24 | 2013-04-03 | ソニー株式会社 | 発光素子組立体、面状光源装置、及び、液晶表示装置組立体 |
JP2011077308A (ja) | 2009-09-30 | 2011-04-14 | Fujitsu Ltd | 半導体装置の実装方法 |
JP2011165871A (ja) * | 2010-02-09 | 2011-08-25 | Denso Corp | 電子装置およびその製造方法 |
US10177079B2 (en) * | 2010-03-19 | 2019-01-08 | Furukawa Electric Co., Ltd. | Conductive connecting member and manufacturing method of same |
JP5782823B2 (ja) * | 2011-04-27 | 2015-09-24 | 日亜化学工業株式会社 | 窒化物半導体発光素子およびその製造方法 |
US8569109B2 (en) * | 2011-06-30 | 2013-10-29 | Infineon Technologies Ag | Method for attaching a metal surface to a carrier, a method for attaching a chip to a chip carrier, a chip-packaging module and a packaging module |
JP6379342B2 (ja) * | 2014-07-09 | 2018-08-29 | 三菱マテリアル株式会社 | 半導体装置及びその製造方法 |
TWI662657B (zh) * | 2015-04-07 | 2019-06-11 | 聯華電子股份有限公司 | 半導體元件的堆疊結構 |
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EP4191644A1 (en) | 2023-06-07 |
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