TW202002113A - 半導體裝置的製造方法 - Google Patents

半導體裝置的製造方法 Download PDF

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TW202002113A
TW202002113A TW108121400A TW108121400A TW202002113A TW 202002113 A TW202002113 A TW 202002113A TW 108121400 A TW108121400 A TW 108121400A TW 108121400 A TW108121400 A TW 108121400A TW 202002113 A TW202002113 A TW 202002113A
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Taiwan
Prior art keywords
etch stop
stop layer
interlayer dielectric
layer
conductive
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TW108121400A
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English (en)
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黃建樺
魏慈慧
蔡承孝
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台灣積體電路製造股份有限公司
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Publication of TW202002113A publication Critical patent/TW202002113A/zh

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明實施例提供一種半導體裝置的製造方法，所述方法包含：提供包含導電元件和層間介電質的一結構，其中所述層間介電質包含矽且圍繞所述導電元件；形成一蝕刻停止層於所述導電元件和層間介電質之上，其中所述蝕刻停止層包含金屬氧化物，其中所述蝕刻停止層包含與導電元件接觸的第一部分和與層間介電質接觸的第二部分；烘烤所述蝕刻停止層以將位於蝕刻停止層的第二部分中的金屬氧化物轉換為金屬矽氧化物；以及選擇性蝕刻所述蝕刻停止層以移除蝕刻停止層的第一部分，但不移除蝕刻停止層的第二部分。

Description

半導體裝置的製造方法
本發明實施例係關於半導體製造技術，特別是有關於半導體裝置中可選擇性移除的蝕刻停止層的製造方法。
半導體積體電路（integrated circuit；IC）產業已歷經快速成長。積體電路之材料和設計上的技術進展已經產生了數個世代的積體電路，每一世代皆較前一世代具有更小且更複雜的電路。然而，這些進展也增加了加工和製造積體電路的複雜度，而且為了實現這樣的進展，積體電路加工和製造上也需要有相同的進步。在積體電路演進的歷程中，當幾何尺寸（亦即使用生產製程可以產生的最小元件）縮減時，功能密度（亦即單位晶片面積的內連接裝置數量）通常也增加。
幾何尺寸的縮減導致了半導體製造的挑戰。舉例來說，隨著金屬元件之間的節距下降，疊對（overlay）控制變得更困難，因為等量的疊對位移（overlay shift）現在對於裝置效能具有更顯著的影響（舉例來說，未對準的導孔（via）可能導致此導孔和相鄰金屬元件之間的電流洩漏）。疊對位移可能降低裝置效能及/或引起可靠性問題。因此，雖然現有的半導體裝置及其製造通常已經足以達到它們的預期目的，但它們並非在所有面向皆令人滿意。
根據本發明實施例，提供一種半導體裝置的製造方法，包含：提供包含導電元件和層間介電質的一結構，其中所述層間介電質包含矽且圍繞所述導電元件；形成一蝕刻停止層於所述導電元件和層間介電質之上，其中所述蝕刻停止層包含金屬氧化物，其中所述蝕刻停止層包含與導電元件接觸的第一部分和與層間介電質接觸的第二部分；烘烤所述蝕刻停止層以將位於蝕刻停止層的第二部分中的金屬氧化物轉換為金屬矽氧化物；以及選擇性蝕刻所述蝕刻停止層以移除蝕刻停止層的第一部分，但不移除蝕刻停止層的第二部分。
根據本發明實施例，提供一種半導體裝置，包含：基板；第一和第二導電元件，設置於所述基板上；層間介電質，設置於所述基板上和所述第一和第二導電元件之間；蝕刻停止層，包含金屬矽氧化物，延伸於所述層間介電質之上並與所述層間介電質接觸，其中所述蝕刻停止層未延伸於第一導電元件或第二導電元件之上；以及導電孔，設置於所述第一導電元件之上且與第一導電元件電性接觸，其中所述導電孔至少被所述層間介電質和蝕刻停止層的一部分與第二導電元件隔開。
根據本發明實施例，提供一種半導體裝置的製造方法，包含：形成第一蝕刻停止層，包含與導電元件接觸的第一部分且包含與圍繞所述導電元件的第一層間介電質接觸的第二部分，其中所述第一蝕刻停止層的第一部分包含金屬氧化物，且所述第一蝕刻停止層的第二部分包含金屬矽氧化物；蝕刻所述第一蝕刻停止層以移除第一蝕刻停止層的第一部分，但不移除第一蝕刻停止層的第二部分；形成一第二蝕刻停止層於所述第一蝕刻停止層的第二部分之上和導電元件之上；形成一第二層間介電質於所述第二蝕刻停止層之上；蝕刻一開口，垂直地穿過所述第二層間介電質和第二蝕刻停止層以露出所述導電元件的上表面；以及以導電材料填充所述開口以形成導電孔於開口中，其中所述導電孔與所述導電元件的上表面接觸但被第一蝕刻停止層的第二部分與第一層間介電質隔開。
以下內容提供了許多不同的實施例或範例，用於實施所提供之標的之不同部件。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例來說，敘述中若提及第一部件形成於第二部件上方，可能包含形成第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。此外，本發明實施例在不同範例中可重複使用參考數字及/或字母，此重複是為了簡化和清楚之目的，並非代表所討論的不同實施例及/或組態之間有特定的關係。
此外，其中可能用到與空間相對用語，例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」及類似的用詞，這些空間相對用語係為了便於描述如圖所示之一個（些）元件或部件與另一個（些）元件或部件之間的關係。這些空間相對用語包含使用中或步驟中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），則其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
更進一步，當以「約（about）」、「大約（approximate）」及其類似的用詞描述一個數字或一個數字範圍時，所述用詞係用以涵蓋在合理範圍內的數字，包含所描述的數字，例如在所描述數字的+/− 10%以內或本技術領域中具有通常知識者可理解的其他數值。舉例來說，用詞「約5 nm」包含從4.5 nm至5.5 nm的尺寸範圍。
本發明整體涉及但不限於減少或防止與疊對控制相關的問題。疊對可以指例如積體電路晶片的半導體裝置中不同膜層的各種元件之間的對準。舉例來說，積體電路晶片可包含由多個內連線層（也稱為不同的金屬化層）構成的內連線結構。每個內連線層可包含由層間介電質（interlayer dielectric；ILD）圍繞的一個或多個導電元件，例如導孔、接觸件（contact）或金屬線。在一些情況下，一內連線層（例如上層）中的第一導電元件可能需要電性連接至另一內連線層（例如下層）中的第二導電元件。因此，期望這兩個導電元件能垂直地對齊。如果疊對控制不理想，則兩個導電元件之間可能存在顯著量的未對準（misalignment），這可能導致例如第二導電元件旁邊的層間介電質之過蝕刻（虎齒狀圖案）的問題。過蝕刻可縮短抵達相鄰導電元件的漏電路徑，這又可能導致可靠性及/或效能問題，例如時間相依介電崩潰（time-dependent dielectric breakdown；TDDB）或其他電流洩漏問題。
為了克服上述討論的問題，本發明實施例形成能夠增加漏電路徑長度的蝕刻停止層（etch stop layer；ESL）的部分。在一些實施例中，這透過先形成蝕刻停止層（包含金屬氧化物）於導電元件上和層間介電質上來實現，所述層間介電質包含矽且圍繞導電元件。接著，在升高的溫度下烘烤蝕刻停止層以改變其化學組成。舉例來說，金屬矽氧化物可以形成於與層間介電質接觸的蝕刻停止層之一部分中，因為矽滲透至蝕刻停止層中以與包含在其中的金屬氧化物反應。然後，使用包含鹼性胺（alkali amine）的濕蝕刻劑選擇性移除蝕刻停止層。在選擇性蝕刻期間，移除了蝕刻停止層包含金屬氧化物的部分，但是保留蝕刻停止層包含金屬矽氧化物的部分。剩餘的蝕刻停止層部分保護層間介電質在通孔（via hole）蝕刻製程中免於被不期望地蝕刻。
本發明的一個優點是減輕了由疊對位移引起的問題。舉例來說，在理想情況下，通孔應該與導電元件對準。然而，由於疊對位移，通孔和導電元件可能未對準。如果沒有實現可選擇性移除的蝕刻停止層，則這種未對準將導致位於通孔下方的層間介電質之一部分無意中被蝕刻。當以金屬填充通孔時，無意中被蝕刻的孔洞也將被填充，如果通孔已對準，則提供了更靠近下一個導電元件的導電路徑。這可能導致可靠性及/或效能問題，例如崩潰電壓、時間相依介電崩潰或漏電。
如前所述，在現實世界的半導體製造中，疊對控制可能不是最佳的，特別是當幾何尺寸縮小時，將導致通孔和導電元件之間的未對準。但此處揭露之蝕刻停止層的蝕刻選擇性有助於防止由未對準所引起位於通孔下方且與導電元件相鄰之層間介電質被不期望的蝕刻。根據本發明實施例的各個面向，含矽蝕刻停止層保護位於未對準通孔下方的層間介電質部分免於被蝕刻。如此一來，所得到的半導體裝置具有更好的可靠性及/或提升的效能。
現在將參照圖式更詳細地描述本發明的各個面向。在此面向，第1A～1I圖根據本發明實施例繪示各製造階段之半導體裝置的示意剖面側視圖，而第2圖繪示根據本發明實施例進行之方法流程圖。
現在參照第1A圖，其繪示半導體裝置（或半導體結構）100的一部分。半導體裝置100包含基板102，基板102可以由矽或例如鍺的其他半導體材料組成。基板102也可以包含化合物半導體，例如碳化矽、砷化鎵、砷化銦或磷化銦。在一些實施例中，基板102可以包含合金半導體，例如矽鍺、碳化矽鍺、磷化鎵砷或磷化鎵銦。在一些實施例中，基板102可以包含磊晶層，例如覆蓋塊狀半導體的磊晶層。可形成各種微電子元件於基板102中或基板102上，例如包含源極/汲極及/或閘極的電晶體元件、包含淺溝槽隔離（shallow trench isolation；STI）的隔離結構或任何其他合適的元件。
半導體裝置100也包含內連線層110。內連線層110可以是多層內連線結構（multi-layered interconnect structure；MLI）中的內連線層之一，其形成於基板102之上且可以包含在半導體裝置100的各種微電子元件之間提供內連線（例如佈線）的多個圖案化介電層和導電層。在內連線層110和基板102之間可以存在中間層或元件，但是為了簡單起見，並未繪示出這些膜層或元件。
在一實施例中，內連線層110包含多個導電元件（包含導電元件120和122）以及部分或完全地圍繞導電元件120和122的層間介電質130。導電元件120和122可以包含接觸件、導孔或金屬線。在一些實施例中，導電元件120和122包含導電材料，例如鋁、鋁合金、鈦、氮化鈦、鎢、銅、銅合金、鉭、氮化鉭、鎢、釕、銠或前述之組合。當導電元件120和122包含金屬材料時，它們也稱為金屬元件。需注意的是，導電元件120和122不包含任何矽（純矽或矽化物形式），原因是導電元件120和122不應在烘烤過程中與疊對的膜層（例如，如下所述之蝕刻停止層140）反應而形成矽化物。
與導電元件120和122不同，層間介電質130可以是含矽的二氧化物材料，其中矽以各種合適的形式存在。舉例來說，層間介電質130可以包含二氧化矽或低介電常數（low-k）介電材料，其介電常數值小於二氧化矽的介電常數值（約為4）。在一些實施例中，低介電常數介電材料包含多孔有機矽酸鹽薄膜，例如矽氧烷（SiOCH）、四乙氧基矽烷（tetraethylorthosilicate；TEOS）氧化物、未摻雜的矽酸鹽玻璃、摻硼氧化矽例如硼磷矽酸鹽玻璃（borophosphosilicate glass；BPSG）、熔融石英玻璃（fused silica glass；FSG）、磷矽酸鹽玻璃（phosphosilicate glass；PSG）、硼摻雜二氧化矽、碳摻雜二氧化矽、多孔二氧化矽、多孔碳摻雜二氧化矽、碳氮化矽（silicon carbon nitride；SiCN）、碳氧化矽（silicon oxycarbide；SiOCN）、旋塗矽基聚合物介電質或前述之組合。應理解的是，可以對內連線層110進行例如化學機械研磨（chemical mechanical polishing；CMP）的平坦化製程，以使導電元件120和122及/或層間介電質130的上表面變平。
參照第1B圖，沉積第一蝕刻停止層140在內連線層110上。沉積製程包含化學氣相沉積（chemical vapor deposition；CVD）、物理氣相沉積（physical vapor deposition；PVD）、原子層沉積（atomic layer deposition；ALD）、熱原子層沉積（thermal ALD）或前述之組合。在一些實施例中，蝕刻停止層140包含金屬氧化物，例如氧化鋁（AlOx）、氧化鉿（HfOx）、氧化鈦（TiOx）、氧化錳（MnOx）、氧化釩（VOx）、其他合適的金屬氧化物或前述之組合。在一些實施例中，蝕刻停止層140具有介於10至60埃（Å）之整體均勻的厚度。這樣的厚度範圍使得蝕刻停止層140不僅提供足夠的保護（就上方導孔結構和下方導電元件之間的漏電路徑而言），而且還使相鄰導電元件120和122之間的寄生電容最小化（因為在蝕刻停止層140中的材料的介電常數值高於層間介電質130中的低介電常數材料的介電常數值）。
參照第1C圖，蝕刻停止層140在升高的溫度下經歷烘烤製程。現有技術並未進行這種烘烤製程。在烘烤期間，蝕刻停止層140與層間介電質130接觸的一或多個部分142改變或轉換其化學組成，舉例來說，層間介電質130中包含的矽（以任何合適的形式）遷移或滲透至蝕刻停止層140中，接著與蝕刻停止層之部分142的金屬氧化物反應，形成金屬矽氧化物。在一些實施例中，烘烤後的蝕刻停止層之部分142包含金屬矽氧化物，例如氧化鋁矽（AlSiOx）、氧化鉿矽（HfSiOx）、氧化鈦矽（TiSiOx）、氧化錳矽（MnSiOx）、氧化釩矽（VSiOx）、其他合適的金屬矽氧化物或前述之組合。需注意的是，矽可以以任何合適的化學形式存在於金屬矽氧化物中。然而，在烘烤期間，蝕刻停止層140與導電元件120和122接觸的一或多個其他部分144可不形成任何金屬矽氧化物，因為導電元件120和122不包含任何矽材料。如第1C圖所示，因為蝕刻停止層之部分142和144與層間介電質130和導電元件120和122的相應邊緣對準，所以化學轉換是一種自對準（self-aligning）過程。需注意的是，即使在自對準過程中，矽也可能不完全沿著垂直線遷移或滲透至蝕刻停止層中，因此蝕刻停止層之部分142和144的邊緣可能不會完全地（strictly）與層間介電質130及導電元件120和122的相應邊緣對準。
在一些實施例中，在100°C至400°C的溫度下烘烤具有蝕刻停止層140的半導體裝置100。需注意的是，在烘烤期間可以例如根據預定的溫度曲線（temperature profile）而改變溫度。在一些實施例中，持續烘烤30秒至10分鐘。在一些實施例中，可在環境氣體中進行烘烤，所述環境氣體包含氮氣（N2 ）、氮氣和氫氣（H2 ）的組合、氮氣和惰性氣體例如氬氣（Ar）的組合或任何其它合適的氣體組合物。合適的環境氣體（例如N2 +H2 ）透過使矽更容易地滲透至蝕刻停止層之部分142中而有助於增強矽化過程。
現在參照第1D圖，進行濕蝕刻製程以從半導體裝置100的上表面選擇性地移除部分的蝕刻停止層140。在一實施例中，蝕刻溶液150被配置以保留與層間介電質130接觸的蝕刻停止層部分142，但是移除與導電元件120和122接觸的蝕刻停止層部分144。換句話說，蝕刻後的蝕刻停止層140保留在層間介電質130的上表面上，但不保留在導電元件120和122的上表面上。如第1D圖所示，沿著導電元件120和122的上表面產生台階高度輪廓（step height profile）或幾何形狀。
選擇性移除蝕刻停止層140的原因是蝕刻停止層之部分142和144間的蝕刻選擇性，其在烘烤後包含不同的材料。在一些實施例中，蝕刻停止層之部分142和144間的蝕刻選擇性是顯著的（例如約1：30或更高）。也就是說，當暴露於蝕刻溶液150時，蝕刻停止層之部分144（其包含金屬氧化物）的蝕刻速率比蝕刻停止層之部分142（其包含金屬矽氧化物）的蝕刻速率快至少30倍。在一些實施例中，蝕刻停止層之部分144的蝕刻速率為每分鐘約20 Å或更高。此外，一旦露出導電元件120和122的上表面，就可以停止蝕刻，因為蝕刻溶液150在導電元件120和122上具有低蝕刻速率。在一些實施例中，導電元件120和122的蝕刻速率每分鐘不超過1 Å。
在一些實施例中，蝕刻溶液150包含鹼性胺，例如氫氧化銨（ammonia hydroxide，NH4 OH）、羥胺（hydroxylamine，NH2 OH）、其他合適的化合物或前述之組合。蝕刻溶液150的pH值可以設定在8～13之間，以防止或最小化矽與蝕刻溶液150間的反應（因為矽在酸性環境中更具活性）。在一實施例中，蝕刻溶液150中鹼性胺的濃度為8%或更低（除非另有說明，百分比是指重量）。鹼性胺中的氫氧化物（OH−）使金屬氧化物（包含在蝕刻停止層之部分144中）和金屬矽氧化物（包含在蝕刻停止層之部分142中）間產生蝕刻速率差異。具體地，以下例示公式表示氫​​氧化物與金屬氧化物反應形成可溶於蝕刻溶液150的金屬氫氧化物（例如氫氧化鋁），但氫氧化物不與金屬矽氧化物反應： l 蝕刻停止層之部分144中的例示反應：2OH− +3H2 O+Al2 O3 à 2Al(OH)4 − (aq) l 蝕刻停止層之部分142中沒有反應：OH− +Al(Si)Ox à 沒有反應。
為了增強蝕刻效能，蝕刻溶液150也可包含溶劑，例如二乙二醇單甲基醚（diethylene glycol monomethyl ether）、乙二醇（ethylene glycol）、丁基二乙二醇（butyl diethylene glycol）和二甲亞碸（dimethyl sulfoxide）、任何其他合適的溶劑或前述之組合。另外，蝕刻溶液150可包含螯合劑，例如乙二胺四乙酸（ethylenediaminetetraacetic acid）、二伸乙基三胺五乙酸（diethylenetriaminepentaacetic acid）、其他合適的螯合劑或前述之組合。此外，蝕刻溶液150可包含金屬腐蝕抑制劑以幫助防止金屬元件的腐蝕。金屬腐蝕抑制劑的合適候選物可包含苯並三唑（benzotriazole；BTA）、十二胺（dodecylamine）或前述之組合。蝕刻溶液150也可以包含例如濃度為20%至80%的水。在一些實施例中，在介於室溫至60°C的溫度下進行濕蝕刻製程。需注意的是，在蝕刻期間可以改變溫度。在一些實施例中，持續蝕刻1至5分鐘。
現在參照第1E圖，進行沉積製程以形成第二蝕刻停止層160於半導體裝置100之上。在一些實施例中，沉積製程可包含化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、熱原子層沉積或前述之組合。第二蝕刻停止層160可共形地（conformally）形成於蝕刻停止層140的剩餘部分之上和導電元件120和122的上表面之上。在一些實施例中，蝕刻停止層160包含介電材料，其可以是與蝕刻停止層140的材料相同或不同的材料。在一些實施例中，蝕刻停止層160包含金屬氧化物，例如氧化鋁（AlOx）、氧化鉿（HfOx）、氧化鈦（TiOx）、氧化錳（MnOx）、氧化釩（VOx）、其他合適的金屬氧化物或前述之組合。或者，蝕刻停止層160可包含碳氮化矽（SiCN）、碳氧化矽（SiOCN）、碳化矽（SiC）、氮化矽（SiN）或前述之組合。在一些實施例中，蝕刻停止層160具有50 Å或更小的厚度。蝕刻停止層160可用於例如黏著、防止金屬氧化、防止金屬損傷和確保普遍蝕刻效能的目的。
繼續參照第1E圖，進行另一沉積製程以形成層間介電質170於蝕刻停止層160之上。沉積製程可包含例如化學氣相沉積、物理氣相沉積、原子層沉積或前述之組合。在一些實施例中，層間介電質170可包含低介電常數（low-k）介電材料，例如矽氧烷（SiOCH）、四乙氧基矽烷（TEOS）、硼磷矽酸鹽玻璃（BPSG）、熔融石英玻璃（FSG）等。在一些實施例中，層間介電質130和層間介電質170具有相同的材料組成。
在一些實施例中，形成蓋層（capping layer）172於層間介電質170上。可以使用物理氣相沉積、化學氣相沉積、原子層沉積及/或其他合適的方法來沉積蓋層172。蓋層172可以使用任何合適的材料，例如矽、氧化矽（SiO2 ）、氮化矽（SiN）、碳氮化矽（SiCN）、碳化矽（SiC）或前述之組合。
在一些實施例中，形成硬罩幕（hard mask；HM）層174於半導體裝置100的頂表面之上。硬罩幕層174可以包含任何合適的材料。在一實施例中，硬罩幕層174包含矽、碳氮化矽（SiCN）、氧化鉿（HfO2 ）、氧化鋁（Al2 O3 ）、氧化鋯（ZrO2 ）、氮化鈦（TiN）、碳化鎢（WC）、其他隔離材料或前述之組合。可以藉由物理氣相沉積、化學氣相沉積、原子層沉積、電鍍或其他合適的方法來形成硬罩幕層174。
現在參照第1F圖，進行一或多個製程以蝕刻出開口180，開口180從頂部到底部垂直延伸穿過硬罩幕層174、蓋層172和層間介電質170以到達蝕刻停止層160。在一些實施例中，先對硬罩幕層174進行微影製程以定義開口180的位置（舉例來說，透過光阻沉積、曝光和光阻移除）。然後，可以使用蝕刻製程來移除硬罩幕層174。所述蝕刻製程可以包含濕蝕刻或乾蝕刻。可以使用相同的蝕刻製程或另一種蝕刻製程來移除蓋層172和層間介電質170。在一實施例中，使用乾蝕刻來移除蓋層172和層間介電質170。如第1F圖所示，開口180並未與金屬元件120完美地對齊，當疊對結束時可能發生這樣的狀況。在第1F圖中，開口180在蝕刻停止層160處停止，蝕刻停止層160在蝕刻製程中具有非常低的蝕刻速率。蝕刻停止層160（有時稱為襯層）有助於確保穿過不同材料層正確創造開口。
現在參照第1G圖，使用另一蝕刻製程來移除位於開口180底部上的一部分蝕刻停止層160。所述蝕刻製程可以包含濕蝕刻或乾蝕刻，且比周圍材料更快地蝕刻蝕刻停止層160。其結果，開口180延伸至導電元件120的上表面。在一些實施例中，藉由蝕刻製程部分地蝕刻位於開口180下方的中間蝕刻停止層之部分142。當（沉積的）中間蝕刻停止層之部分142和蝕刻停止層160是相同材料時，控制蝕刻製程的持續時間（duration），使得中間蝕刻停止層之部分142不被完全蝕刻。否則，當（沉積的）中間蝕刻停止層之部分142和蝕刻停止層160是不同材料時，蝕刻製程可以在蝕刻停止層之部分142上具有相對較低的蝕刻速率（但是中間蝕刻停止層之部分142的上方角落仍然可能被切削，如第1G圖所示）。在任何情況下，蝕刻製程確保開口180不會到達層間介電質130。
稍後將以導電材料填充開口180以例如形成像是導孔或金屬線的導電元件。理想地，開口180應該與導電元件120對準，使得導電元件120和將在開口180中形成的導電元件之間可以建立良好的電性連接。然而，在現實世界的半導體製造中通常是這種情況，由於疊對控制能力的限制，開口180和導電元件120之間的對準是不完美的。隨著每個半導體技術節點的幾何尺寸縮小，這個問題變得更加嚴重。因此，如第1F圖所示，在開口180和導電元件120之間存在未對準，這表現在開口180的「向右」移動，使得現在的開口180位於一部分的層間介電質上方。在傳統的半導體裝置中，由於過蝕刻，這種未對準可能導致位於開口180下方的層間介電質130部分被不期望地蝕刻。然後，當導電材料填充開口180時，層間介電質130的過蝕刻部分將被導電材料填充。這可能導致例如時間相依介電崩潰或半導體裝置100內電流洩漏的問題。
本發明實施例透過形成蝕刻停止層之部分142克服了上述問題，蝕刻停止層之部分142防止層間介電質130的潛在蝕刻（在創造開口180時）。更詳細地，如第1G圖所示，經蝕刻的開口180在中間蝕刻停止層之部分142處垂直地停止。如前所述，蝕刻停止層142和蝕刻停止層160的材料組成可以配置成在創造開口180的期間使兩者之間存在顯著的蝕刻選擇性。如此一來，可以大致蝕刻所述蝕刻停止層160而不顯著影響中間蝕刻停止層之部分142，這使得中間蝕刻停止層之部分142做為保護結構。由於保留了中間蝕刻停止層之部分142，因此也保護了位於中間蝕刻停止層之部分142下方的層間介電質130部分免於被蝕刻。
現在參照第1H圖，進行沉積製程以形成導電材料190於半導體裝置100之上。在不同實施例中，導電材料包含銅、鎢、鋁、其他合適的金屬、金屬合金或前述之組合。沉積製程可以包含例如化學氣相沉積、電鍍、物理氣相沉積、原子層沉積或前述之組合。在一些實施例中，沉積的導電材料190包含金屬或金屬合金，例如銅、鋁、鎢、鈦或前述之組合。在一些實施例中，可形成阻障層（barrier layer）（例如鈦、氮化鈦、鉭、氮化鉭或前述之組合）於開口180的側壁上，並於此後將導電材料填充在開口180中。
沉積的導電材料190之一部分填充開口180以形成導電孔（conductive via）192。在一些實施例中，導電孔192做為導電元件，其電性連接至下方的導電元件120。同樣地，由於中間蝕刻停止層之部分142在蝕刻導孔開口（via opening）期間做為保護層，所以位於中間蝕刻停止層之部分142下方的層間介電質130部分未被蝕刻。因此，即使導電元件120和開口180因爲疊對位移而未對準，沉積的導電材料190也不會不經意地到達層間介電質130。
現在參照第1I圖，進行例如化學機械平坦化（chemical mechanical planarization；CMP）的平坦化製程以平坦化導電材料190的上部分，從而留下被層間介電質170圍繞的導電孔192。可將導電孔192和層間介電質170視為是多層內連線結構的第二內連線層194的一部分，其位於內連線層110上方。
在一些實施例中，內連線層110是Mn （例如金屬-0）內連線層，而內連線層194是Mn+1 （金屬-1）內連線層。在一些實施例中，Mn 內連線層中的節距（相鄰導電元件之間的距離）介於16至40 nm之間，且導電元件的臨界尺寸（critical dimension；CD）約為20 nm或更小。在一些實施例中，Mn+1 內連線層中導電孔的底表面之臨界尺寸約為24 nm或更小，在這種情況下，疊對位移容差（tolerance）可約為8 nm或更小。需注意的是，疊對位移容差在很大程度上取決於Mn 內連線層中的節距（舉例來說，如果節距為40 nm，則疊對位移容差可約為8 nm，但如果節距縮小到20 nm，則疊對位移容差可以縮小至4～6 nm）。本發明實施例藉由使用可選擇性移除的蝕刻停止層140來改善疊對位移容差。
需注意的是，在所述製造階段，大部分中間蝕刻停止層之部分142（如果不是全部）仍然設置在導電孔192和層間介電質130之間。換句話說，中間蝕刻停止層之部分142將導電孔192和層間介電質130隔開，並且防止或最小化在導電孔192和導電元件122之間流動的漏電流。在一些實施例中，取決於蝕刻停止層的厚度，使用此處揭露的技術，漏電流可以降低1至2個等級。中間蝕刻停止層之部分142在半導體裝置100的最終結構中保持可被檢測的。實際上，包含上述金屬矽氧化物的中間蝕刻停止層之部分142的存在是本發明的獨特物理特性之一，且可代表已經進行了本發明實施例的步驟。
第2圖是根據本發明的各個面向製造半導體裝置（例如半導體裝置100）的方法200之流程圖。應結合第1A～1I圖理解方法200。首先，方法200包含步驟210，用於提供包含導電元件（例如導電元件120）和可以完全或部分地圍繞導電元件120的層間介電質（例如層間介電質130）的結構。以上參照第1A圖描述了更多細節。
方法200包含步驟220，在導電元件和層間介電質之上形成蝕刻停止層，例如蝕刻停止層140，其包含金屬氧化物。以上參照第1B圖描述了更多細節。方法200包含烘烤蝕刻停止層以轉換其化學組成的步驟230。在一實施例中，在化學組成轉換之後，與導電元件接觸的蝕刻停止層的第一部分（例如蝕刻停止層之部分144）不包含任何金屬矽氧化物，而與層間介電質接觸的蝕刻停止層的第二部分（例如蝕刻停止層之部分142）包含金屬矽氧化物。因此，烘烤選擇性地將蝕刻停止層之部分142轉換成金屬矽氧化物。在烘烤期間，透過層間介電質中的矽與蝕刻停止層的第二部分中的金屬氧化物間的化學反應來形成金屬矽氧化物。以上參照第1C圖描述了更多細節。
方法200包含步驟240，選擇性地蝕刻所述蝕刻停止層，以移除蝕刻停止層的第一部分而不移除蝕刻停止層的第二部分。需注意的是，實際上，不移除膜層或結構可能不是絕對的（亦即，即使在蝕刻選擇性之間存在顯著的差異，仍然可能移除所述膜層或結構的一小部分）。在一實施例中，蝕刻停止層的選擇性蝕刻被配置為使得蝕刻停止層的第一部分的蝕刻速率顯著地比蝕刻停止層的第二部分的蝕刻速率大（例如至少快30倍）。以上參照第1D圖描述了更多細節。
方法200包含步驟250，形成第二蝕刻停止層（例如蝕刻停止層160）於第一蝕刻停止層的第二部分之上和第一導電元件之上。在步驟252，可形成第二層間介電質（例如層間介電質170）於第二蝕刻停止層之上。在步驟254，可形成蓋層（例如蓋層172）於第二層間介電質之上。在步驟256，可形成硬罩幕層（例如硬罩幕層174）於蓋層之上。以上參照第1E圖描述了關於步驟250～256的更多細節。
方法200包含步驟258，蝕刻出露出第一導電元件之上表面的開口（例如開口180）。開口可與導電元件完全對準（當沒有疊對位移時）或者與導電元件部分對準（當存在一些疊對位移時）。在任何情況下，第一蝕刻停止層的第二部分保護位於其下方的第一層間介電質的一部分免於被蝕刻。以上參照第1F圖和第1G圖描述了更多細節。
方法200包含步驟260，以導電材料（例如導電材料190）填充開口，以形成與導電元件接觸的導電孔（例如導電孔192）。以上參照第1H圖描述了更多細節。在一些實施例中，步驟260可以包含如參照第1I圖所述的化學機械平坦化製程。
應理解的是，方法200僅僅是範例，並非用於將本發明實施例限制為超出明確敘述的內容。可以在方法200之前、期間和之後提供額外的步驟，並且可以取代、消除或移動所述的一些步驟以用於方法200的額外實施例。也應理解的是，本發明的各個面向可以應用於平面電晶體以及鰭式場效電晶體（FinFET）裝置。舉例來說，方法200可以包含在進行步驟210之前形成電晶體的源極/汲極區域和閘極結構，以及在進行步驟260之後形成額外的內連線層、封裝和測試。可以進行其他步驟，但是為了簡單起見，不在此詳細討論。
基於以上的討論，可以看出本發明實施例提供優於傳統裝置及其製造方法的優點。然而，可理解的是，其他實施例可以提供額外的優點，並非所有優點都必須在此公開，且並非所有實施例都需要有特定優點。
本發明的一個優點是減輕了由疊對位移引起的問題。舉例來說，在理想情況下，通孔（via hole）應該與導電元件對準。然而，由於疊對位移，通孔和導電元件可能未對準。如果沒有實施可選擇性移除的蝕刻停止層，則這種未對準將導致位於通孔下方的層間介電質的一部分被不想要地蝕刻。這可能導致可靠性及/或效能問題，例如崩潰電壓、時間相依介電崩潰或漏電。在此，可選擇性移除的蝕刻停止層做為導孔和層間介電質之間的隔板（separator）和絕緣體。其結果，蝕刻停止層保護了下方的層間介電質部分在通孔蝕刻製程中免於被不期望地蝕刻，這反過來改善了半導體裝置的可靠性及/或效能。
本發明實施例的一個面向包含一種半導體裝置的製造方法，所述方法包含：提供包含導電元件和層間介電質的一結構，其中所述層間介電質包含矽且圍繞所述導電元件，以及形成一蝕刻停止層於所述導電元件和層間介電質之上，所述蝕刻停止層包含金屬氧化物。所述蝕刻停止層包含與導電元件接觸的一第一部分和與層間介電質接觸的一第二部分。所述方法更包含烘烤所述蝕刻停止層以將位於蝕刻停止層的第二部分中的金屬氧化物轉換為金屬矽氧化物，以及選擇性蝕刻所述蝕刻停止層以移除蝕刻停止層的第一部分，但不移除蝕刻停止層的第二部分。
在一些實施例中，所述蝕刻停止層被形成為具有介於10至60 Å的厚度。在一些實施例中，烘烤所述蝕刻停止層不會將位於蝕刻停止層的第一部分中的金屬氧化物轉換為金屬矽氧化物。在烘烤期間，藉由層間介電質中的矽與蝕刻停止層的第二部分中的金屬氧化物間的化學反應形成位於所述蝕刻停止層的第二部分中的金屬矽氧化物。在包含氮氣和氫氣的環境氣體中烘烤所述蝕刻停止層。在一些實施例中，在介於100°C至400°C的溫度下烘烤所述蝕刻停止層。在一些實施例中，位於所述蝕刻停止層的第二部分中的金屬矽氧化物係擇自於下列所組成之族群：氧化矽鋁（AlSiOx ）、氧化矽鉿（HfSiOx ）、氧化矽鈦（TiSiOx ）、氧化矽錳（MnSiOx ）及氧化矽釩（VSiOx ）。在一些實施例中，使用蝕刻溶液進行蝕刻停止層的選擇性蝕刻，且其中所述蝕刻溶液包含氫氧化銨、羥胺或兩者。在一些實施例中，所述蝕刻溶液更包含水、螯合劑、金屬腐蝕抑制劑以及擇自於下列所組成之族群的溶劑：二乙二醇單甲基醚（diethylene glycol monomethyl ether）、乙二醇（ethylene glycol）、丁基二乙二醇（butyl diethylene glycol）和二甲亞碸（dimethyl sulfoxide）。在一些實施例中，所述蝕刻停止層的選擇性蝕刻被配置為使得蝕刻停止層的第一部分的蝕刻速率顯著地大於蝕刻停止層的第二部分的蝕刻速率。
在一些實施例中，所述層間介電質為第一層間介電質且蝕刻停止層為第一蝕刻停止層。所述方法更包含：形成一第二蝕刻停止層於所述第一蝕刻停止層的第二部分之上和所述第一導電元件之上；形成一第二層間介電質於所述第二蝕刻停止層之上；以及蝕刻出開口於所述第二層間介電質中和所述第二蝕刻停止層中。所述開口至少部分地與導電元件對齊。所述第一蝕刻停止層的第二部分保護位於其下方的第一層間介電質的一部分免於被蝕刻。所述方法更包含以導電材料填充該開口以形成與該導電元件接觸的導電孔。在一些實施例中，所述方法在形成所述第二層間介電質之後和在所述第二層間介電質中蝕刻出開口之前更包含：形成一蓋層於所述第二層間介電質之上；以及形成一硬罩幕層於所述蓋層之上。所述開口至少從頂部至底部穿透所述硬罩幕層、所述蓋層、所述第二層間介電質和所述第二蝕刻停止層。
本發明實施例的另一個面向包含一種半導體裝置，包含：一基板；第一和第二導電元件，設置於所述基板上；一層間介電質，設置於所述基板上和所述第一和第二導電元件之間；以及一蝕刻停止層，包含一金屬矽氧化物，延伸於所述層間介電質之上且與所述層間介電質接觸。所述蝕刻停止層未延伸於第一導電元件或第二導電元件之上。所述半導體裝置更包含導電孔設置於所述第一導電元件之上且與第一導電元件電性接觸。所述導電孔至少被所述層間介電質和蝕刻停止層的一部分與第二導電元件隔開。在一些實施例中，所述半導體裝置更包含第二蝕刻停止層，設置於所述第一蝕刻停止層之上且鄰近所述導電孔；以及第二層間介電質，設置於所述第二蝕刻停止層且圍繞所述導電孔。在一些實施例中，導電孔部分地覆蓋所述第一導電元件的上表面，且第二蝕刻停止層也部分地覆蓋所述第一導電元件的上表面。在一些實施例中，所述蝕刻停止層中的金屬矽氧化物係擇自於下列所組成之族群：氧化矽鋁（AlSiOx）、氧化矽鉿（HfSiOx）、氧化矽鈦（TiSiOx）、氧化矽錳（MnSiOx）及氧化矽釩（VSiOx）。在一些實施例中，所述層間介電質包含矽。在一些實施例中，所述蝕刻停止層具有介於10至60 Å的厚度。
本發明實施例的另一個面向包含一種半導體裝置的製造方法，包含：形成第一蝕刻停止層，包含與導電元件接觸的第一部分且包含與圍繞所述導電元件的第一層間介電質接觸的第二部分。所述第一蝕刻停止層的第一部分包含金屬氧化物，且所述第一蝕刻停止層的第二部分包含金屬矽氧化物。所述方法更包含蝕刻所述第一蝕刻停止層以移除第一蝕刻停止層的第一部分，但不移除第一蝕刻停止層的第二部分；形成一第二蝕刻停止層於所述第一蝕刻停止層的第二部分之上和導電元件之上；形成一第二層間介電質於所述第二蝕刻停止層之上；蝕刻出開口，其垂直地穿過所述第二層間介電質和第二蝕刻停止層以露出所述導電元件的上表面；以及以導電材料填充所述開口以形成一導電孔於開口中。所述導電孔與所述導電元件的上表面接觸但被第一蝕刻停止層的第二部分與第一層間介電質隔開。
在一些實施例中，形成所述第一蝕刻停止層包含：沉積所述第一蝕刻停止層，所述第一和第二部分中包含金屬氧化物但所述第一和第二部分中不包含任何金屬矽氧化物；以及在介於100°C至400°C的溫度下烘烤所述第一蝕刻停止層，使得所述第一蝕刻停止層的第二部分中的金屬矽氧化物藉由所述第一層間介電質中的矽與所述第一蝕刻停止層的第二部分中的金屬氧化物間的化學反應而形成。在一些實施例中，所述開口部分地與導電元件對齊，且所述第一蝕刻停止層的第二部分保護位於其下方的第一層間介電質在開口的蝕刻期間免於被蝕刻。在一些實施例中，蝕刻所述第一蝕刻停止層包含使用包含鹼性胺的濕蝕刻溶液，且蝕刻所述開口包含使用乾蝕刻製程。
以上概述數個實施例之部件，使得在本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的面向。在本發明所屬技術領域中具有通常知識者應該理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。本發明所屬技術領域中具有通常知識者也應該理解到，此類等效的結構並未悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍下，做各式各樣的改變、取代和替換。
100‧‧‧半導體裝置102‧‧‧基板110、194‧‧‧內連線層120、122‧‧‧導電元件130、170‧‧‧層間介電質140、160‧‧‧蝕刻停止層142、144‧‧‧部分150‧‧‧蝕刻溶液172‧‧‧蓋層174‧‧‧硬罩幕層180‧‧‧開口190‧‧‧導電材料192‧‧‧導電孔200‧‧‧方法210、220、230、240、250、252、254、256、258、260‧‧‧步驟
藉由以下的詳細描述配合所附圖式，可以更加理解本發明實施例的內容。需強調的是，根據產業上的標準慣例，許多部件（feature）並未按照比例繪製。事實上，為了能清楚地討論，各種部件的尺寸可能被任意地增加或減少。 第1A、1B、1C、1D、1E、1F、1G、1H和1I圖係根據本發明實施例之各製造階段的半導體裝置的剖面示意圖。 第2圖係根據本發明實施例之半導體裝置的製造方法之流程圖。
100‧‧‧半導體裝置
102‧‧‧基板
110、194‧‧‧內連線層
120、122‧‧‧導電元件
130、170‧‧‧層間介電質
142‧‧‧部分
160‧‧‧蝕刻停止層
192‧‧‧導電孔

Claims (1)

  1. 一種半導體裝置的製造方法，該方法包括： 提供包括一導電元件和一層間介電質的一結構，其中該層間介電質包括矽且圍繞該導電元件； 形成一蝕刻停止層於該導電元件和該層間介電質之上，其中該蝕刻停止層包括金屬氧化物，其中該蝕刻停止層包括與該導電元件接觸的一第一部分和與該層間介電質接觸的一第二部分； 烘烤該蝕刻停止層以將位於該蝕刻停止層的該第二部分中的該金屬氧化物轉換為金屬矽氧化物；以及 選擇性蝕刻該蝕刻停止層以移除該蝕刻停止層的該第一部分，但不移除該蝕刻停止層的該第二部分。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI767663B (zh) * 2020-04-28 2022-06-11 台灣積體電路製造股份有限公司 半導體結構及其形成的方法
TWI774280B (zh) * 2020-04-21 2022-08-11 台灣積體電路製造股份有限公司 連接結構及其形成方法
US11521929B2 (en) 2020-04-28 2022-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Capping layer for liner-free conductive structures
US11972979B2 (en) 2019-06-10 2024-04-30 Intel Corporation 1D vertical edge blocking (VEB) via and plug
US12009305B2 (en) 2023-04-18 2024-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for forming the same

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10867805B2 (en) 2018-06-29 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Selective removal of an etching stop layer for improving overlay shift tolerance
KR102580659B1 (ko) * 2018-10-01 2023-09-20 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11227792B2 (en) * 2019-09-19 2022-01-18 International Business Machines Corporation Interconnect structures including self aligned vias
US11276571B2 (en) * 2019-12-26 2022-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Method of breaking through etch stop layer
US11715687B2 (en) 2020-05-28 2023-08-01 Taiwan Semiconductor Manufacturing Company Limited Contact structures for reducing electrical shorts and methods of forming the same
TWI795770B (zh) * 2020-05-28 2023-03-11 台灣積體電路製造股份有限公司 用以減低電氣短路之接觸結構及其形成方法
CN113764332A (zh) * 2020-06-07 2021-12-07 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11955382B2 (en) * 2020-12-03 2024-04-09 Applied Materials, Inc. Reverse selective etch stop layer
US11978668B2 (en) 2021-09-09 2024-05-07 Samsung Electronics Co., Ltd. Integrated circuit devices including a via and methods of forming the same
WO2023048019A1 (ja) * 2021-09-22 2023-03-30 東京エレクトロン株式会社 半導体装置の製造方法
US20240030132A1 (en) * 2022-07-21 2024-01-25 Nanya Technology Corporation Semiconductor device with porous dielectric layers and method for fabricating the same

Family Cites Families (118)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6788477B2 (en) 2002-10-22 2004-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Apparatus for method for immersion lithography
KR100655774B1 (ko) * 2004-10-14 2006-12-11 삼성전자주식회사 식각 저지 구조물, 이의 제조 방법, 이를 포함하는 반도체장치 및 그 제조 방법
US7394155B2 (en) 2004-11-04 2008-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Top and sidewall bridged interconnect structure and method
US7927779B2 (en) 2005-06-30 2011-04-19 Taiwan Semiconductor Manufacturing Companym, Ltd. Water mark defect prevention for immersion lithography
US8383322B2 (en) 2005-08-05 2013-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion lithography watermark reduction
US7993808B2 (en) 2005-09-30 2011-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. TARC material for immersion watermark reduction
US20070257323A1 (en) * 2006-05-05 2007-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked contact structure and method of fabricating the same
US8564759B2 (en) 2006-06-29 2013-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for immersion lithography
US8518628B2 (en) 2006-09-22 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Surface switchable photoresist
US8253922B2 (en) 2006-11-03 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion lithography system using a sealed wafer bath
US8208116B2 (en) 2006-11-03 2012-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion lithography system using a sealed wafer bath
US8068208B2 (en) 2006-12-01 2011-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for improving immersion scanner overlay performance
US8580117B2 (en) 2007-03-20 2013-11-12 Taiwan Semiconductor Manufactuing Company, Ltd. System and method for replacing resist filter to reduce resist filter-induced wafer defects
US8264662B2 (en) 2007-06-18 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. In-line particle detection for immersion lithography
US8003281B2 (en) 2008-08-22 2011-08-23 Taiwan Semiconductor Manufacturing Company, Ltd Hybrid multi-layer mask
US7862962B2 (en) 2009-01-20 2011-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit layout design
US8216767B2 (en) 2009-09-08 2012-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning process and chemical amplified photoresist with a photodegradable base
US8841058B2 (en) 2010-08-03 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Photolithography material for immersion lithography processes
US8764995B2 (en) 2010-08-17 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Extreme ultraviolet light (EUV) photomasks, and fabrication methods thereof
US8323870B2 (en) 2010-11-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method and photoresist with zipper mechanism
FR2969375A1 (fr) * 2010-12-17 2012-06-22 St Microelectronics Crolles 2 Structure d'interconnexion pour circuit intégré
US9632426B2 (en) 2011-01-18 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ immersion hood cleaning
US8464186B2 (en) 2011-01-21 2013-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Providing electron beam proximity effect correction by simulating write operations of polygonal shapes
US8507159B2 (en) 2011-03-16 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Electron beam data storage system and method for high volume manufacturing
US8524427B2 (en) 2011-04-14 2013-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Electron beam lithography system and method for improving throughput
US8621406B2 (en) 2011-04-29 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US9201022B2 (en) 2011-06-02 2015-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Extraction of systematic defects
US8647796B2 (en) 2011-07-27 2014-02-11 Taiwan Semiconductor Manufacturing Company, Ltd. Photoactive compound gradient photoresist
US8601407B2 (en) 2011-08-25 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Geometric pattern data quality verification for maskless lithography
US8473877B2 (en) 2011-09-06 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Striping methodology for maskless lithography
US8664679B2 (en) 2011-09-29 2014-03-04 Toshiba Techno Center Inc. Light emitting devices having light coupling layers with recessed electrodes
US8736084B2 (en) 2011-12-08 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for E-beam in-chip overlay mark
US8691476B2 (en) 2011-12-16 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. EUV mask and method for forming the same
US9960110B2 (en) * 2011-12-30 2018-05-01 Intel Corporation Self-enclosed asymmetric interconnect structures
US8732626B2 (en) 2012-01-05 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. System and method of circuit layout for multiple cells
US8715890B2 (en) 2012-01-31 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor mask blanks with a compatible stop layer
US9097978B2 (en) 2012-02-03 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus to characterize photolithography lens quality
US8530121B2 (en) 2012-02-08 2013-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-grid exposure method
US8709682B2 (en) 2012-02-08 2014-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. Mask and method for forming the mask
US8822106B2 (en) 2012-04-13 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Grid refinement method
US8589828B2 (en) 2012-02-17 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Reduce mask overlay error by removing film deposited on blank of mask
US8584057B2 (en) 2012-03-01 2013-11-12 Taiwan Semiconductor Manufacturing Copmany, Ltd. Non-directional dithering methods
US8572520B2 (en) 2012-03-01 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Optical proximity correction for mask repair
US8510687B1 (en) 2012-03-01 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Error diffusion and grid shift in lithography
US8589830B2 (en) 2012-03-07 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for enhanced optical proximity correction
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8527916B1 (en) 2012-03-14 2013-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Dissection splitting with optical proximity correction to reduce corner rounding
US8837810B2 (en) 2012-03-27 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for alignment in semiconductor device fabrication
US8841047B2 (en) 2012-04-02 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Extreme ultraviolet lithography process and mask
US8628897B1 (en) 2012-07-05 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Extreme ultraviolet lithography process and mask
US9091930B2 (en) 2012-04-02 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced EUV lithography system
US8741551B2 (en) 2012-04-09 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and composition of a dual sensitive resist
US9367655B2 (en) 2012-04-10 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Topography-aware lithography pattern check
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US8627241B2 (en) 2012-04-16 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Pattern correction with location effect
US8631360B2 (en) 2012-04-17 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methodology of optical proximity correction optimization
US8877409B2 (en) 2012-04-20 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Reflective mask and method of making same
US8677511B2 (en) 2012-05-02 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus for charged particle lithography system
US8728332B2 (en) 2012-05-07 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of patterning small via pitch dimensions
US8631361B2 (en) 2012-05-29 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit design method with dynamic target point
US8722286B2 (en) 2012-05-31 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Devices and methods for improved reflective electron beam lithography
US8609308B1 (en) 2012-05-31 2013-12-17 Taiwan Semicondcutor Manufacturing Company, Ltd. Smart subfield method for E-beam lithography
US20130320451A1 (en) 2012-06-01 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") Semiconductor device having non-orthogonal element
US9213234B2 (en) 2012-06-01 2015-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Photosensitive material and method of lithography
US8563224B1 (en) 2012-06-04 2013-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. Data process for E-beam lithography
US8468473B1 (en) 2012-06-08 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for high volume e-beam lithography
US8762900B2 (en) 2012-06-27 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for proximity correction
US8751976B2 (en) 2012-06-27 2014-06-10 Cheng-Lung Tsai Pattern recognition for integrated circuit design
US9851636B2 (en) 2012-07-05 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Materials and methods for improved photoresist performance
US8745550B2 (en) 2012-07-09 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fracture aware OPC
US20140017615A1 (en) 2012-07-11 2014-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for resist coating and developing
US9256133B2 (en) 2012-07-13 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for developing process
US8835082B2 (en) 2012-07-31 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method and system for E-beam lithography with multi-exposure
US8679707B2 (en) 2012-08-01 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a lithography mask
US8765330B2 (en) 2012-08-01 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Phase shift mask for extreme ultraviolet lithography and method of fabricating same
US8850366B2 (en) 2012-08-01 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making a mask by forming a phase bar in an integrated circuit design layout
US8828625B2 (en) 2012-08-06 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Extreme ultraviolet lithography mask and multilayer deposition method for fabricating same
US9028915B2 (en) 2012-09-04 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a photoresist layer
US8765582B2 (en) 2012-09-04 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method for extreme ultraviolet electrostatic chuck with reduced clamp effect
US8785084B2 (en) 2012-09-04 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method for mask fabrication and repair
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8954899B2 (en) 2012-10-04 2015-02-10 Taiwan Semiconductor Manufacturing Company, Ltd. Contour alignment system
US8739080B1 (en) 2012-10-04 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Mask error enhancement factor (MEEF) aware mask rule check (MRC)
US9158209B2 (en) 2012-10-19 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of overlay prediction
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US20140123084A1 (en) 2012-11-01 2014-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for Improving a Lithography Simulation Model
US20140119638A1 (en) 2012-11-01 2014-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. System, method and computer program product to evaluate a semiconductor wafer fabrication process
US8906595B2 (en) 2012-11-01 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for improving resist pattern peeling
US9128384B2 (en) 2012-11-09 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a pattern
US9012132B2 (en) 2013-01-02 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Coating material and method for photolithography
US8753788B1 (en) 2013-01-02 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus of repairing a mask and a method for the same
US8812999B2 (en) 2013-01-02 2014-08-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method and system of mask data preparation for curvilinear mask patterns for a device
US8987142B2 (en) 2013-01-09 2015-03-24 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-patterning method and device formed by the method
US8799834B1 (en) 2013-01-30 2014-08-05 Taiwan Semiconductor Manufacturing Company Limited Self-aligned multiple patterning layout design
US20140226893A1 (en) 2013-02-11 2014-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method and System for Image-Based Defect Alignment
US8936903B2 (en) 2013-03-09 2015-01-20 Taiwan Semiconductor Manufacturing Company, Ltd. Photo-resist with floating acid
US10274839B2 (en) 2013-03-11 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Two-dimensional marks
US9690212B2 (en) 2013-03-11 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid focus-exposure matrix
US8932799B2 (en) 2013-03-12 2015-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Photoresist system and method
US9223220B2 (en) 2013-03-12 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photo resist baking in lithography process
US8716841B1 (en) 2013-03-14 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Photolithography mask and process
US9054159B2 (en) 2013-03-14 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of patterning a feature of a semiconductor device
US9146469B2 (en) 2013-03-14 2015-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Middle layer composition for trilayer patterning stack
US8984450B2 (en) 2013-03-14 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for extracting systematic defects
US9501601B2 (en) 2013-03-14 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Layout optimization of a main pattern and a cut pattern
US9153478B2 (en) 2013-03-15 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer etching process for integrated circuit design
US9406589B2 (en) * 2014-03-14 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Via corner engineering in trench-first dual damascene process
US9529268B2 (en) 2014-04-03 2016-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods for improving pattern transfer
US9256123B2 (en) 2014-04-23 2016-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making an extreme ultraviolet pellicle
US9184054B1 (en) 2014-04-25 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
CN105489549B (zh) * 2014-10-13 2018-11-16 中芯国际集成电路制造(上海)有限公司 一种铜互连结构及其制造方法、电子装置
TWI690780B (zh) * 2014-12-30 2020-04-11 美商富士軟片電子材料美國股份有限公司 用於自半導體基板去除光阻之剝離組成物
US9496169B2 (en) * 2015-02-12 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming an interconnect structure having an air gap and structure thereof
US9818690B2 (en) * 2015-10-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned interconnection structure and method
WO2018004697A1 (en) * 2016-07-01 2018-01-04 Intel Corporation Dual layer metal oxide rram devices and methods of fabrication
TW202011547A (zh) * 2018-05-16 2020-03-16 美商微材料有限責任公司 用於產生完全自對準的通孔的方法
US10867805B2 (en) 2018-06-29 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Selective removal of an etching stop layer for improving overlay shift tolerance

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11972979B2 (en) 2019-06-10 2024-04-30 Intel Corporation 1D vertical edge blocking (VEB) via and plug
TWI774280B (zh) * 2020-04-21 2022-08-11 台灣積體電路製造股份有限公司 連接結構及其形成方法
US11791204B2 (en) 2020-04-21 2023-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with connecting structure having a doped layer and method for forming the same
TWI767663B (zh) * 2020-04-28 2022-06-11 台灣積體電路製造股份有限公司 半導體結構及其形成的方法
US11521929B2 (en) 2020-04-28 2022-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Capping layer for liner-free conductive structures
US12009305B2 (en) 2023-04-18 2024-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for forming the same

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