TW201921518A - 半導體裝置之製造方法及半導體裝置 - Google Patents

半導體裝置之製造方法及半導體裝置

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Publication number
TW201921518A
TW201921518A TW107121406A TW107121406A TW201921518A TW 201921518 A TW201921518 A TW 201921518A TW 107121406 A TW107121406 A TW 107121406A TW 107121406 A TW107121406 A TW 107121406A TW 201921518 A TW201921518 A TW 201921518A
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
mounting portion
wafer
silver paste
semiconductor device
Prior art date
Application number
TW107121406A
Other languages
English (en)
Inventor
杉浦正俊
岡浩偉
Original Assignee
日商瑞薩電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商瑞薩電子股份有限公司 filed Critical 日商瑞薩電子股份有限公司
Publication of TW201921518A publication Critical patent/TW201921518A/zh

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Abstract

本發明提供一種半導體裝置之製造方法及半導體裝置，其目的在於改善半導體裝置的可靠度。半導體裝置之組裝的晶粒接合步驟，分別包含如下步驟：在晶片搭載部1c之頂面1ca的複數第1區域的各個1caa塗布燒結銀膠6b；使燒結銀膠6b乾燥；以及在位於複數第1區域的各個1caa之間的第2區域1cab，塗布銀膠7。進一步包含如下步驟：以使半導體晶片2的背面與晶片搭載部1c的頂面1ca，隔著燒結銀膠6b及銀膠7而互相面對之方式，將半導體晶片2搭載於晶片搭載部1c；於晶片搭載後，半導體晶片2之主面2a的第1角部、第2角部、第3角部及第4角部各自之一部分，位於複數第1區域的各個1caa。

Description

半導體裝置之製造方法及半導體裝置
本發明，例如係關於一種功率系半導體裝置及其製造方法。
在需要對應高散熱之功率系半導體裝置中，考慮環境對策的觀點(無鉛)，作為在將半導體晶片搭載於晶粒墊(晶片搭載部)時使用之黏晶材的一例，已知使用銀膠或燒結銀膠(用於形成燒結銀的膠)。
作為黏晶材，於日本特開2014-29897號公報(專利文獻1)，揭露一種使用燒結接合材之半導體裝置的構造。 [先前技術文獻] [專利文獻]
[專利文獻1]日本特開2014-29897號公報
[本發明所欲解決的問題]
上述功率系半導體裝置中，在使用銀膠作為黏晶材的情況，在製品完成後之溫度循環測試等因半導體晶片與晶粒墊的線膨脹係數差而產生熱應力，此熱應力集中於半導體晶片的角部正下方之銀膠。
此一結果，從本案發明人之研討，得知在半導體晶片的角部正下方中之銀膠的與半導體晶片之接合部附近，發生破壞(裂縫、剝離)。因而，作為半導體晶片的角部之黏晶材的破壞對策，本案發明人研討將燒結銀膠使用在黏晶材的情況。依此一研討，則由於在熱應力所集中之半導體晶片的角部配置高強度之燒結銀，故可抑制因銀膠而成為問題之黏晶材的破壞。
另一方面，作為需要對應高散熱之半導體裝置的構造，已知一種晶粒墊露出型之半導體裝置，而為了進一步改善散熱性，亦有將晶粒墊的厚度減薄之半導體裝置。
然而，從本案發明人之研討，得知在使用燒結銀膠作為將晶粒墊的厚度減薄之半導體裝置的黏晶材之情況，晶粒墊因膠體固化時的收縮而變形，對半導體裝置(製品)之翹曲量造成影響。
其他問題與新特徵，應可自本說明書之記述內容及附圖明瞭。 [解決問題之技術手段]
一實施形態的半導體裝置之製造方法，包含如下步驟：(a)準備具備第1表面與第1背面之半導體晶片；(b)準備具有晶片搭載部的導線框架，該晶片搭載部具備第2表面與第2背面；(c)在該晶片搭載部的該第2表面之複數第1區域的各個塗布燒結銀膠；以及(d)使該燒結銀膠乾燥。進一步，包含如下步驟：(e)將銀膠塗布在位於該複數第1區域的各個之間的第2區域；以及(f)以使該半導體晶片的該第1背面與該晶片搭載部的該第2表面，隔著該燒結銀膠與該銀膠而互相面對之方式，將該半導體晶片搭載於該晶片搭載部。進一步，包含如下步驟：(g)對該半導體晶片加熱與加壓，將該半導體晶片的該第1背面，與該燒結銀膠及該銀膠連接。此處，俯視時，該半導體晶片具備：往第1方向延伸的第1邊及第2邊、往與該第1方向交叉之第2方向延伸的第3邊及第4邊。此外，俯視時，該半導體晶片具備：該第1邊與該第3邊交會的第1角部，該第3邊與該第2邊交會的第2角部，該第2邊與該第4邊交會的第3角部、及該第4邊與該第1邊交會的第4角部。進一步，於該(f)步驟後，俯視時，該第1角部、該第2角部、該第3角部及該第4角部各自之一部分，位於該複數第1區域的各個。
此外，一實施形態的另一半導體裝置之製造方法，包含如下步驟：(a)準備具備第1表面與第1背面之半導體晶片；(b)準備具有具備第2表面與第2背面之晶片搭載部的導線框架；以及(c)於該晶片搭載部的該第2表面塗布燒結銀膠或銀膠之一者。進一步包含如下步驟：(d)於該晶片搭載部的該第2表面塗布燒結銀膠或銀膠之另一者；以及(e)以使該半導體晶片的該第1背面與該晶片搭載部的該第2表面，隔著該燒結銀膠與該銀膠而互相面對之方式，將該半導體晶片搭載於該晶片搭載部。進一步包含如下步驟：(f)對該半導體晶片加熱，將該半導體晶片的該第1背面與該燒結銀膠及該銀膠連接。此處，該燒結銀膠，塗布在該晶片搭載部之該第2表面的複數第1區域的各個，而該銀膠，塗布在位於該複數第1區域的各個之間的第2區域。此外，俯視時，該半導體晶片具備往第1方向延伸的第1邊及第2邊、往與該第1方向交叉之第2方向延伸的第3邊及第4邊。此外，俯視時，該半導體晶片具備：該第1邊與該第3邊交會的第1角部、該第3邊與該第2邊交會的第2角部、該第2邊與該第4邊交會的第3角部、及該第4邊與該第1邊交會的第4角部。進一步，於該(e)步驟後，俯視時，該第1角部、該第2角部、該第3角部及該第4角部各自之一部分，位於該複數第1區域的各個。
此外，一實施形態的半導體裝置，包含：具備第1表面與第1背面之半導體晶片、搭載該半導體晶片之晶片搭載部、經由第1導電性構件而與該半導體晶片電性連接之第1導線、及經由第2導電性構件而與該半導體晶片電性連接之第2導線。進一步，包含密封體，該密封體將該半導體晶片、該第1導電性構件、該第2導電性構件、該晶片搭載部之一部分、該第1導線之一部分、該第2導線之一部分密封；該半導體晶片的該第1背面，隔著第1接合材與第2接合材而與該晶片搭載部的該第2表面互相面對。俯視時，該晶片搭載部的該第2表面，具備該第1接合材所在處的複數第1區域，以及位於該複數第1區域的各個之間、該第2接合材所在處的第2區域。此外，俯視時，該半導體晶片具備：第1邊，往第1方向延伸；第2邊，位於該第1邊之相反側，往該第1方向延伸；第3邊，往與該第1方向交叉之第2方向延伸；及第4邊，位於該第3邊之相反側，往該第2方向延伸。此外，俯視時，該半導體晶片進一步具備：該第1邊與該第3邊交會的第1角部、該第3邊與該第2邊交會的第2角部、該第2邊與該第4邊交會的第3角部、及該第4邊與該第1邊交會的第4角部。進一步，俯視時，該第1、第2、第3及第4角部各自之一部分，位於該複數第1區域的各個。 [本發明之效果]
依上述一實施形態，則可改善半導體裝置的可靠度。
以下實施形態，除了特別必要時以外，原則上對於同一或同樣部分的說明不予重複。
進一步，以下實施形態中，雖為了方便在必要時分割為複數個部分或實施形態而予以說明，但除了特別指出之情況以外，其等並非彼此全無關聯，而係具有一方為另一方之部分或全部的變形例、細節、補充說明等關係。
此外，以下實施形態中，在提及要素的數目等(包含個數、數值、量、範圍等)之情況，除了特別指出之情況及原理上明顯限定為特定數目之情況等以外，並未限定於該特定數目，可使其為特定數目以上亦可為以下。
此外，以下實施形態中，其構成要素(亦包含要素步驟等)，除了特別指出之情況及原理上明顯被視為必須之情況等以外，自然可說是並非為必要。
此外，以下實施形態中，關於構成要素等，在記載「具備A」、「包含A」時，除了特別指出僅為該要素之情況等，自然並未排除其以外的要素。同樣地，以下實施形態中，在提及構成要素等之形狀、位置關係等時，除了特別指出之情況及原理上明顯被視為並非如此之情況等以外，包含實質上與該形狀等近似或類似者等。此一條件，對於上述數值及範圍亦相同。
以下，依據附圖詳細地說明本發明之實施形態。另，在用於說明實施形態的全部附圖中，對於具有相同功能的構件給予相同符號，並省略其重複的說明。此外，有即便為俯視圖，仍為了容易了解附圖而繪上影線之情況。
(實施形態) ＜半導體裝置的構造＞ 圖1為透視內部而顯示實施形態之半導體裝置的構造之一例的俯視圖，圖2為顯示沿著圖1之A-A線切斷的構造之一例的剖面圖，圖3為將圖2的B部之構造放大顯示的部分放大剖面圖。
圖1及圖2所示的本實施形態之半導體裝置為半導體封裝，其具備將半導體晶片(亦稱作Pellet)2密封，且由絕緣性樹脂構成的密封體3，進一步具備位於密封體3之內部與外部的複數導線部1。另，複數導線部1，各自具備以密封體3覆蓋之內引腳部1a、及從密封體3往外部露出(突出)之外引腳部1b，複數條(此處為3條)外引腳部1b，各自為半導體裝置之外部連接用端子部(外部端子部)。
而本實施形態之半導體裝置，如圖1所示，複數外引腳部1b從密封體3之期望的1個側面3c突出。進一步，如圖2所示，從密封體3的底面(第4背面)3b，露出將半導體晶片2支持在頂面(第2表面、晶片搭載面)1ca的板狀之晶片搭載部(亦稱作島部(island)、晶粒墊、頭座(header)或突片)1c的底面(第2背面)1cb。亦即，本實施形態之半導體裝置，為表面安裝型之半導體裝置，且亦為需要對應高散熱之半導體裝置。
亦即，晶片搭載部1c的底面1cb從密封體3的底面3b露出，故可將從半導體晶片2發出的熱經由晶片搭載部1c而往外部散出，係對應高散熱之稱作To-封裝0(Tr ansistor Outline Package，電晶體外形封裝)等的功率系之半導體裝置。
此外，本實施形態之半導體裝置中，複數外引腳部1b，各自從密封體3露出而筆直地延伸。本實施形態中，作為具備上述構造之半導體裝置的一例，列舉功率裝置5而予以說明。例如，於半導體晶片2，形成具備溝槽式閘極型構造之縱型功率MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金氧半場效電晶體)以作為作為功率電晶體。功率MOSFET之裝置構造，係在表面形成溝並在其中嵌入閘極，如同圖2所記載，具備以在半導體晶片2的主面(第1表面)2a露出的方式形成之源極(S)電極及閘極(G)電極，進一步具備形成在背面(第1背面)2b之汲極(D)電極；對背面2b，施加大電流。另，雖圖中並未記載，但作為組裝於半導體裝置內之元件，功率電晶體亦可為功率雙極性電晶體(Bipolar Transistor)或IGBT(Insulated Gate Bipolar Transistor，絕緣閘極雙極性電晶體)。
若利用圖1~圖3對功率裝置5之詳細構造予以說明，則其具有：晶片搭載部1c，具備頂面1ca、及與頂面1ca位於相反側的底面1cb；以及半導體晶片2，經由接合材(黏晶材)而搭載於晶片搭載部1c的頂面1ca。此半導體晶片2，具備：主面2a；以及源極用電極墊(接合電極、接合墊、第1電極)2c與閘極用電極墊(接合電極、接合墊、第2電極)2d，以在主面2a露出的方式形成。進一步，半導體晶片2，具備與主面2a位於相反側的背面2b，此背面2b以與晶片搭載部1c的頂面1ca相對向之方式搭載於晶片搭載部1c上。
另，半導體晶片2的背面2b成為電極，在本實施形態之功率裝置5，為汲極(D)用電極2e。亦即，半導體晶片2，具備露出源極用電極墊2c及閘極用電極墊2d的主面2a、及形成有汲極用電極2e的背面2b。因此，半導體晶片2的背面2b(汲極用電極2e、第3電極)與晶片搭載部1c，必須藉由導電性的接合材電性連接並機械性連接。
本實施形態之功率裝置5中，作為導電性的接合材，使用燒結銀6與銀膠7。亦即，藉由燒結銀6及銀膠7，將半導體晶片2的背面2b(汲極用電極2e)與晶片搭載部1c的頂面1ca固接(機械性連接)，並電性連接。
此處，於半導體晶片2的背面2b，形成汲極用電極(背面電極)2e，故來自半導體晶片2之發熱量亦多。因此，作為接合材(黏晶材)，藉由使用燒結銀6與銀膠7，而使半導體晶片2的背面2b側成為散熱路徑。亦即，從半導體晶片2的背面2b側，經由燒結銀6及銀膠7而往晶片搭載部1c進行傳熱，進一步，成為在密封體3的底面3b露出晶片搭載部1c的底面1cb之構造。
此外，在圖1所示的俯視圖中，將沿著晶片搭載部1c的一邊配置之複數條(此處為2條)導線部1的內引腳部1a，與半導體晶片2之主面2a的2個電極墊，各自藉由導電性的引線電性連接。此外，於內引腳部1a各自之半導體晶片2側的端部，形成導線寬變寬之寬幅部1aa，將此寬幅部1aa與Al引線4連接。
此外，本實施形態的功率裝置5中之在半導體晶片2的主面2a露出之複數電極墊，為源極用電極墊2c、及俯視之大小較源極用電極墊2c更小的閘極用電極墊2d。
此外，圖1及圖2所示之密封體3，具備各導線部1突出的側面3c，3條外引腳部1b從此側面3c突出。進一步，密封體3，具備頂面(第3表面)3a、及位於其相反側的底面(第4背面)3b，以使晶片搭載部1c的底面1cb在密封體3的底面3b露出之方式，將晶片搭載部1c的一部分(頂面1ca側)，且將半導體晶片2及複數條Al引線4(Al引線4a、Al引線4b)密封。
本實施形態之半導體裝置為功率裝置5，故如圖1所示，從密封體3的側面3c突出之3條導線部1中的2條外引腳部1b，為源極導線(S)1d與閘極導線(G)1e。此外，如圖2所示，半導體晶片2的背面2b，如同上述地成為汲極(D)用電極(背面電極)2e，因此，在密封體3的底面3b露出之晶片搭載部1c的底面1cb，為汲極(D)用電極。此外，從側面3c突出之剩下的1條外引腳部1b，為與晶片搭載部1c連結的汲極導線。
另，經由Al引線4而與半導體晶片2的主面2a之2個電極墊分別電性連接之外引腳部1b，各自與內引腳部1a一體化地形成。亦即，如圖1所示，外引腳部1b之源極導線1d，與內引腳部1a之源極導線1d一體地連結，此外，外引腳部1b之閘極導線1e，與內引腳部1a之閘極導線1e一體地連結。因此，源極導線(第1導線)1d的內引腳部(一部分)1a及閘極導線(第2導線)1e的內引腳部(一部分)1a，分別嵌入至密封體3內。
此外，將源極導線1d的寬幅部1aa，與直徑(線徑)大的Al引線(第1導電性構件) 4a電性連接，進一步，將此Al引線4a，與半導體晶片2之連接用電極(接合電極)中的源極用電極墊(第1電極)2c電性連接。
亦即，對複數導線部1中之源極導線(第1導線)1d施加大電流，故經由直徑(線徑)大的Al引線4a，將源極導線1d，與半導體晶片2之源極用電極墊2c電性連接。
另一方面，將內引腳部1a之閘極導線(第2導線)1e的寬幅部1aa，與直徑(線徑)較Al引線4a更小的Al引線(第2導電性構件)4b電性連接，進一步，將此Al引線4b，與半導體晶片2之連接用電極(接合電極)中的閘極用電極墊(第2電極)2d電性連接。
亦即，對複數導線部1中之閘極導線1e施加小電流，故經由細的Al引線4b，將閘極導線1e，與半導體晶片2之閘極用電極墊2d電性連接。
此外，如圖1所示，使與晶片搭載部1c連結的懸吊導線1f即外引腳部1b，於密封體3的側面3c突出。
另，晶片搭載部1c、與此晶片搭載部1c連結的懸吊導線1f、及包含內引腳部1a與外引腳部1b之複數導線部1，例如係由以Cu(銅)為主成分之Cu合金構成。此外，引線，例如係由Al(鋁)等構成。此外，密封體3，例如係由熱硬化性的環氧樹脂構成。然則，上述尺寸與各構件之材料，並未限定於上述形態。
此外，本實施形態之功率裝置5中，如圖2所示，作為半導體晶片2的接合材，使用燒結銀(第1接合材)6與銀膠(第2接合材)7。具體而言，半導體晶片2的背面2b， 隔著燒結銀6及銀膠7，而與晶片搭載部1c的頂面1ca互相面對。其中，燒結銀6，在剖面視圖中，配置於包含半導體晶片2之各4個角部的區域，即第1區域1caa(參考後述圖21)。亦即，晶片搭載部1c的頂面1ca，具備複數第1區域1caa，燒結銀6分別位於複數第1區域的各個1caa。另一方面，銀膠7，配置於第1區域1caa與第1區域1caa之間的區域，即第2區域1cab(參考後述圖21)。亦即，晶片搭載部1c的頂面1ca，具備位於複數第1區域的各個1caa之間的第2區域1cab，且銀膠7位於該第2區域1cab。亦即，燒結銀6，俯視時，分別配置於半導體晶片2之各4個角部附近；銀膠7，配置於半導體晶片2之中央附近。
此外，如圖3所示，將燒結銀6之粒子6a鍛燒硬化，故相較於銀膠7之粒子7a，粒徑更小。例如，燒結銀6之粒子6a為nm級，銀膠7之粒子7a為μm級。然則，燒結銀6之中，從半導體晶片2擠出的區域之燒結銀6，其粒子6a的大小，相較於配置於晶片下之粒子6a，粒徑增大未受半導體晶片2加壓的分。
＜本案發明人所研討之構造＞ 圖4為顯示本案發明人所研討的半導體裝置之構造的第1問題圖，圖5為顯示本案發明人所研討的半導體裝置之構造的第2問題圖。
利用圖4，對本案發明人所研討之半導體裝置予以說明。
圖4所示之半導體裝置，為需要對應高散熱之半導體裝置50。主要為使用在ECU(Engine Control Unit，引擎控制單元)周圍的車載用之半導體裝置50，於汽車的引擎直接載放用途中，售出保障運作至125℃之周圍溫度條件為止的製品。此外，現今市面上亦販售接面溫度保障至150℃為止的製品。此等半導體裝置50中， 作為固接半導體晶片2之黏晶材，雖運用銀膠7、燒結銀膠等，但在使用銀膠7的情況，於製品完成後之溫度循環測試等，因半導體晶片2與晶粒墊(晶片搭載部1c)的線膨脹係數差而產生熱應力。而從本案發明人的研討，得知由於此一熱應力，在半導體晶片2的角部正下方(圖4所示之C部)中，發生晶片-黏晶材間的破壞(裂縫、剝離)。
於半導體晶片2的角部附近引起上述破壞之機制，係因俯視時半導體晶片2的中央部附近之黏晶材，其周圍受到外周附近之黏晶材的束縛，故不易收縮。另一方面，外周附近(端部附近)之黏晶材，其外側進一步開放，故束縛少而容易收縮。進一步，在俯視時，於外周附近中，角部距離中心的距離亦最遠，因而欲使其收縮的力亦變大。因此，角部之黏晶材收縮最甚，應力集中於角部，此一結果，導致上述破壞。
相對於此，本案發明人，進一步研討將用於形成燒結銀6的膠即燒結銀膠使用在黏晶材之情況。
如圖5所示，由於在熱應力所集中之半導體晶片2的角部配置高強度之燒結銀膠6b，故可抑制上述因銀膠7而成為問題之上述破壞。
然而，晶粒墊露出型之半導體裝置中，為了進一步改善散熱性，而有將晶粒墊(晶片搭載部1c)減薄(厚度之一例值為0.4mm以下)的製品，吾人已知在使用燒結銀膠6b作為此等製品之黏晶材的情況，晶粒墊(晶片搭載部1c)因膠體固化時的收縮而變形(圖5之P部)，對製品翹曲量造成影響。
進一步，從本案發明人之研討，得知在使用燒結銀膠6b的半導體裝置50之製造方法(後述加壓處理之情況)中，若以「燒結銀膠之塗布」→「乾燥」→「搭載半導體晶片」的順序實施組裝，則在使燒結銀膠6b乾燥的乾燥步驟中，燒結銀膠6b之密接性降低，造成半導體晶片2的位置偏移。
因而，圖1及圖2所示的本實施形態之功率裝置5中，作為半導體晶片2的黏晶材，在俯視時包含半導體晶片2的角部之區域即第1區域1caa(參考圖21)使用燒結銀6，於該處以外之區域(第1區域1caa與第1區域1caa之間的第2區域1cab(參考圖21))，使用銀膠7。
藉此，在半導體裝置完成後之溫度循環測試等，即便受到因半導體晶片2與晶片搭載部1c的線膨脹係數差而產生之熱應力，仍變得不易發生半導體晶片2的角部正下方之晶片-黏晶材間之破壞(裂縫、剝離)。
藉此，可改善功率裝置(半導體裝置)5的可靠度。
另，本實施形態中，作為功率系之半導體裝置，雖列舉To-封裝予以說明，但本實施形態之半導體裝置，自然亦包含其他晶粒墊露出型之封裝(例如，內建有微電腦的晶粒墊露出型之QFP(Quad Flat Package，四面扁平封裝))等。
＜半導體裝置之製造方法＞ [1. 準備導線框架] 圖6為顯示在圖1所示之半導體裝置的組裝所使用之導線框架的要部構造之一例的部分俯視圖，圖7為顯示沿著圖6之A-A線切斷的構造之一例的剖面圖。
首先，準備如圖6及圖7所示之導線框架8。於導線框架8，形成複數個能夠形成圖1所示之1個功率裝置5的裝置區8a。於裝置區8a，形成晶片搭載部1c、及配置在晶片搭載部1c旁(附近、周圍)的複數導線部1。本實施形態之導線框架8中， 於1個裝置區8a，包含：1個晶片搭載部1c，俯視時呈略四角形；以及2條導線部1與1條懸吊導線1f，對應於略四角形之晶片搭載部1c的一邊。
另，晶片搭載部1c，具備搭載圖1所示之半導體晶片2的頂面(第2表面)1ca、及位於其相反側的圖2所示之底面(第2背面)1cb。
此外，在各導線部1與懸吊導線1f中，各自之與晶片搭載部1c側為相反側的端部，和框部8b連結，藉由框部8b支持。晶片搭載部1c，藉由和框部8b連結的懸吊導線1f而支持。
此外，於各導線部1各自之晶片搭載部1c側的端部，形成導線寬變寬之寬幅部1aa。此寬幅部1aa，為連接引線的區域。
此處，導線框架8，例如係由以銅(Cu)為主成分的基材形成，圖6所示之圖案，係藉由蝕刻加工或沖壓加工等形成。
[2. 晶粒接合] 圖8為顯示圖1所示之半導體裝置的晶粒接合步驟中之燒結銀膠的塗布方法之一例的剖面圖，圖9為顯示圖1所示之半導體裝置的晶粒接合步驟中之燒結銀膠的塗布方法之變形例的剖面圖。此外，圖10為顯示圖1所示之半導體裝置的晶粒接合步驟中之燒結銀膠塗布後的構造之一例的部分俯視圖，圖11為顯示沿著圖10之A-A線切斷的構造之一例的剖面圖。
首先，準備如圖1及圖2所示之半導體晶片2。另，半導體晶片2，具備主面(第1表面)2a、及位於其相反側的背面(第1背面)2b。於主面2a，露出源極用電極墊2c與閘極用電極墊2d，另一方面，於背面2b，形成背面電極，即汲極用電極2e。
接著，準備圖1所示之半導體晶片2及圖6所示之導線框架8後，施行晶粒接合。本實施形態中，作為將半導體晶片2固接的黏晶材，使用燒結銀(第1接合材)6與銀膠(第2接合材)7。亦即，經由配置於導線框架8之晶片搭載部1c的頂面1ca之燒結銀6、與同樣塗布於頂面1ca之銀膠7，而將半導體晶片2與晶片搭載部1c晶粒接合。
在晶粒接合步驟，如圖8所示，首先，於導線框架8之晶片搭載部1c的頂面1ca，塗布燒結銀膠(第1接合材)6b。此處處理之燒結銀膠6b為膠狀的燒結銀材料。 亦即，係用於形成燒結銀6的膠，在後述內容中，將其稱作燒結銀膠6b。此外，在塗布燒結銀膠6b之區域，具體而言，晶片搭載部1c的頂面1ca之複數第1區域的各個1caa(參考後述圖21)，塗布燒結銀膠6b。亦即，如圖10所示，在俯視時呈略四角形之晶片搭載部1c的頂面1ca之各4個角部附近，塗布燒結銀膠6b。
此時，例如，藉由網版印刷，塗布膠狀的燒結銀材料，即燒結銀膠6b。具體而言，如圖8所示地將導線框架8載置於平台9，在此一狀態下，使用金屬遮罩10，於導線框架8之晶片搭載部1c的頂面1ca上塗布燒結銀膠6b。此時，在晶片搭載部1c的頂面1ca之各個複數該第1區域1caa，塗布燒結銀膠6b。
此外，作為代替方法，亦可如圖9所示，利用沖淋式噴嘴(多點噴嘴)12，於導線框架8之晶片搭載部1c的頂面1ca上塗布燒結銀膠6b。亦即，利用安裝在注射器11之沖淋式噴嘴12，將燒結銀膠6b於晶片搭載部1c的頂面1ca多點塗布。
如此地藉由利用沖淋式噴嘴12將燒結銀膠6b多點塗布，而可對晶片搭載部1c的頂面1ca之複數第1區域1caa效率良好地塗布燒結銀膠6b，可改善將功率裝置5量產時的生產力。
然則，作為變形例，亦可利用單點噴嘴13(參考後述圖12)，於晶片搭載部1c的頂面1ca塗布燒結銀膠6b。
另，本實施形態中，燒結銀膠6b，係指硬化前之體積比若使銀為1，則樹脂成分為0.3程度，因此，硬化後，樹脂成分幾乎不存在者。
於圖10及圖11，顯示燒結銀膠6b的塗布完畢之構造。如圖10所示，其係在導線框架8之晶片搭載部1c的頂面1ca之各4個角部附近(後述第1區域1caa，在之後的步驟即晶片搭載後分別配置半導體晶片2之4個角部的區域)塗布燒結銀膠6b的構造。
在塗布燒結銀膠後，使燒結銀膠6b乾燥。
例如，以約120℃使燒結銀膠6b乾燥(烘焙)。藉此，可降低燒結銀膠6b的流動性。另，為了施行燒結銀膠6b的乾燥步驟，本實施形態之組裝，在塗布燒結銀膠6b前，不應塗布銀膠7。
藉由在塗布銀膠7前使燒結銀膠6b乾燥，可抑制銀膠7的對於半導體晶片2之密接性(黏性)因乾燥而降低。亦即，若銀膠7的對於半導體晶片2之密接性降低，則成為造成半導體晶片2的位置偏移之原因，而藉由在塗布銀膠7前使燒結銀膠6b乾燥，可抑制銀膠7的對於半導體晶片2之密接性的降低，減少半導體晶片2之位置偏移的發生。
接著，塗布銀膠7。
圖12為顯示圖1所示之半導體裝置的晶粒接合步驟中之銀膠的塗布方法之一例的剖面圖，圖13為本實施形態所使用的燒結銀膠與銀膠中之銀含有量的比較圖，圖14為顯示圖1所示之半導體裝置的晶粒接合步驟中之銀膠塗布後的構造之一例的部分俯視圖，圖15為顯示沿著圖14之A-A線切斷的構造之一例的剖面圖。
首先，如圖12所示，將導線框架8之晶片搭載部1c配置於平台9上，配置後，在導線框架8之晶片搭載部1c的頂面(第2表面)1ca上，利用安裝於注射器11之單點噴嘴13塗布銀膠7。銀膠7，如圖14所示，塗布在連結4個燒結銀膠6b而成的區域內。換而言之，塗布在俯視時晶片搭載部1c的中央部附近。若以另一表現方式描述，則在位於後述圖21所示的複數第1區域的各個1caa之間的第2區域1cab，塗布銀膠7。
此時，亦可利用多點噴嘴(圖9所示之沖淋式噴嘴12)，塗布銀膠7。此外，如圖14及圖15所示，與燒結銀膠6b之4處的合計塗布量相較，銀膠7的塗布量多。
另，本實施形態中，銀(Ag)膠7，係指硬化前之體積比若使銀為1，則樹脂成分為0.7程度者。此外，係指硬化後之體積比若使銀為1，則樹脂成分成為0.5程度者。
此外，亦可如圖13所示地比較燒結銀膠6b與銀膠7。亦即，銀膠7之銀含有量為60-90wt%，燒結銀膠6b之銀含有量為80wt%以上。此外，銀膠7之樹脂&溶劑摻合量為~40wt%，燒結銀膠6b之樹脂&溶劑摻合量為~20wt%。
進一步，若以空隙率(以百分率表示每單位體積之間隙的比例)比較銀膠7與燒結銀膠6b，則成為燒結銀膠6b之空隙率＞銀膠7之空隙率的關係。另，若以空孔率(將在接合層之任意剖面中空孔所占的比例，以複數個剖面平均的值)比較銀膠7與燒結銀膠6b，則成為燒結銀膠6b之空孔率＞銀膠7之空孔率。
接著，將半導體晶片2搭載於晶片搭載部1c上。
圖16為顯示圖1所示之半導體裝置的晶粒接合步驟中之晶片配置方法的一例之剖面圖，圖17為顯示圖1所示之半導體裝置的晶粒接合後之構造的一例之部分俯視圖，圖18為顯示沿著圖17之B-B線切斷的構造之一例的剖面圖，圖19為將圖18的C部之構造放大顯示的部分放大剖面圖。
此處，如圖16所示，使用筒夾14將半導體晶片2搭載於晶片搭載部1c上。此時，藉由筒夾14保持半導體晶片2並搬送半導體晶片2後，以使半導體晶片2的背面2b與晶片搭載部1c的頂面1ca，隔著燒結銀膠6b及銀膠7而互相面對之方式，將半導體晶片2配置於晶片搭載部1c上。
配置後，對半導體晶片2加熱與加壓，將半導體晶片2的背面2b，與燒結銀膠6b及銀膠7連接。具體而言，對筒夾14施加荷重，以來自平台9的熱將導線框架8之晶片搭載部1c、燒結銀膠6b及銀膠7加熱，藉以將半導體晶片2壓接在晶片搭載部1c。而此時的來自平台9之加熱溫度，例如為250℃程度，較使燒結銀膠6b乾燥時之加熱溫度(例如120℃)更高。進一步，藉由此250℃的加熱，使燒結銀膠6b進一步硬化。
另，對半導體晶片2的荷重施加，亦可藉由筒夾14以外的塊體材料等施行。
此處，利用圖17的俯視圖、圖18及圖19的剖面圖，說明燒結銀膠6b的相對於半導體晶片2之位置關係。
圖19中，使燒結銀膠6b之埋入部(半導體晶片2與晶片搭載部1c所包夾之第1部分)的水平方向S之長度為X，使燒結銀膠6b的從半導體晶片2擠出之擠出部(第2部分)的水平方向S之長度為Y。而在比較X與Y之長度時，相較於X＜Y時，以成為X＞Y時較佳。藉由成為X＞Y，在晶片角部正下方的燒結銀膠6b之連接面積變大，故可提高在晶片角部正下方之連接強度。此一結果，即便強力施加晶片角部正下方之應力，仍可提高對於此一應力之承受性。
進一步，對於上述埋入部(第1部分)X及擠出部(第2部分)Y詳細地予以說明。
圖20為顯示圖1所示之半導體裝置的晶粒接合後之構造的一例之部分俯視圖，圖21為顯示沿著圖20之C-C線切斷的構造之一例的剖面圖，圖22為顯示沿著圖20之D-D線切斷的構造之一例的剖面圖。
首先，利用圖20所示之俯視圖，說明半導體晶片2的相對於晶片搭載部1c之位置關係的定義。俯視時，半導體晶片2，具備：第1邊2ae，往第1方向15延伸；第2邊2af，位於第1邊2ae之相反側，並往第1方向15延伸；第3邊2ag，往與第1方向15交叉之第2方向16延伸；及第4邊2ah，位於第3邊2ag之相反側，並往第2方向16延伸。
進一步，俯視時，半導體晶片2，具備：第1邊2ae與第3邊2ag交會的第1角部2aa、第3邊2ag與第2邊2af交會的第2角部2ab、第2邊2af與第4邊2ah交會的第3角部2ac、及第4邊2ah與第1邊2ae交會的第4角部2ad。
而在圖20所示之將半導體晶片2搭載於晶片搭載部1c的構造中，第1角部2aa、 第2角部2ab、第3角部2ac及第4角部2ad各自之一部分，位於複數第1區域的各個1caa(圖21所示之(X1+Y1)區域)。
詳而言之，若觀察圖20之C-C線(沿著邊的線)的剖面圖(圖21)、圖20之D-D線(對角線)的剖面圖(圖22)，則可如同下述地表示。
首先，在沿著半導體晶片2的邊之剖面圖，即圖21中，半導體晶片2的邊緣區域=燒結銀膠6b的塗布區域=(X1+Y1)區域=第1區域1caa。此外，銀膠7的塗布區域=Z1區域=第2區域1cab。
此外，在沿著半導體晶片2的對角線之剖面圖，即圖22中，半導體晶片2的邊緣區域=燒結銀膠6b的塗布區域=(X2+Y2)區域=第1區域1caa。此外，銀膠7的塗布區域=Z2區域=第2區域1cab。
亦即，在沿著半導體晶片2的邊之截面構造中、或沿著半導體晶片2的對角線之截面構造中，皆滿足X1＞Y1，X2＞Y2的關係。
此外，從獲得半導體晶片2的密接性之觀點來看，宜成為Z1＞2×(X1+Y1)，Z2＞2×(X2+Y2)。進一步，宜使銀膠7的塗布面積＞燒結銀膠6b的塗布面積。
本實施形態中，在沿著半導體晶片2的邊之截面構造(圖21)及沿著半導體晶片2的對角線之截面構造(圖22)中，半導體晶片2的中心區域(中央區域)，係指與銀膠7的塗布區域(第2區域1cab)重疊之區域。
此外，在沿著半導體晶片2的邊之截面構造(圖21)及沿著半導體晶片2的對角線之截面構造(圖22)中，半導體晶片2的邊緣區域(角部區域)，係指與燒結銀膠6b的塗布區域(第1區域1caa)重疊之區域。
而在圖20所示之平面構造中，半導體晶片2的邊a1(第1邊2ae)與邊a2(第3邊2ag)之夾角(第1角部2aa)的一部分，位於燒結銀膠6b的塗布區域(第1區域1caa)。同樣地，半導體晶片2的邊a2(第3邊2ag)與邊a3(第2邊2af)之夾角(第2角部2ab)的一部分、半導體晶片2的邊a3(第2邊2af)與邊a4(第4邊2ah)之夾角(第3角部2ac)的一部分，分別在俯視時，各自位於複數燒結銀膠6b的塗布區域(第1區域1caa)。同樣地，半導體晶片2的邊a4(第4邊2ah)與邊a1(第1邊2ae)之夾角(第4角部2ad)的一部分，在俯視時，位於複數燒結銀膠6b的塗布區域(第1區域1caa)。
另，若為俯視時，將半導體晶片2的複數個角各自之一部分配置於燒結銀膠6b的塗布區域之思維方式，則考慮如同下述之概念圖。圖23為顯示圖20所示的構造之半導體晶片、銀膠、及燒結銀膠的區域之關係的一例之第1概念圖，圖24為顯示圖20所示的構造之半導體晶片、銀膠、及燒結銀膠的區域之關係的一例之第2概念圖，圖25為顯示圖23所示之半導體晶片、銀膠、及燒結銀膠的區域之關係的變形例之概念圖。
圖23~圖25中，對燒結銀膠6b的塗布區域繪上影線，對銀膠7的塗布區域未繪上影線(空心的區域)。
此處，圖23所示之第1概念圖的情況，在繪上影線之1~20的外周區域之任一處塗布燒結銀膠6b後，以半導體晶片2推壓銀膠7使其流動，在晶片下方的區域(未繪上影線之1~16的中央區域之任一處)潤濕擴散。因此，銀膠7的潤濕擴散目標受到燒結銀膠6b限定(規定)，潤濕擴散不足(=孔隙的產生)之風險增加。亦即，有產生孔隙的顧慮。
因而，如圖24所示之第2概念圖般地，俯視時，將半導體晶片2的複數個角各自之一部分配置於燒結銀膠6b的塗布區域(繪上影線之1~16的角部區域)。圖24所示之構造中，複數燒結銀膠6b的塗布區域(繪上影線之1~16的角部區域)，藉由銀膠7的塗布區域(未繪上影線之1~20的區域)而成為各自獨立(孤立)之狀態。藉此，相較於圖23的第1概念圖之構造，可抑制孔隙的產生。
另，作為圖23所示之第1概念圖的變形例，考慮圖25所示的概念圖之構造。然則，在半導體晶片2的4邊中之相對向的任2邊中，推測發生與圖23之第1概念圖相同的孔隙之顧慮，故較不適宜。亦即，在半導體晶片2的4邊中之相對向的任2邊中，銀膠7的潤濕擴散目標受到燒結銀膠6b限定(規定)，有產生孔隙的顧慮。
如同上述，燒結銀膠6b的塗布區域與銀膠7的塗布區域之關係中，如同圖24所示之第2概念圖般地，宜為複數燒結銀膠6b的塗布區域，藉由銀膠7的塗布區域而成為各自獨立(孤立)之狀態的構造。然則，亦可採用圖23所示的第1概念圖之構造、或圖25所示的第1概念圖之變形例的構造。
此處，在由複數第1區域1caa構成之燒結銀膠6b的塗布區域，與第2區域1cab即銀膠7的塗布區域之關係中，俯視時，複數第1區域1caa之面積的和，宜較第2區域1cab之面積更小。例如，為圖24所示之構造或圖25所示之構造。
上述內容，亦能夠以其他敘述方式表現。例如，如圖21及圖22所示，在從晶片搭載部1c的底面1cb朝向半導體晶片2的主面2a之第3方向17的剖面視圖中，且在與第3方向17垂直之第4方向18中，第2區域1cab，位於複數第1區域1caa所包含的第3區域1cac與複數第1區域1caa所包含的第4區域1cad之間。亦即，第2區域1cab，位於複數第1區域1caa中的第3區域1cac與複數第1區域1caa中的第4區域1cad之間。此外，第2區域1cab的第4方向18中之長度Z1(或Z2)，較第3區域1cac的第4方向18中之長度與第4區域1cad的第4方向18中之長度的和更大。亦即，(X1 +Y1)+(X1+Y1)＜Z1，(X2+Y2)+(X2+Y2)＜Z2。
此外，如圖19所示，在從晶片搭載部1c的底面1cb朝向半導體晶片2的主面2a之第3方向17的剖面視圖中，塗布於圖20所示之俯視時的複數第1區域的各個1caa (參考圖21)之燒結銀膠6b，具備在第3方向17中被半導體晶片2與晶片搭載部1c所包夾的第1部分X。進一步，具備在第3方向17中並未被半導體晶片2與晶片搭載部1c所包夾的第2部分Y。亦即，燒結銀膠6b，具備第1部分X與第2部分Y。此外，與第3方向17垂直之第4方向(S)18中的第1部分X之長度，宜較第4方向(S)18中的第2部分Y之長度更大。亦即，X＞Y較佳。藉此，在晶片角部正下方的燒結銀膠6b之連接面積變大，故可提高在晶片角部正下方之連接強度。
藉由上述方式，完成晶粒接合步驟。亦即，成為半導體晶片2的背面2b藉由燒結銀6及銀膠7而固接於晶片搭載部1c的頂面1ca之狀態。另，晶粒接合步驟中，將燒結銀膠6b加熱而使其硬化，故在較晶粒接合步驟更後期的組裝步驟中，將燒結銀膠6b稱作燒結銀6。
[3. 引線接合] 圖26為顯示圖1所示之半導體裝置的引線接合後之構造的一例之部分俯視圖，圖27為顯示沿著圖26之B-B線切斷的構造之一例的剖面圖。
晶粒接合後，如圖26及圖27所示地施行引線接合。此處，藉由源極引線即Al引線4a，將半導體晶片2的主面2a之源極用電極墊2c與源極導線1d之寬幅部1aa電性連接，此外，藉由係閘極引線且線徑較Al引線4a更小的Al引線4b，將半導體晶片2的主面2a之閘極用電極墊2d與閘極導線1e之寬幅部1aa電性連接。
此時，以源極引線、閘極引線的順序施行引線接合。亦即，首先，藉由線徑大的Al引線4a，將半導體晶片2之源極用電極墊2c與源極導線1d電性連接，其後，藉由線徑小的Al引線4b，將半導體晶片2之閘極用電極墊2d與閘極導線1e電性連接。
Al引線4a、4b，係以鋁(Al)為主成分之金屬引線，但源極引線及閘極引線，亦可使用以銅(Cu)或金(Au)為主成分之金屬引線。進一步，源極引線，為了降低ON電阻，故引線之線徑大。其大小，例如較閘極引線之線徑更大。
[4. 樹脂密封(樹脂成型)] 圖28為顯示圖1所示之半導體裝置的樹脂成型後之構造的一例之部分俯視圖，圖29為顯示沿著圖28之B-B線切斷的構造之一例的剖面圖。
在引線接合後，如圖28及圖29所示地施行樹脂密封。此處，形成密封體3，密封體3具備頂面3a、及位於頂面3a之相反側的底面3b，覆蓋半導體晶片2及晶片搭載部1c的至少一部分。亦即，以晶片搭載部1c的底面1cb在密封體3的底面3b露出之方式，形成密封體3。此外，藉由密封樹脂，將半導體晶片2、源極引線及閘極引線等Al引線4，進一步將晶片搭載部1c、源極導線1d、閘極導線1e各自之一部分密封。
另，密封樹脂，例如由環氧系樹脂等熱可塑性樹脂構成。
[5. 鍍膜形成] 圖30為顯示圖1所示之半導體裝置的鍍膜形成後之構造的一例之部分俯視圖，圖31為顯示沿著圖30之B-B線切斷的構造之一例的剖面圖。
在樹脂密封後，施行鍍膜形成。
在鍍膜形成步驟中，如圖30及圖31所示，於外引腳部(外部端子、源極導線、閘極導線)1b、及從密封體3露出之晶片搭載部1c的底面1cb，形成金屬膜即鍍膜19。
[6. 導線成形(單片化)] 在鍍膜形成後，施行導線成形。
在導線成形步驟中，將圖1所示之功率裝置5，從圖6所示之導線框架8切離而單片化(切斷/成形)。具體而言，從圖6所示之導線框架8的框部8b，將圖1所示之各外引腳部1b及懸吊導線1f切離而單片化，取得功率裝置5。
藉由上述方式，完成圖1所示之功率裝置5的組裝。
＜變形例＞ 對本實施形態的變形例予以說明。此處，關於晶粒接合步驟，茲就未實施燒結銀膠6b之乾燥的組裝予以說明。
圖32為顯示圖1所示之半導體裝置的變形例之銀膠的塗布方法之剖面圖，圖33為顯示圖1所示之半導體裝置的變形例之銀膠塗布後的構造之部分俯視圖，圖34為顯示沿著圖33之A-A線切斷的構造之剖面圖。
在晶粒接合步驟中，首先，如圖32所示，將導線框架8之晶片搭載部1c配置於平台9上，配置後，在導線框架8之晶片搭載部1c的頂面(第2表面)1ca上，利用安裝於注射器11之單點噴嘴13塗布銀(Ag)膠7。銀膠7，如圖33的俯視圖及圖34的剖面視圖所示，塗布在晶片搭載部1c的中央部附近。若以另一表現方式描述，則在圖21所示的位於複數第1區域的各個1caa之間的第2區域1cab，塗布銀膠7。
此時，亦可利用多點噴嘴，塗布銀膠7。
另，本變形例中，銀膠7，亦指硬化前之體積比若使銀為1，則樹脂成分為0.7程度者。此外，係指硬化後之體積比若使銀為1，則樹脂成分成為0.5程度者。
在塗布銀膠7後，塗布燒結銀膠6b。
圖35為顯示圖1所示之半導體裝置的變形例之燒結銀膠的塗布方法之剖面圖，圖36為顯示圖1所示之半導體裝置的另一變形例之燒結銀膠的塗布方法之剖面圖，圖37為顯示圖1所示之半導體裝置的變形例之燒結銀膠塗布後的構造之部分俯視圖，圖38為顯示沿著圖37之A-A線切斷的構造之一例的剖面圖。
如圖35所示，在塗布有銀膠7之晶片搭載部1c的頂面1ca，塗布燒結銀膠6b。此處處理之燒結銀膠6b為膠狀的燒結銀材料。此外，塗布之區域，具體而言，為圖21所示之晶片搭載部1c的頂面1ca之複數第1區域的各個1caa，在複數第1區域的各個1caa塗布燒結銀膠6b。此處，如圖37所示，在俯視時呈略四角形之晶片搭載部1c的頂面1ca之各4個角部附近，塗布燒結銀膠6b。
此時，例如，藉由網版印刷，塗布膠狀的燒結銀材料，即燒結銀膠6b。詳而言之，如圖35所示地將導線框架8載置於平台9，在此一狀態下，使用金屬遮罩10，於導線框架8之晶片搭載部1c的頂面1ca上塗布燒結銀膠6b。此時，於晶片搭載部1c的頂面1ca中，在圖21所示之各個複數該第1區域1caa，塗布燒結銀膠6b。
另，本變形例中，燒結銀膠6b，係指硬化前之體積比若使銀為1，則樹脂成分為0.3程度，因此，硬化後，樹脂成分幾乎不存在者。
此外，作為代替方法，亦可如圖36所示，利用沖淋式噴嘴(多點噴嘴)12，於導線框架8之晶片搭載部1c的頂面1ca上塗布燒結銀膠6b。亦即，利用安裝在注射器11之沖淋式噴嘴12，將燒結銀膠6b於晶片搭載部1c的頂面1ca多點塗布。
如此地藉由利用沖淋式噴嘴12將燒結銀膠6b多點塗布，而可對晶片搭載部1c的頂面1ca之複數第1區域1caa效率良好地塗布燒結銀膠6b，可改善將功率裝置5量產時的生產力。
然則，作為變形例，亦可利用單點噴嘴13(參考圖32)，於晶片搭載部1c的頂面1ca塗布燒結銀膠6b。
另，如圖37及圖38所示，與燒結銀膠6b之4處的合計塗布量相較，銀膠7的塗布量多。
此外，本變形例中，亦可如圖13所示地比較銀膠7與燒結銀膠6b。亦即，銀膠7之銀含有量為60-90wt%，燒結銀膠6b之銀含有量為80wt%以上。此外，銀膠7之樹脂&溶劑摻合量為~40wt%，燒結銀膠6b之樹脂&溶劑摻合量為20wt%。進一步，若以空隙率(以百分率表示每單位體積之間隙的比例)比較銀膠7與燒結銀膠6b，則成為燒結銀膠6b之空隙率＞銀膠7之空隙率的關係。另，若以空孔率(將在接合層之任意剖面中空孔所占的比例，以複數個剖面平均的值)比較銀膠7與燒結銀膠6b，則成為燒結銀膠6b之空孔率＞銀膠7之空孔率。
在塗布銀膠7與燒結銀膠6b後，如圖39所示，使用筒夾14將半導體晶片2搭載於晶片搭載部1c上。此時，藉由筒夾14保持半導體晶片2並搬送半導體晶片2後，以使半導體晶片2的背面2b與晶片搭載部1c的頂面1ca，隔著燒結銀膠6b及銀膠7而互相面對之方式，將半導體晶片2配置於晶片搭載部1c上。
在晶片搭載後，施行銀膠7及燒結銀膠6b之固化步驟，完成晶粒接合步驟。
在本變形例的晶粒接合中，亦與圖17~圖22所示之構造同樣地，於晶片搭載部1c的第1區域1caa塗布燒結銀膠6b，並於第2區域1cab塗布銀膠7，進一步在俯視時，以半導體晶片2將其4個角部分別配置在第1區域1caa的方式予以晶粒接合即可。
另，本變形例之晶粒接合中，不具有燒結銀膠6b的乾燥步驟，故雖對於在塗布銀膠7後塗布燒結銀膠6b之情況進行說明，但本變形例之晶粒接合，亦可在塗布燒結銀膠6b後塗布銀膠7。
＜效果＞ 依本實施形態的半導體裝置(功率裝置5)之製造方法，則在俯視時，藉由在半導體晶片2的角部配置由燒結銀膠6b(燒結銀6)構成之接合部，而變得不易在半導體晶片2的複數角部各自之正下方發生晶片-黏晶材間的破壞(裂縫、剝離)。
亦即，在製品完成後之溫度循環測試等，即便受到因半導體晶片2與晶片搭載部(晶粒墊)1c的線膨脹係數差而產生之熱應力，仍因在半導體晶片2的角部配置由燒結銀膠6b(燒結銀6)構成之接合部，而可提高上述接合部的強度。藉此，變得不易發生在半導體晶片2各自的角部正下方之晶片-黏晶材間的破壞。亦即，可抑制在半導體晶片2各自的角部正下方之晶片-黏晶材間的破壞之發生。
此一結果，可改善半導體裝置(功率裝置5)的可靠度。
此外，俯視時，相較於在晶片搭載部1c塗布有燒結銀膠6b的區域，塗布有銀膠7的區域較大，故可防止燒結銀膠6b之硬化所造成的晶片搭載部1c之變形。
換而言之，銀膠7黏接在半導體晶片2之面積，較燒結銀膠6b黏接在半導體晶片2之面積更大。藉此，可防止燒結銀膠6b之硬化所造成的晶片搭載部1c之變形，與上述內容同樣地，可改善半導體裝置(功率裝置5)的可靠度。
進一步，在需要對應高散熱之半導體裝置(功率裝置5)中，即便係為了進一步改善散熱性，而將晶片搭載部1c的厚度減薄之構造，仍可防止晶片搭載部1c的變形，可提高半導體裝置(功率裝置5)的可靠度及品質。
此外，在晶粒接合步驟中，藉由使燒結銀膠6b乾燥，而可降低燒結銀膠6b的流動性。此外，藉由在塗布銀膠7前使燒結銀膠6b乾燥，可抑制銀膠7的對於半導體晶片2之密接性因乾燥而降低。亦即，藉由在塗布銀膠7前使燒結銀膠6b乾燥，而可抑制銀膠7的對於半導體晶片2之密接性的降低，減少搭載半導體晶片2時之半導體晶片2的位置偏移之發生。
以上，雖依據實施形態具體地說明本案發明人所提出之發明，但本發明並未限定於至此之前所記載的實施形態，在不脫離其要旨之範疇內自然可進行各種變更。
例如，上述實施形態中，雖說明半導體裝置(功率裝置5)的複數外引腳部1b，各自從密封體3露出而筆直地延伸之情況，但複數外引腳部1b，例如亦可各自折彎為鷗翼狀。
進一步，作為組裝於半導體裝置內之元件，在半導體裝置為晶粒墊露出型之QFP等的情況，亦可為內建有MCU(Micro Control Unit，微控制單元)之IC(Integr ated Circuit，積體電路)等。
此外，在未脫離上述實施形態所說明之技術思想要旨的範疇內，可將實施例與變形例組合應用。
1‧‧‧導線部
1a‧‧‧內引腳部
1aa‧‧‧寬幅部
1b‧‧‧外引腳部
1c‧‧‧晶片搭載部
1ca‧‧‧頂面(第2表面)
1caa‧‧‧第1區域
1cab‧‧‧第2區域
1cac‧‧‧第3區域
1cad‧‧‧第4區域
1cb‧‧‧底面(第2背面)
1d‧‧‧源極導線
1e‧‧‧閘極導線
1f‧‧‧懸吊導線
2‧‧‧半導體晶片
2a‧‧‧主面(第1表面)
2aa‧‧‧第1角部
2ab‧‧‧第2角部
2ac‧‧‧第3角部
2ad‧‧‧第4角部
2ae‧‧‧第1邊
2af‧‧‧第2邊
2ag‧‧‧第3邊
2ah‧‧‧第4邊
2b‧‧‧背面(第1背面)
2c‧‧‧源極用電極墊
2d‧‧‧閘極用電極墊
2e‧‧‧汲極用電極
3‧‧‧密封體
3a‧‧‧頂面(第3表面)
3b‧‧‧底面(第4背面)
3c‧‧‧側面
4、4a、4b‧‧‧Al引線
5‧‧‧功率裝置(半導體裝置)
6‧‧‧燒結銀(第1接合材)
6a‧‧‧粒子
6b‧‧‧燒結銀膠(第1接合材)
7‧‧‧銀膠(第2接合材)
7a‧‧‧粒子
8‧‧‧導線框架
8a‧‧‧裝置區
8b‧‧‧框部
9‧‧‧平台
10‧‧‧金屬遮罩
11‧‧‧注射器
12‧‧‧沖淋式噴嘴
13‧‧‧單點噴嘴
14‧‧‧筒夾
15‧‧‧第1方向
16‧‧‧第2方向
17‧‧‧第3方向
18‧‧‧第4方向
19‧‧‧鍍膜
50‧‧‧半導體裝置
a1~a4‧‧‧邊
X‧‧‧埋入部(第1部分)
Y‧‧‧擠出部(第2部分)
【圖1】係透視內部而顯示實施形態之半導體裝置的構造之一例的俯視圖。 【圖2】係顯示沿著圖1之A-A線切斷的構造之一例的剖面圖。 【圖3】係將圖2的B部之構造放大顯示的部分放大剖面圖。 【圖4】係顯示本案發明人所研討的半導體裝置之構造的第1問題圖。 【圖5】係顯示本案發明人所研討的半導體裝置之構造的第2問題圖。 【圖6】係顯示在圖1所示之半導體裝置的組裝所使用之導線框架的要部構造之一例的部分俯視圖。 【圖7】係顯示沿著圖6之A-A線切斷的構造之一例的剖面圖。 【圖8】係顯示圖1所示之半導體裝置的晶粒接合步驟中之燒結銀膠的塗布方法之一例的剖面圖。 【圖9】係顯示圖1所示之半導體裝置的晶粒接合步驟中之燒結銀膠的塗布方法之變形例的剖面圖。 【圖10】係顯示圖1所示之半導體裝置的晶粒接合步驟中之燒結銀膠塗布後的構造之一例的部分俯視圖。 【圖11】係顯示沿著圖10之A-A線切斷的構造之一例的剖面圖。 【圖12】係顯示圖1所示之半導體裝置的晶粒接合步驟中之銀膠的塗布方法之一例的剖面圖。 【圖13】係本實施形態所使用的燒結銀膠與銀膠中之銀含有量的比較圖。 【圖14】係顯示圖1所示之半導體裝置的晶粒接合步驟中之銀膠塗布後的構造之一例的部分俯視圖。 【圖15】係顯示沿著圖14之A-A線切斷的構造之一例的剖面圖。 【圖16】係顯示圖1所示之半導體裝置的晶粒接合步驟中之晶片配置方法的一例之剖面圖。 【圖17】係顯示圖1所示之半導體裝置的晶粒接合後之構造的一例之部分俯視圖。 【圖18】係顯示沿著圖17之B-B線切斷的構造之一例的剖面圖。 【圖19】係將圖18的C部之構造放大顯示的部分放大剖面圖。 【圖20】係顯示圖1所示之半導體裝置的晶粒接合後之構造的一例之部分俯視圖。 【圖21】係顯示沿著圖20之C-C線切斷的構造之一例的剖面圖。 【圖22】係顯示沿著圖20之D-D線切斷的構造之一例的剖面圖。 【圖23】係顯示圖20所示的構造之半導體晶片、銀膠、及燒結銀膠的區域之關係的一例之第1概念圖。 【圖24】係顯示圖20所示的構造之半導體晶片、銀膠、及燒結銀膠的區域之關係的一例之第2概念圖。 【圖25】係顯示圖23所示之半導體晶片、銀膠、及燒結銀膠的區域之關係的變形例之概念圖。 【圖26】係顯示圖1所示之半導體裝置的引線接合後之構造的一例之部分俯視圖。 【圖27】係顯示沿著圖26之B-B線切斷的構造之一例的剖面圖。 【圖28】係顯示圖1所示之半導體裝置的樹脂成型後之構造的一例之部分俯視圖。 【圖29】係顯示沿著圖28之B-B線切斷的構造之一例的剖面圖。 【圖30】係顯示圖1所示之半導體裝置的鍍膜形成後之構造的一例之部分俯視圖。 【圖31】係顯示沿著圖30之B-B線切斷的構造之一例的剖面圖。 【圖32】係顯示圖1所示之半導體裝置的變形例之銀膠的塗布方法之剖面圖。 【圖33】係顯示圖1所示之半導體裝置的變形例之銀膠塗布後的構造之部分俯視圖。 【圖34】係顯示沿著圖33之A-A線切斷的構造之剖面圖。 【圖35】係顯示圖1所示之半導體裝置的變形例之燒結銀膠的塗布方法之剖面圖。 【圖36】係顯示圖1所示之半導體裝置的另一變形例之燒結銀膠的塗布方法之剖面圖。 【圖37】係顯示圖1所示之半導體裝置的變形例之燒結銀膠塗布後的構造之部分俯視圖。 【圖38】係顯示沿著圖37之A-A線切斷的構造之一例的剖面圖。 【圖39】係顯示圖1所示之半導體裝置的晶粒接合步驟中之變形例的晶片配置方法之剖面圖。

Claims (20)

  1. 一種半導體裝置之製造方法，包含如下步驟： (a) 準備半導體晶片，該半導體晶片具備第1表面、及位於該第1表面之相反側的第1背面； (b) 準備具有晶片搭載部的導線框架，該晶片搭載部具備第2表面、及位於該第2表面之相反側的第2背面； (c) 於該(a)步驟與該(b)步驟後，在該晶片搭載部的該第2表面之複數第1區域的各個，塗布第1接合材； (d) 於該(c)步驟後，使該第1接合材乾燥； (e) 於該(d)步驟後，在位於該複數第1區域的各個之間的第2區域，塗布第2接合材； (f) 於該(e)步驟後，以使該半導體晶片的該第1背面與該晶片搭載部的該第2表面， 隔著該第1接合材與該第2接合材而互相面對之方式，將該半導體晶片搭載於該晶片搭載部；以及 (g) 於該(f)步驟後，對該半導體晶片加熱與加壓，將該半導體晶片的該第1背面，與該第1接合材及該第2接合材連接； 此處，俯視時，該半導體晶片具備：第1邊，往第1方向延伸；第2邊，位於該第1邊之相反側，往該第1方向延伸；第3邊，往與該第1方向交叉之第2方向延伸；及第4邊，位於該第3邊之相反側，往該第2方向延伸； 俯視時，該半導體晶片進一步具備：該第1邊與該第3邊交會的第1角部、該第3邊與該第2邊交會的第2角部、該第2邊與該第4邊交會的第3角部、及該第4邊與該第1邊交會的第4角部； 於該(f)步驟後，俯視時，該第1角部、該第2角部、該第3角部及該第4角部各自之一部分，位於該複數第1區域的各個。
  2. 如申請專利範圍第1項之半導體裝置之製造方法，其中， 於該(f)步驟後，俯視時，該複數第1區域之面積的和，較該第2區域之面積更小。
  3. 如申請專利範圍第2項之半導體裝置之製造方法，其中， 於該(f)步驟後，在從該晶片搭載部的該第2背面朝向該半導體晶片的該第1表面之第3方向的剖面視圖中， 在與該第3方向垂直之第4方向中，該第2區域，位於該複數第1區域所包含的第3區域與該複數第1區域所包含的第4區域之間； 該第2區域的該第4方向中之長度，較該第3區域的該第4方向中之長度與該第4區域的該第4方向中之長度的和更大。
  4. 如申請專利範圍第1項之半導體裝置之製造方法，其中， 於該(f)步驟後，在從該晶片搭載部的該第2背面朝向該半導體晶片的該第1表面之第3方向的剖面視圖中， 塗布於該複數第1區域的各個之該第1接合材，具備在該第3方向中被該半導體晶片與該晶片搭載部所包夾的第1部分、及在該第3方向中並未被該半導體晶片與該晶片搭載部所包夾的第2部分； 與該第3方向垂直之第4方向中的第1部分之長度，較該第4方向中的第2部分之長度更大。
  5. 如申請專利範圍第1項之半導體裝置之製造方法，其中， 該(f)步驟中的將該第1接合材及該第2接合材加熱之溫度，較該(d)步驟中的使該第1接合材乾燥之溫度更高。
  6. 如申請專利範圍第1項之半導體裝置之製造方法，其中， 包含(h)步驟：於該(g)步驟後，形成密封體，該密封體具備第3表面與位於該第3表面之相反側的第3背面，覆蓋該半導體晶片及該晶片搭載部的至少一部分； 於該(h)步驟後，在該密封體的該第3背面，露出該晶片搭載部的該第2背面。
  7. 如申請專利範圍第1項之半導體裝置之製造方法，其中， 在該(c)步驟，將該第1接合材於該晶片搭載部的該第2表面多點塗布。
  8. 如申請專利範圍第1項之半導體裝置之製造方法，其中， 於該半導體晶片的該第1表面，露出源極用電極及閘極用電極； 於該半導體晶片的該第1背面，具備汲極用電極。
  9. 一種半導體裝置之製造方法，包含如下步驟： (a) 準備半導體晶片，該半導體晶片具備第1表面、及位於該第1表面之相反側的第1背面； (b) 準備具有晶片搭載部的導線框架，該晶片搭載部具備第2表面、及位於該第2表面之相反側的第2背面； (c) 於該(a)步驟與該(b)步驟後，在該晶片搭載部的該第2表面，塗布用於形成燒結銀的燒結銀膠或銀膠之一者； (d) 於該(c)步驟後，在該晶片搭載部的該第2表面，塗布該燒結銀膠或該銀膠之另一者； (e) 於該(d)步驟後，以使該半導體晶片的該第1背面與該晶片搭載部的該第2表面，隔著該燒結銀膠與該銀膠而互相面對之方式，將該半導體晶片搭載於該晶片搭載部；以及 (f) 於該(e)步驟後，對該半導體晶片加熱，將該半導體晶片的該第1背面，與該燒結銀膠及該銀膠連接； 此處， 於該(c)步驟及該(d)步驟中，該燒結銀膠，塗布在該晶片搭載部的該第2表面之複數第1區域的各個，而該銀膠，塗布在位於該複數第1區域的各個之間的第2區域； 俯視時，該半導體晶片具備：第1邊，往第1方向延伸；第2邊，位於該第1邊之相反側，往該第1方向延伸；第3邊，往與該第1方向交叉之第2方向延伸；及第4邊，位於該第3邊之相反側，往該第2方向延伸； 俯視時，該半導體晶片進一步具備：該第1邊與該第3邊交會的第1角部、該第3邊與該第2邊交會的第2角部、該第2邊與該第4邊交會的第3角部、及該第4邊與該第1邊交會的第4角部； 於該(e)步驟後，俯視時，該第1角部、該第2角部、該第3角部及該第4角部各自之一部分，位於該複數第1區域的各個。
  10. 如申請專利範圍第9項之半導體裝置之製造方法，其中， 於該(e)步驟後，俯視時，該複數第1區域之面積的和，較該第2區域之面積更小。
  11. 如申請專利範圍第9項之半導體裝置之製造方法，其中， 於該(e)步驟後，在從該晶片搭載部的該第2背面朝向該半導體晶片的該第1表面之第3方向的剖面視圖中， 在與該第3方向垂直之第4方向中，該第2區域，位於該複數第1區域所包含的第3區域與該複數第1區域所包含的第4區域之間； 該第2區域的該第4方向中之長度，較該第3區域的該第4方向中之長度與該第4區域的該第4方向中之長度的和更大。
  12. 如申請專利範圍第9項之半導體裝置之製造方法，其中， 於該(e)步驟後，在從該晶片搭載部的該第2背面朝向該半導體晶片的該第1表面之第3方向的剖面視圖中， 塗布於該複數第1區域的各個之該燒結銀膠，具備在該第3方向中被該半導體晶片與該晶片搭載部所包夾的第1部分、及在該第3方向中並未被該半導體晶片與該晶片搭載部所包夾的第2部分； 與該第3方向垂直之第4方向中的第1部分之長度，較該第4方向中的第2部分之長度更大。
  13. 如申請專利範圍第9項之半導體裝置之製造方法，其中， 包含(g)步驟：於該(f)步驟後，形成密封體，該密封體具備第3表面與位於該第3表面之相反側的第3背面，覆蓋該半導體晶片及該晶片搭載部的至少一部分； 於該(g)步驟後，在該密封體的該第3背面，露出該晶片搭載部的該第2背面。
  14. 如申請專利範圍第9項之半導體裝置之製造方法，其中， 在該(c)步驟或該(d)步驟，將該燒結銀膠於該晶片搭載部的該第2表面多點塗布。
  15. 如申請專利範圍第9項之半導體裝置之製造方法，其中， 於該半導體晶片的該第1表面，露出源極用電極及閘極用電極； 於該半導體晶片的該第1背面，具備汲極用電極。
  16. 一種半導體裝置，包含： 半導體晶片，具備露出第1電極及第2電極的第1表面、及形成有第3電極的第1背面，該第1背面係該第1表面之相反側； 晶片搭載部，具備搭載有該半導體晶片的第2表面、及該第2表面之相反側的第2背面； 第1導線，經由第1導電性構件而與該半導體晶片之該第1電極電性連接； 第2導線，經由第2導電性構件而與該半導體晶片之該第2電極電性連接；以及 密封體，將該半導體晶片、該第1導電性構件、該第2導電性構件、該晶片搭載部之一部分、該第1導線之一部分、該第2導線之一部分密封； 該半導體晶片的該第1背面，隔著第1接合材與第2接合材而與該晶片搭載部的該第2表面互相面對； 俯視時，該晶片搭載部的該第2表面，具備該第1接合材所在處的複數第1區域，以及位於該複數第1區域的各個之間、該第2接合材所在處的第2區域； 俯視時，該半導體晶片具備：第1邊，往第1方向延伸；第2邊，位於該第1邊之相反側，往該第1方向延伸；第3邊，往與該第1方向交叉之第2方向延伸；及第4邊，位於該第3邊之相反側，往該第2方向延伸； 俯視時，該半導體晶片進一步具備：該第1邊與該第3邊交會的第1角部、該第3邊與該第2邊交會的第2角部、該第2邊與該第4邊交會的第3角部、及該第4邊與該第1邊交會的第4角部； 俯視時，該第1角部、該第2角部、該第3角部及該第4角部各自之一部分，位於該複數第1區域的各個。
  17. 如申請專利範圍第16項之半導體裝置，其中， 俯視時，該複數第1區域之面積的和，較該第2區域之面積更小。
  18. 如申請專利範圍第17項之半導體裝置，其中， 在從該晶片搭載部的該第2背面朝向該半導體晶片的該第1表面之第3方向的剖面視圖中， 在與該第3方向垂直之第4方向中，該第2區域，位於該複數第1區域所包含的第3區域與該複數第1區域所包含的第4區域之間； 該第2區域的該第4方向中之長度，較該第3區域的該第4方向中之長度與該第4區域的該第4方向中之長度的和更大。
  19. 如申請專利範圍第16項之半導體裝置，其中， 在從該晶片搭載部的該第2背面朝向該半導體晶片的該第1表面之第3方向的剖面視圖中， 塗布於該複數第1區域的各個之該第1接合材，具備在該第3方向中被該半導體晶片與該晶片搭載部所包夾的第1部分、及在該第3方向中並未被該半導體晶片與該晶片搭載部所包夾的第2部分； 與該第3方向垂直之第4方向中的第1部分之長度，較該第4方向中的第2部分之長度更大。
  20. 如申請專利範圍第16項之半導體裝置，其中， 該第1接合材之粒子，相較於該第2接合材之粒子，粒徑更小。
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