TW201916136A - Wafer processing method to simultaneously perform the alignment step while the area imaged by the visible-light imaging means is obliquely irradiated by an oblique light means - Google Patents

Wafer processing method to simultaneously perform the alignment step while the area imaged by the visible-light imaging means is obliquely irradiated by an oblique light means Download PDF

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TW201916136A
TW201916136A TW107132557A TW107132557A TW201916136A TW 201916136 A TW201916136 A TW 201916136A TW 107132557 A TW107132557 A TW 107132557A TW 107132557 A TW107132557 A TW 107132557A TW 201916136 A TW201916136 A TW 201916136A
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wafer
sealing material
front surface
alignment
processing method
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TW107132557A
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TWI769311B (en
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鈴木克彥
伴祐人
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日商迪思科股份有限公司
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0058—Accessories specially adapted for use with machines for fine working of gems, jewels, crystals, e.g. of semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/02—Positioning or observing the workpiece, e.g. with respect to the point of impact; Aligning, aiming or focusing the laser beam
    • B23K26/03—Observing, e.g. monitoring, the workpiece
    • B23K26/032—Observing, e.g. monitoring, the workpiece using optical means
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/08—Devices involving relative movement between laser beam and workpiece
    • B23K26/083—Devices involving movement of the workpiece in at least one axial direction
    • B23K26/0853—Devices involving movement of the workpiece in at least in two axial directions, e.g. in a plane
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    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/50—Working by transmitting the laser beam through or within the workpiece
    • B23K26/53—Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0005—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing
    • B28D5/0011—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing with preliminary treatment, e.g. weakening by scoring
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0058—Accessories specially adapted for use with machines for fine working of gems, jewels, crystals, e.g. of semiconductor material
    • B28D5/0064—Devices for the automatic drive or the program control of the machines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/40—Semiconductor devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/16—Composite materials, e.g. fibre reinforced
    • B23K2103/166—Multilayered materials
    • B23K2103/172—Multilayered materials wherein at least one of the layers is non-metallic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
    • B23K2103/56—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26 semiconducting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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Abstract

To provide a wafer processing method capable of performing an alignment process by using a carbon black-containing sealing material coated on the front surface of a wafer. A wafer processing method is to seal a front surface of a device wafer with a sealing material, and form a plurality of bumps in the chip regions of the sealing material. The device wafer is formed with devices in the chip regions which are divided by a plurality of predetermined dividing lines formed in a manner of crossing each other on the front surface. The wafer processing method is characterized by comprising: an alignment step for using a visible-light imaging means passing through the sealing material from the front surface side of the wafer to image the front surface side of the device wafer and detect the alignment marks, and detecting the predetermined dividing lines for performing laser processing based on the alignment marks; a modified layer forming step for, after the alignment step, positioning the condensing point of a laser beam having a transmissive wavelength to the device wafer and the sealing material in the interior of the device wafer and the sealing material, and irradiating the laser beam along the predetermined dividing line from the front surface side of the wafer to form a modified layer in the interior of the device wafer and the sealing material; and a cutting step for, after the modified layer forming step, applying an external force to the device wafer and the sealing material, serving the modified layer as the cutting starting point, and dividing the wafer into a plurality of device chips, each of which has a front surface sealed by the sealing material. The alignment step is simultaneously performed while the area imaged by the visible-light imaging means is obliquely irradiated by an oblique light means.

Description

晶圓加工方法Wafer processing method

本發明為關於WL-CSP晶圓的加工方法。The invention relates to a method for processing a WL-CSP wafer.

WL-CSP（Wafer-level Chip Size Package，晶圓級晶片尺寸封裝）晶圓是在晶圓的狀態下形成重佈層及電極（金屬柱）後，將正面側以樹脂密封，並以切割刀片等分割成各封裝件的技術，因為晶圓單體化後的封裝件的大小近似於半導體元件晶片的大小，從小型化及輕量化的觀點亦被廣泛採用。WL-CSP (Wafer-level Chip Size Package) wafers are formed with a redistribution layer and electrodes (metal pillars) in the state of the wafer, and then the front side is sealed with resin, and a dicing blade is used. The technology of equal division into individual packages is widely adopted from the viewpoint of miniaturization and weight reduction because the size of the package after the wafer is singulated is similar to that of a semiconductor element wafer.

在WL-CSP晶圓的製程中，在形成多個元件的元件晶圓之元件面側形成重佈層，並進一步透過重佈層形成用來連接元件中的電極的金屬柱後，以樹脂密封金屬柱及元件。In the manufacturing process of the WL-CSP wafer, a redistribution layer is formed on the element surface side of an element wafer on which a plurality of elements are formed, and a metal pillar for connecting electrodes in the element is formed through the redistribution layer, and then sealed with a resin. Metal posts and components.

接著，薄化密封材並同時使金屬柱在密封材表面露出後，在金屬柱的端面形成被稱為電極凸塊的外部端子。之後，以切割裝置等切割WL-CSP晶圓並分割為一個個的CSP。Next, after the sealing material is thinned and the metal pillar is exposed on the surface of the sealing material, an external terminal called an electrode bump is formed on an end surface of the metal pillar. After that, the WL-CSP wafer is cut by a dicing device or the like and divided into individual CSPs.

為了保護半導體晶圓免於衝擊或濕氣等，以密封材進行密封相當重要。通常，作為密封材，藉由使用在環氧樹脂中混入由SiC所組成的填充料而成之密封材，密封材的熱膨脹係數近似於半導體元件晶片的熱膨脹係數，因而防止藉由熱膨脹係數的差異所產生加熱時的封裝件的損壞。In order to protect semiconductor wafers from impact, moisture, etc., it is important to seal with a sealing material. Generally, as a sealing material, a sealing material made of epoxy resin mixed with a filler composed of SiC is used. The thermal expansion coefficient of the sealing material is similar to the thermal expansion coefficient of a semiconductor element wafer, thus preventing the difference in thermal expansion coefficient. Damage to the package during heating.

WL-CSP晶圓一般而言使用切割裝置分割為一個個的CSP。在此種情況，由於樹脂覆蓋住為了檢測分割預定線而利用的元件，故WL-CSP晶圓無法從正面側檢測元件的目標（target）圖案。WL-CSP wafers are generally divided into individual CSPs using a dicing device. In this case, since the element used for detecting the predetermined division line is covered by the resin, the WL-CSP wafer cannot detect the target pattern of the element from the front side.

為此，以在WL-CSP晶圓的樹脂上形成的電極凸塊為目標分度分割預定線，並在樹脂上表面印刷對準用的目標等，進行分割預定線和切割刀片的對準。For this purpose, an electrode bump formed on the resin of the WL-CSP wafer is used as the target division and division line, and a target for alignment is printed on the upper surface of the resin to align the division line and the cutting blade.

但是，在電極凸塊或樹脂上印刷的目標並未形成為如元件般高精確度，故作為對準用的目標有低精確度的問題。因此，基於電極凸塊或印刷的目標而分度分割預定線的情況，恐有偏離分割預定線而切割到元件部分之慮。However, the target printed on the electrode bump or the resin is not formed to have a high accuracy as an element, so there is a problem of low accuracy as an object for alignment. Therefore, when the predetermined line is divided based on the electrode bump or the printed target, there is a fear that the element line may be cut off from the predetermined division line.

因此，例如在日本特開2013-74021號公報中，提出基於在晶圓的外周露出的元件晶圓的圖案來進行對準的方法。 [習知技術文獻] [專利文獻]Therefore, for example, Japanese Patent Application Laid-Open No. 2013-74021 proposes a method of performing alignment based on the pattern of the element wafer exposed on the outer periphery of the wafer. [Habitual technical literature] [patent literature]

[專利文獻1]日本特開2013-074021號公報 [專利文獻2]日本特開2016-015438號公報[Patent Document 1] Japanese Patent Application Publication No. 2013-074021 [Patent Document 2] Japanese Patent Application Publication No. 2016-015438

[發明所欲解決的課題] 但是，一般在晶圓的外周上的元件精確度差，若基於在晶圓的外周露出的圖案實施對準時，除有在偏離分割預定線的位置上分割晶圓之慮，更有因晶圓不同而有元件晶圓的圖案不在外周露出之情況。[Problems to be Solved by the Invention] However, in general, the accuracy of components on the outer periphery of a wafer is poor. When alignment is performed based on a pattern exposed on the outer periphery of the wafer, the wafer is divided at a position deviating from a predetermined division line. It is more concerned that the pattern of the element wafer may not be exposed on the periphery due to different wafers.

本發明鑒於上述的問題點，其目的為提供一種晶圓加工方法，能藉由在晶圓正面被覆之包含炭黑的密封材而實施對準步驟。In view of the above problems, the present invention aims to provide a wafer processing method capable of performing an alignment step by using a sealing material containing carbon black coated on the front side of a wafer.

[解決課題的技術手段] 根據本發明，提供一種晶圓加工方法，以密封材密封元件晶圓的正面，在該密封材的該晶片區域上分別形成多個凸塊，該元件晶圓藉由在正面交叉形成的多條分割預定線劃分的晶片區域上分別形成元件而成，該晶圓加工方法的特徵在於具備：對準步驟，從該晶圓的正面側藉由可見光攝像手段穿透該密封材，對該元件晶圓的正面側攝像並檢測對準標記，且基於該對準標記檢測應進行雷射加工的該分割預定線；改質層形成步驟，在實施了該對準步驟後，將對該元件晶圓及該密封材具有穿透性的波長之雷射光束的聚光點定位於該元件晶圓及該密封材的內部，從該晶圓的正面側沿著該分割預定線照射雷射光束，在該元件晶圓及該密封材的內部形成改質層；以及分割步驟，在實施了該改質層形成步驟後，對該元件晶圓及該密封材施加外力，並以該改質層作為分割起點分割為正面藉由密封材密封的一個個的元件晶片；該對準步驟係在藉由該可見光攝像手段進行攝像的區域中藉由斜光手段照射斜向來的光並同時實施。[Technical means to solve the problem] According to the present invention, there is provided a wafer processing method in which a front surface of a component wafer is sealed with a sealing material, and a plurality of bumps are formed on the wafer region of the sealing material, respectively. Components are formed on the wafer regions divided by a plurality of predetermined division lines formed on the front side. The wafer processing method is characterized by including an alignment step to penetrate the wafer from the front side of the wafer by visible light imaging means. Sealing material, imaging the front side of the element wafer and detecting an alignment mark, and based on the alignment mark, the predetermined dividing line for laser processing should be detected; a reforming layer forming step, after performing the alignment step The focusing point of the laser beam having a wavelength penetrating to the element wafer and the sealing material is positioned inside the element wafer and the sealing material, and the division is planned along the division from the front side of the wafer. A laser beam is radiated to form a modified layer inside the element wafer and the sealing material; and a dividing step, after the step of forming the modified layer is performed, an external coating is applied to the element wafer and the sealing material And using the modified layer as a starting point for division into individual element wafers sealed by a sealing material on the front side; the alignment step is to irradiate obliquely by oblique light in an area imaged by the visible light imaging means Light simultaneously.

[發明功效] 根據本發明的晶圓加工方法，以斜光手段照射斜向來的光，並同時藉由可見光攝像手段穿透密封材而檢測在元件晶圓上形成的對準標記，且能基於對準標記實施對準，因此不需如以往般去除在晶圓的正面的外周部分的密封材，即可簡單實施對準步驟。[Effect of the invention] According to the wafer processing method of the present invention, the oblique light is irradiated by oblique light, and at the same time, the sealing material is penetrated by the visible light imaging means to detect the alignment mark formed on the element wafer. The alignment is performed with the quasi-marks, so the alignment step can be easily performed without removing the sealing material on the outer peripheral portion of the front surface of the wafer as usual.

因此，將對元件晶圓及密封材具有穿透性的波長之雷射光束的聚光點定位於元件晶圓及密封材的內部，從晶圓的正面側照射雷射光束，在元件晶圓及密封材的內部形成改質層，能夠以該改質層作為分割起點將晶圓分割為正面藉由密封材密封的一個個的元件晶片。Therefore, the condensing point of the laser beam having a wavelength that is transparent to the element wafer and the sealing material is positioned inside the element wafer and the sealing material, and the laser beam is irradiated from the front side of the wafer to the element wafer. A modified layer is formed inside the sealing material, and the modified layer can be used as a starting point for dividing the wafer into individual element wafers whose front surfaces are sealed with the sealing material.

以下參閱圖式詳細說明本發明的實施方式。WL-CSP晶圓27的分解立體圖參閱圖1（A）而示出。圖1（B）係WL-CSP晶圓27的立體圖。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. An exploded perspective view of the WL-CSP wafer 27 is shown with reference to FIG. 1 (A). FIG. 1 (B) is a perspective view of the WL-CSP wafer 27.

如圖1（A）所示，在元件晶圓11的正面11a上，在形成為格子狀的多條分割預定線（切割道）13所劃分的各區域上形成LSI（Large Scale Integration，大型積體電路）等的元件15。As shown in FIG. 1 (A), on the front surface 11a of the element wafer 11, a large scale integration (LSI) is formed on each area divided by a plurality of predetermined division lines (cut lines) 13 formed in a grid pattern. Body circuit) and other components 15.

元件晶圓（以下有單純略稱為晶圓之情形）11是預先研削背面11b並薄化至預定的厚度（100~200µm程度）後，如圖2所示，在元件15中的電極17形成電性連接的多個金屬柱21後，以將金屬柱21埋設在晶圓11的正面11a側之方式利用密封材23進行密封。An element wafer (hereinafter simply referred to as a wafer) 11 is prepared by grinding the back surface 11b in advance and thinning it to a predetermined thickness (about 100 to 200 μm). As shown in FIG. 2, an electrode 17 is formed in the element 15 The plurality of metal pillars 21 electrically connected are sealed with a sealing material 23 so that the metal pillars 21 are buried on the front surface 11 a side of the wafer 11.

作為密封材23，包含以質量%表示的10.3%的環氧樹脂或環氧樹脂＋酚樹脂、8.53%的二氧化矽填充料、0.1~0.2%的炭黑，以及4.2~4.3%的其他成分之組成。作為其他成分，舉例而言包含金屬氫氧化物、三氧化二銻、二氧化矽等。As the sealing material 23, 10.3% of epoxy resin or epoxy resin + phenol resin, 8.53% of silica filler, 0.1 to 0.2% of carbon black, and 4.2 to 4.3% of other components are included as mass%. Of the composition. Examples of other components include metal hydroxides, antimony trioxide, and silicon dioxide.

以如此組成的密封材23被覆晶圓11的正面11a並密封晶圓11的正面11a，則因為密封材23中含有極少量的炭黑而使密封材23變為黑色，一般難以通過密封材23看見晶圓11的正面11a。When the front surface 11a of the wafer 11 is covered with the sealing material 23 thus composed and the front surface 11a of the wafer 11 is sealed, the sealing material 23 becomes black because the sealing material 23 contains a small amount of carbon black, and it is generally difficult to pass through the sealing material 23 The front side 11a of the wafer 11 is seen.

在此密封材23中混入炭黑的原因，主要為了防止元件15的靜電破壞，現在市面並未販售不含有炭黑的密封材。The reason why carbon black is mixed in the sealing material 23 is mainly to prevent the electrostatic destruction of the element 15. Currently, no sealing material containing carbon black is not sold on the market.

作為其他的實施方式，在元件晶圓11的正面11a上形成重佈層後，在重佈層上亦可形成對元件15中的電極17電性連接的金屬柱21。As another embodiment, after a redistribution layer is formed on the front surface 11 a of the element wafer 11, a metal pillar 21 electrically connected to the electrode 17 in the element 15 may be formed on the redistribution layer.

接著，使用具有由單晶鑽石所組成的位元切割工具並稱之為平面切割裝置（鉋平機）或磨床（grinder）的研削裝置薄化密封材23。薄化密封材23後，例如藉由電漿蝕刻使金屬柱21的端面露出。Next, the sealing material 23 is thinned using a grinding device having a bit cutting tool composed of a single crystal diamond and called a plane cutting device (planer) or a grinder. After the sealing material 23 is thinned, the end face of the metal pillar 21 is exposed by, for example, plasma etching.

接著，在露出的金屬柱21的端面藉由周知的方法形成焊料等金屬凸塊25，並完成WL-CSP晶圓27。在本實施方式的WL-CSP晶圓27中，密封材23的厚度為100µm程度。Next, a metal bump 25 such as solder is formed on the end surface of the exposed metal pillar 21 by a known method, and the WL-CSP wafer 27 is completed. In the WL-CSP wafer 27 of this embodiment, the thickness of the sealing material 23 is approximately 100 μm.

以雷射加工裝置切割WL-CSP晶圓27時，如圖3所示，較佳為WL-CSP晶圓27的外周部黏貼有黏貼於環狀框架F之作為黏著膠膜的切割膠膜T。藉此，WL-CSP晶圓27透過切割膠膜T成為支撐於環狀框架F的狀態。When the WL-CSP wafer 27 is cut by a laser processing apparatus, as shown in FIG. 3, it is preferable that the outer peripheral portion of the WL-CSP wafer 27 is adhered with a dicing adhesive film T as an adhesive film adhered to the ring frame F. . Thereby, the WL-CSP wafer 27 is in a state of being supported by the ring frame F through the dicing adhesive film T.

但是，以雷射加工裝製切割WL-CSP晶圓27時，亦可不使用環狀框架F，利用在WL-CSP晶圓27的背面黏貼黏著膠膜的方式。However, when the WL-CSP wafer 27 is cut by laser processing, the ring frame F may not be used, and an adhesive film may be adhered to the back of the WL-CSP wafer 27.

在本發明的晶圓加工方法中，首先，從WL-CSP晶圓27的正面側藉由可見光攝像手段通過密封材23對元件晶圓11的正面11a攝像，並檢測在元件晶圓11的正面上形成的至少2個的目標圖案等的對準標記，基於這些對準標記檢測應進行切割的分割預定線13並實施對準步驟。In the wafer processing method of the present invention, first, the front surface 11a of the element wafer 11 is imaged by the sealing material 23 from the front side of the WL-CSP wafer 27 by a visible light imaging means, and the front surface of the element wafer 11 is detected. Alignment marks such as at least two target patterns formed thereon are detected based on these alignment marks, and a predetermined division line 13 to be cut is performed, and an alignment step is performed.

關於該對準步驟，參閱圖4進行詳細說明。在實施對準步驟前，晶圓11的背面11b側黏貼外周部裝設於環狀框架F的切割膠膜T。This alignment step will be described in detail with reference to FIG. 4. Before the alignment step is performed, the dicing adhesive film T attached to the annular frame F is attached to the outer surface of the back surface 11b of the wafer 11.

在對準步驟中，如圖4所示，透過切割膠膜T在雷射加工裝置的卡盤台10吸引保持WL-CSP晶圓27，且使密封元件晶圓11的正面11a的密封材23在上方露出。並且，以夾具12夾住固定環狀框架F。In the alignment step, as shown in FIG. 4, the WL-CSP wafer 27 is attracted and held by the chuck table 10 of the laser processing apparatus through the dicing film T, and the sealing material 23 that seals the front surface 11 a of the element wafer 11 is held. Exposed above. Then, the ring frame F is clamped and fixed by the jig 12.

在對準步驟中，以可見光攝像單元26的CCD等的攝像元件對WL-CPS晶圓27的正面攝像。但是，因在密封材23中包含二氧化矽填充料、炭黑等的成分，進一步在密封材23的正面有凹凸，因此即使以可見光攝像單元26的垂直照明穿透密封材23對元件晶圓11的正面11a進行攝像，攝像影像仍為失焦，難以檢測目標圖案等的對準標記。In the alignment step, the front surface of the WL-CPS wafer 27 is imaged by an imaging element such as a CCD of the visible light imaging unit 26. However, since the sealing material 23 contains components such as a silicon dioxide filler and carbon black, and further has unevenness on the front surface of the sealing material 23, even if the vertical illumination of the visible light imaging unit 26 penetrates the sealing material 23 to the element wafer The front surface 11a of 11 is captured, and the captured image is still out of focus, making it difficult to detect alignment marks such as a target pattern.

因此，在本實施方式的對準步驟中，對可見光攝像單元26的垂直照明加上照射從斜光手段28在攝像區域中斜向來的光，改善攝像影像的失焦，並能檢測對準標記。Therefore, in the alignment step of the present embodiment, the vertical illumination of the visible light imaging unit 26 is irradiated with the light obliquely coming from the oblique light means 28 in the imaging area to improve the out-of-focus of the captured image and to detect the alignment mark.

從斜光手段28照射的光較佳為白色光，對WL-CSP晶圓27的正面的入射角範圍為30°～60°較佳。較佳為，可見光攝像單元14具備能調整曝光時間等的曝光器。The light irradiated from the oblique light means 28 is preferably white light, and the incident angle range to the front surface of the WL-CSP wafer 27 is preferably 30 ° to 60 °. Preferably, the visible light imaging unit 14 includes an exposure device capable of adjusting the exposure time and the like.

接著，以使連結這些對準標記的直線與加工進給方向平行的方式對卡盤台10進行θ旋轉，並進一步藉由將圖5（A）所示的卡盤台10在與加工進給方向X1正交的方向上僅移動對準標記與分割預定線13的中心之距離，檢測應進行雷射加工的分割預定線13。Next, the chuck table 10 is θ-rotated so that the straight line connecting these alignment marks is parallel to the processing feed direction, and the chuck table 10 shown in FIG. 5 (A) is further processed with the processing feed. In the direction orthogonal to the direction X1, only the distance between the alignment mark and the center of the planned division line 13 is moved, and the planned division line 13 to be subjected to laser processing is detected.

實施了對準步驟後，如圖5（A）所示，實施改質層形成步驟，即從WL-CSP晶圓27的正面側沿著分割預定線13，從雷射加工裝置的雷射頭（聚光器）16將對元件晶圓11及密封材23具有穿透性的波長（例如1064nm）之雷射光束LB的該聚光點定位於元件晶圓11的內部及密封材23的內部，藉由卡盤台10在箭頭X1方向或箭頭X2方向上加工進給，在元件晶圓的內部及密封材23的內部形成改質層29（29a，29b）。After the alignment step is performed, as shown in FIG. 5 (A), a modified layer forming step is performed, that is, from the front side of the WL-CSP wafer 27 along the predetermined division line 13 and from the laser head of the laser processing apparatus (Concentrator) 16 Positions the condensing point of the laser beam LB having a wavelength (for example, 1064 nm) having a penetrating power to the element wafer 11 and the sealing material 23 inside the element wafer 11 and the inside of the sealing material 23 By processing and feeding in the direction of arrow X1 or arrow X2 by the chuck table 10, a modified layer 29 (29a, 29b) is formed inside the element wafer and inside the sealing material 23.

在改質層形成步驟中，首先，如圖5（B）所示，將雷射光束LB的聚光點定位於元件晶圓11的內部，並藉由卡盤台10在箭頭X1方向上加工進給，在元件晶圓11的內部形成聚光點29a。In the modified layer forming step, first, as shown in FIG. 5 (B), the light-condensing point of the laser beam LB is positioned inside the element wafer 11 and processed by the chuck table 10 in the direction of the arrow X1. The feed spot forms a light collecting spot 29 a inside the element wafer 11.

接著，如圖5（C）所示，將雷射光束LB的聚光點定位於密封材23的內部，並藉由將卡盤台10在箭頭X2方向上加工進給，在密封材23的內部形成聚光點29b。Next, as shown in FIG. 5 (C), the condensing point of the laser beam LB is positioned inside the sealing material 23, and the chuck table 10 is processed and fed in the direction of the arrow X2. Condensing spots 29b are formed inside.

沿著在第1方向伸長的分割預定線13在去程及返程間多次實施該改質層形成步驟後，90°旋轉卡盤台10，並沿著在正交於第1方向的第2方向上伸長的分割預定線13在去程及返程間多次實施該改質層形成步驟。After the modified layer forming step is repeatedly performed between the return journey and the return route 13 along the planned division line 13 extending in the first direction, the chuck table 10 is rotated 90 °, and along the second orthogonal to the first direction The predetermined dividing line 13 that is elongated in the direction is repeatedly subjected to this modified layer formation step between the outbound and return journeys.

實施了改質層形成步驟後，使用圖6所示的分割裝置50對WL-CSP晶圓27施加外力，並實施分割步驟，將WL-CSP晶圓27分割為一個個的元件晶片31。After the modified layer forming step is performed, an external force is applied to the WL-CSP wafer 27 using the dividing device 50 shown in FIG. 6, and the dividing step is performed to divide the WL-CSP wafer 27 into individual element wafers 31.

如圖7所示的分割裝置50，具備：框架保持手段52，保持環狀框架F；以及膠膜擴張手段54，擴張在框架保持手段52中保持的環狀框架F上裝設的切割膠膜T。The dividing device 50 shown in FIG. 7 includes: a frame holding means 52 that holds the ring frame F; and a film expansion means 54 that expands a dicing film attached to the ring frame F held by the frame holding means 52. T.

框架保持手段52由環狀的框架保持構件56，以及作為配設於框架保持構件56的外周的固定手段之多個夾具58而構成。框架保持構件56的上表面形成載置環狀框架F的載置面56a，在該載置面56a上載置環狀框架F。The frame holding means 52 includes an annular frame holding member 56 and a plurality of clamps 58 as fixing means arranged on the outer periphery of the frame holding member 56. The upper surface of the frame holding member 56 forms a mounting surface 56 a on which the ring-shaped frame F is placed, and the ring-shaped frame F is placed on the mounting surface 56 a.

此外，載置面56a上載置的環狀框架F是藉由夾具58而固定於框架保持手段56。如此構成的框架保持手段52是藉由膠膜擴張手段54支撐而能在上下方向移動。The ring frame F mounted on the mounting surface 56 a is fixed to the frame holding means 56 by a clamp 58. The frame holding means 52 configured as described above is supported by the film expansion means 54 and is movable in the vertical direction.

膠膜擴張手段54具備擴張鼓輪60，其配設於環狀的框架保持構件56的內側。擴張鼓輪60的上端以蓋62閉鎖。該擴張鼓輪60具有，比環狀框架F的內徑小，且比裝設於環狀框架F的切割膠膜T上所黏貼的WL-CSP晶圓27的外徑大的內徑。The film expansion means 54 includes an expansion drum 60 that is disposed inside the ring-shaped frame holding member 56. The upper end of the expansion drum 60 is closed with a cover 62. This expansion drum 60 has an inner diameter smaller than the inner diameter of the ring frame F and larger than the outer diameter of the WL-CSP wafer 27 adhered to the dicing film T mounted on the ring frame F.

擴張鼓輪60具有在其下端一體形成的支撐凸緣64。膠膜擴張手段54進一步具備驅動手段66，其在上下方向移動環狀的框架保持構件56。該驅動手段66由在支撐凸緣64上配設的多個的汽缸68所構成，該活塞桿70連結框架保持構件56的下表面。The expansion drum 60 has a support flange 64 integrally formed at a lower end thereof. The film expansion means 54 further includes a driving means 66 that moves the ring-shaped frame holding member 56 in the vertical direction. The driving means 66 includes a plurality of cylinders 68 provided on the support flange 64, and the piston rod 70 connects the lower surface of the frame holding member 56.

由多個汽缸68所構成的驅動手段66，在基準位置與擴張位置之間往上下方向移動，其中該基準位置是將環狀的框架保持構件56在該載置面56a與擴張輪鼓60的上端的蓋62的表面大致同一高度的位置，該擴張位置是從擴張輪鼓60的上端至預定量下方的位置。The driving means 66 composed of a plurality of cylinders 68 moves up and down between a reference position and an expansion position, where the reference frame position holds the ring-shaped frame holding member 56 on the mounting surface 56a and the expansion drum 60. The position of the surface of the upper end cover 62 at substantially the same height is a position from the upper end of the expansion drum 60 to a position below a predetermined amount.

參閱圖7說明關於使用如以上之方式構成的分割裝置50實施的WL-CSP晶圓27的分割步驟。如圖7（A）所示，將透過切割膠膜T支撐WL-CSP晶圓27之環狀框架F載置於框架保持構件56的載置面56a上，並由夾具58固定於框架保持構件56。此時，框架保持構件56定位於該載置面56a與擴張輪鼓60的上端大致同一高度的基準位置。The division process of the WL-CSP wafer 27 performed using the division device 50 configured as described above will be described with reference to FIG. 7. As shown in FIG. 7 (A), the ring frame F supporting the WL-CSP wafer 27 through the dicing adhesive film T is placed on the mounting surface 56a of the frame holding member 56 and fixed to the frame holding member by a clamp 58 56. At this time, the frame holding member 56 is positioned at a reference position at which the mounting surface 56 a and the upper end of the expansion drum 60 are approximately the same height.

接著，驅動汽缸68下降框架保持構件56至如圖7（B）所示的擴張位置。藉此，因被固定在框架保持構件56的載置面56a上的環狀框架F下降，故裝設在環狀框架F上的切割膠膜T抵接擴張輪鼓60的上端緣而主要在半徑方向上擴張。Next, the cylinder 68 is driven to lower the frame holding member 56 to the expanded position as shown in FIG. 7 (B). As a result, the annular frame F fixed on the mounting surface 56 a of the frame holding member 56 is lowered, so that the cutting adhesive film T installed on the annular frame F abuts the upper end edge of the expansion drum 60 and mainly Expansion in the radial direction.

此種結果，在黏貼於切割膠膜T的WL-CSP晶圓27上作用放射狀拉力。如此在WL-CSP晶圓27上作用放射狀拉力，則沿著分割預定線13在元件晶圓11中形成的改質層29a及在密封材23中形成的改質層29b成為分割起點，使WL-CSP晶圓27沿著分割預定線13如圖8的擴大剖面圖所示被割斷，分割為正面由密封材23密封的一個個的元件晶片31。As a result, a radial tensile force acts on the WL-CSP wafer 27 adhered to the dicing film T. In this way, a radial tensile force is applied to the WL-CSP wafer 27, and the modified layer 29a formed in the element wafer 11 and the modified layer 29b formed in the sealing material 23 along the planned division line 13 become the starting point of division, so that The WL-CSP wafer 27 is cut along the planned division line 13 as shown in the enlarged sectional view of FIG. 8, and is divided into individual element wafers 31 whose front surfaces are sealed by a sealing material 23.

11‧‧‧元件晶圓11‧‧‧component wafer

13‧‧‧分割預定線13‧‧‧ divided scheduled line

15‧‧‧元件15‧‧‧ components

16‧‧‧雷射頭（聚光器）16‧‧‧laser (concentrator)

21‧‧‧金屬柱21‧‧‧metal pillar

23‧‧‧密封材23‧‧‧sealing material

25‧‧‧凸塊25‧‧‧ bump

26‧‧‧可見光攝像手段（可見光攝像單元）26‧‧‧Visible light camera means (visible light camera unit)

27‧‧‧WL-CSP晶圓27‧‧‧WL-CSP Wafer

28‧‧‧斜光手段28‧‧‧ oblique light means

29，29A，29b‧‧‧改質層29, 29A, 29b ‧ ‧ ‧ reforming layer

31‧‧‧元件晶片31‧‧‧component chip

50‧‧‧分割裝置50‧‧‧ split device

圖1（A）係WL-CSP晶圓的分解立體圖，圖1（B）係WL-CSP晶圓的立體圖。 圖2係WL-CSP晶圓的放大剖面圖。 圖3係表示WL-CSP晶圓的外周部黏貼裝設於環狀框架的切割膠膜的樣子的立體圖。 圖4係表示對準步驟的剖面圖。 圖5（A）係表示改質層形成步驟的剖面圖，圖5（B）係在元件晶圓的內部定位聚光點的狀態的WL-CSP晶圓的局部放大剖面圖，圖5（C）係在密封材的內部定位聚光點的狀態的WL-CSP晶圓的局部放大剖面圖。。 圖6係分割裝置的立體圖。 圖7係表示分割步驟的剖面圖。 圖8係實施分割步驟後的WL-CSP晶圓的局部放大剖面圖。FIG. 1 (A) is an exploded perspective view of a WL-CSP wafer, and FIG. 1 (B) is a perspective view of a WL-CSP wafer. FIG. 2 is an enlarged sectional view of a WL-CSP wafer. 3 is a perspective view showing a state in which a dicing adhesive film provided on a ring frame is adhered to the outer peripheral portion of the WL-CSP wafer. Fig. 4 is a sectional view showing an alignment step. FIG. 5 (A) is a cross-sectional view showing a step of forming a modified layer, FIG. 5 (B) is a partially enlarged cross-sectional view of a WL-CSP wafer in a state where a light-condensing point is positioned inside an element wafer, and FIG. 5 (C) ) A partially enlarged cross-sectional view of a WL-CSP wafer in a state where a light collecting point is positioned inside a sealing material. . Fig. 6 is a perspective view of a dividing device. Fig. 7 is a cross-sectional view showing a division step. FIG. 8 is a partially enlarged cross-sectional view of the WL-CSP wafer after the singulation step is performed.

Claims (1)

一種晶圓加工方法，以密封材密封元件晶圓的正面，在該密封材的該晶片區域上分別形成多個凸塊，該元件晶圓藉由在正面交叉形成的多條分割預定線劃分的晶片區域上分別形成元件而成，該晶圓加工方法的特徵在於具備： 對準步驟，從該晶圓的正面側藉由可見光攝像手段穿透該密封材，對該元件晶圓的正面側攝像並檢測對準標記，且基於該對準標記檢測應進行雷射加工的該分割預定線； 改質層形成步驟，在實施了該對準步驟後，將對該元件晶圓及該密封材具有穿透性的波長之雷射光束的聚光點定位於該元件晶圓及該密封材的內部，從該晶圓的正面側沿著該分割預定線照射雷射光束，在該元件晶圓及該密封材的內部形成改質層；以及 分割步驟，在實施了該改質層形成步驟後，對該元件晶圓及該密封材施加外力，並以該改質層作為分割起點分割為正面藉由密封材密封的一個個的元件晶片； 該對準步驟係在藉由該可見光攝像手段進行攝像的區域中藉由斜光手段照射斜向來的光並同時實施。A wafer processing method in which a front surface of a component wafer is sealed with a sealing material, and a plurality of bumps are respectively formed on the wafer region of the sealing material. The component wafer is divided by a plurality of predetermined division lines formed on the front surface. The wafer processing method is characterized by comprising: forming an element on a wafer region; an alignment step of penetrating the sealing material from a front side of the wafer by a visible light imaging means, and imaging the front side of the element wafer. An alignment mark is detected, and based on the alignment mark, the predetermined division line for laser processing should be detected; a modified layer forming step, after the alignment step is performed, the element wafer and the sealing material have The focusing point of the penetrating wavelength laser beam is positioned inside the element wafer and the sealing material, and the laser beam is irradiated from the front side of the wafer along the predetermined division line. A reforming layer is formed inside the sealing material; and a slicing step. After the reforming layer forming step is performed, an external force is applied to the element wafer and the sealing material, and the reforming layer is used as a starting point for division. A sealing member sealing face by one of the wafer elements; step based on the alignment of the imaging region by means of the visible light imaging means for irradiating light in an oblique direction inclined by light and simultaneously to the embodiment.
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Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05337668A (en) * 1992-06-09 1993-12-21 Toshiba Corp Laser welding device
JPH06258056A (en) * 1993-03-05 1994-09-16 Tokyo Seimitsu Co Ltd Profile recognition system for semiconductor wafer
JP2002057143A (en) * 2000-08-07 2002-02-22 Hitachi Ltd Floating foreign matter detector
US6724479B2 (en) 2001-09-28 2004-04-20 Infineon Technologies Ag Method for overlay metrology of low contrast features
JP4127614B2 (en) * 2002-01-17 2008-07-30 本田技研工業株式会社 Laser welding apparatus and welding method
JP2006134971A (en) * 2004-11-04 2006-05-25 Disco Abrasive Syst Ltd Laser processing method of wafer
JP5221007B2 (en) * 2006-05-31 2013-06-26 アイシン精機株式会社 Light emitting diode chip and wafer split processing method
JP5828683B2 (en) * 2011-06-07 2015-12-09 株式会社ディスコ Processing equipment
JP5948034B2 (en) 2011-09-27 2016-07-06 株式会社ディスコ Alignment method
KR20130071386A (en) * 2011-12-20 2013-06-28 닛토덴코 가부시키가이샤 Method of dicing substrate and apparatus for dicing substrate using thereof
JP2014003274A (en) * 2012-05-25 2014-01-09 Nitto Denko Corp Method for manufacturing semiconductor device and underfill material
JP2016013557A (en) * 2013-02-13 2016-01-28 住友化学株式会社 Manufacturing apparatus for laser beam irradiation device and optical member adhered body
JP6157890B2 (en) * 2013-03-26 2017-07-05 日東電工株式会社 Underfill material, sealing sheet, and method for manufacturing semiconductor device
KR102215918B1 (en) * 2013-03-27 2021-02-16 하마마츠 포토닉스 가부시키가이샤 Laser machining device and laser machining method
KR102070087B1 (en) * 2013-04-29 2020-01-30 삼성전자주식회사 Method for manufacturing semiconductor device
JP6066854B2 (en) * 2013-07-30 2017-01-25 株式会社ディスコ Wafer processing method
JP6113019B2 (en) * 2013-08-07 2017-04-12 株式会社ディスコ Wafer division method
JP2016015438A (en) * 2014-07-03 2016-01-28 株式会社ディスコ Alignment method
JP6360411B2 (en) * 2014-10-09 2018-07-18 株式会社ディスコ Wafer processing method
JP2016129202A (en) * 2015-01-09 2016-07-14 株式会社ディスコ Wafer processing method
JP6494334B2 (en) * 2015-03-05 2019-04-03 株式会社ディスコ Device chip manufacturing method
JP2016166120A (en) * 2015-03-06 2016-09-15 三星ダイヤモンド工業株式会社 Processing method of laminated substrate, and processing device of laminated substrate by laser beam
JP6339514B2 (en) * 2015-03-25 2018-06-06 Ｔｏｗａ株式会社 Cutting apparatus and cutting method
JP6560040B2 (en) * 2015-07-06 2019-08-14 株式会社ディスコ Wafer processing method
JP2017092129A (en) * 2015-11-05 2017-05-25 株式会社ディスコ Processing method of wafer

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