TW201843778A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201843778A
TW201843778A TW106116429A TW106116429A TW201843778A TW 201843778 A TW201843778 A TW 201843778A TW 106116429 A TW106116429 A TW 106116429A TW 106116429 A TW106116429 A TW 106116429A TW 201843778 A TW201843778 A TW 201843778A
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resin film
electrodes
wiring
semiconductor device
electrode
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TWI659506B (zh
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前田和弘
日坂隆行
久留須整
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日商三菱電機股份有限公司
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Abstract

在半導體基板(1)上，形成具有複數控制電極(2)、複數第1電極(3)、及複數第2電極(4)的多指狀電晶體。樹脂膜(14,15)覆蓋著電晶體。將複數第1電極(3)相互電氣式耦接的第1佈線(8)係形成於樹脂膜(14,15)上。樹脂膜(14,15)係被第1佈線(8)與複數第1電極(3)的接觸部分覆蓋。在複數控制電極(2)與複數第2電極(4)的周圍，形成由樹脂膜(14,15)密封的中空構造(16)。

Description

半導體裝置及其製造方法
本發明係關於形成有經利用樹脂膜密封之中空構造的半導體裝置及其製造方法。
因為由化合物半導體形成的高電子遷移率電晶體(HEMT)，具有優異的高頻特性與低雜訊性，因而應用於微波及毫波的放大器。為能提升HEMT的高頻特性，便必需提升阻斷頻率(fT)與最大動作頻率(fmax)。在使fT及fmax的提升時，增加相互電導、及降低閘極-源極間之靜電容便屬有效手段。
另一方面，有報告指出採用晶圓級封裝技術的HEMT，因為樹脂膜係填充於Y型閘極的屋簷部下方，因而靜電容增加、高頻特性劣化(例如參照非專利文獻1)。為解決此項問題，已知有藉由除去閘極周圍樹脂膜俾防止高頻特性劣化的手段(例如參照專利文獻1~3)。又，有提案：在閘極周圍形成中空構造，且為能盡量抑制電容增加，因而將該中空構造擴大至源極、汲極周圍的電晶體及其製造方法(例如參照專利文獻4、5)。
先前技術文獻 專利文獻
專利文獻1：日本特開平05-335343號公報
專利文獻2：日本特開2015-046445號公報
專利文獻3：日本特開2016-039319號公報
專利文獻4：日本特開2014-209522號公報
專利文獻5：日本特開2009-176930號公報
非專利文獻
非專利文獻1：T. Hisaka1, H. Sasaki1, T. Katoh1, K. Kanaya1, N. Yoshida1, A. A. Villanueva, and J. A. del Alamo, IEICE Electronics Express, Vol.7, No.8, P.558-562
但是，若非電晶體全體均有形成樹脂膜的構造，會有在爾後步驟所使用光阻或無機水溶液等藥物，從樹脂膜與電極間之間隙進入中空構造的問題。又，採用晶圓級封裝技術的半導體裝置，利用樹脂膜覆蓋著電晶體以外的佈線部，導致裝置全體的靜電容增加。結果，會有增益或雜訊特性等高頻特性劣化的問題。
本發明係為解決上述問題而完成，目的在於獲得：防止藥物進入中空構造、降低靜電容，俾能提升高頻特性的半導體裝置及其製造方法。
本發明的半導體裝置，係包括：半導體基板；具有形成於上述半導體基板上的複數控制電極、複數第1電極、 及複數第2電極的多指狀電晶體；覆蓋上述電晶體的樹脂膜；以及形成於上述樹脂膜上，且將上述複數第1電極相互電氣式耦接的第1佈線；其中，上述樹脂膜係覆蓋著上述第1佈線與上述複數第1電極間之接觸部分；在上述複數控制電極及上述複數第2電極的周圍，形成由上述樹脂膜密封的第1中空構造。
本發明係在複數控制電極與複數第2電極的周圍，形成由樹脂膜密封的第1中空構造。依此藉由擴大電晶體的中空構造，相較於僅在控制電極周圍形成中空構造的情況下，能盡可能地降低電晶體的靜電容。藉此，可降低靜電容便能提升高頻特性。又，樹脂膜係覆蓋著第1佈線與複數第1電極的接觸部分。藉此可防止經形成第1中空構造後的步驟所使用光阻或無機水溶液等藥物，進入第1中空構造中。
1‧‧‧半導體基板
2‧‧‧閘極(控制電極)
3‧‧‧源極(第1電極)
4‧‧‧汲極(第2電極)
5‧‧‧閘極佈線(第2佈線)
6‧‧‧閘極墊
7‧‧‧源極佈線
8、27‧‧‧連接佈線(第1佈線)
9‧‧‧源極墊
10‧‧‧汲極佈線
11‧‧‧汲極墊
12、13‧‧‧絕緣膜
14、15‧‧‧樹脂膜
16、17‧‧‧中空構造
18‧‧‧貫穿孔
19‧‧‧下層佈線
20‧‧‧上層佈線
21‧‧‧支柱
22‧‧‧基座電極(控制電極)
23‧‧‧射極(第1電極)
24‧‧‧集電極(第2電極)
圖1係本發明實施形態1的半導體裝置平面圖。
圖2係沿圖1的I-II之剖視圖。
圖3係沿圖1的III-IV之剖視圖。
圖4係本發明實施形態1的半導體裝置之製造步驟剖視圖。
圖5係本發明實施形態1的半導體裝置之製造步驟剖視圖。
圖6係本發明實施形態1的半導體裝置之製造步驟剖視圖。
圖7係本發明實施形態1的半導體裝置之製造步驟剖視圖。
圖8係本發明實施形態1的半導體裝置之製造步驟剖視圖。
圖9係本發明實施形態2的半導體裝置平面圖。
圖10係沿圖9的I-II之剖視圖。
圖11係本發明實施形態3的半導體裝置剖視圖。
圖12係本發明實施形態4的半導體裝置剖視圖。
圖13係本發明實施形態5的半導體裝置剖視圖。
圖14係沿圖13的I-II之剖視圖。
針對本發明實施形態的半導體裝置及其製造方法，參照圖式進行說明。針對相同或對應的構成要件賦予相同元件符號，並有省略重複說明的情況。
實施形態1.
圖1所示係本發明實施形態1的半導體裝置平面圖。圖2所示係沿圖1的I-II之剖視圖。圖3所示係沿圖1的III-IV之剖視圖。在半導體基板1上，形成具有複數閘極2、複數源極3、及複數汲極4的多指狀場效電晶體。閘極2的截面形狀呈T型或Y型。複數閘極2係經由閘極佈線5連接於閘極墊6。複數源極3係經由源極佈線7與連接佈線8，連接於源極墊9。複數汲極4係經由汲極佈線10連接於汲極墊11。
絕緣膜12,13與樹脂膜14,15覆蓋著電晶體。連接佈線8係形成於樹脂膜15上。連接佈線8與源極佈線7係相 互電氣式耦接於複數源極3。樹脂膜14係覆蓋著連接佈線8與複數源極3的接觸部分。在複數閘極2與複數汲極4的周圍，形成由樹脂膜14,15密封的中空構造16。又，在閘線路5與連接佈線8的交叉部分，形成由樹脂膜14,15密封的中空構造17。
樹脂模14,15的厚度係2~20μm。中空構造16,17的高度係1~10μm。中空構造16,17的寬度、深度係數μm~數百μm。中空構造16,17並非晶片全體均有形成，而是依各個電晶體與佈線等迴路要件形成。
接著，針對本實施形態半導體裝置之製造步驟進行說明。圖4~8所示係本發明實施形態1的半導體裝置之製造步驟剖視圖。圖4,6,8係對應於圖2的剖視圖，圖5,7係對應於圖3的剖視圖。
首先，如圖4,5所示，在半導體基板1上形成具有閘極2、源極3、及汲極4的電晶體。此時，亦同時形成閘極佈線5等下層佈線。全面形成絕緣膜12。在爾後步驟會連接電氣佈線的地方，施行絕緣膜12開口。其次，藉由使用旋塗機的塗佈法、或層壓法、或STP(Spin-coating film Transfer and hot-pressing technology)法，全面形成屬於感光性樹脂膜的樹脂膜14。利用曝光與顯影將樹脂膜14施行圖案化，形成覆蓋著源極3，且未覆蓋而是包圍閘極2與汲極4的狀態。藉由依此使用感光性樹脂膜，便可簡單地將樹脂膜14施行圖案化。又，對應於在爾後會成為佈線交叉部分的閘極佈線5上之區域，亦施行樹脂膜14的開口。然後施行硬化處理而使樹脂膜14硬化。
其次，如圖6,7所示，將當作樹脂膜15用的感光性樹脂膜之單頁膜，利用層壓法或STP法接合於樹脂膜14的上面。藉此，在閘極2與汲極4的周圍，形成由樹脂膜14,15密封的中空構造16。同時，同一平面上的閘極佈線5之上方區域亦能形成中空構造17。
其次，如圖8所示，對樹脂膜15施行曝光與顯影，而在源極3等之上形成貫穿孔18。然後，施行硬化處理而使樹脂膜15硬化。另外，樹脂膜15亦可非為非感光性樹脂，此情況在形成貫穿孔18時係採用乾式蝕刻。
其次，利用電鍍或蒸鍍在樹脂膜15上，形成經由貫穿孔18連接於源極3的連接佈線8。電鍍時，形成供電層，並利用光阻施行圖案化後，才施行電解電鍍。然後，除去光阻與供電層。另一方面，蒸鍍法的情況，利用光阻施行圖案化，並利用蒸鍍形成金屬膜，再利用剝脫法除去光阻。最後，利用絕緣膜13覆蓋著樹脂膜14的外側及樹脂膜15的外側。但，接觸所需要的地方施行開口。藉此便製得本實施形態的半導體裝置。
本實施形態係在閘極2與汲極4的周圍，形成由樹脂膜14,15密封的中空構造16。依此藉由擴大電晶體中的中空構造，相較於僅閘極2的周圍才有形成中空構造的情況下，能盡可能地降低電晶體的靜電容。藉此，可降低靜電容，俾能提升高頻特性。
再者，樹脂膜14係覆蓋著連接佈線8與源極3的接觸部分。藉此，如圖6所示，當黏貼樹脂膜15時，中空構 造16被完全密封。所以，可防止在形成中空構造16後的步驟中所使用光阻或無機水溶液等藥物，進入於中空構造16內。
再者，在閘極佈線5與連接佈線8的交叉部分處，形成由樹脂膜14,15密封的中空構造17。依此藉由在佈線間形成中空構造而減小佈線容量，故而可增加特性阻抗。所以，容易獲得阻抗整合，使迴路設計趨於容易。另外，亦可在閘極佈線5與汲極佈線10的交叉部分處形成中空構造17。
實施形態2.
圖9所示係本發明實施形態2的半導體裝置平面圖。圖10所示係沿圖9的I-II之剖視圖。連接佈線8係形成於複數閘極2與複數汲極4的上方、且樹脂膜15上，並將複數源極3相互電氣式耦接。連接佈線8係朝汲極4長邊方向的垂直方向延伸。其他的構成均同實施形態1，此情況亦能獲得與實施形態1同樣的效果。
實施形態3.
圖11所示係本發明實施形態3的半導體裝置剖視圖。在場效電晶體以外的區域形成下層佈線19與上層佈線20。下層佈線19係被樹脂膜14,15覆蓋，而上層佈線20係形成於樹脂膜15上。在下層佈線19與上層佈線20的交叉部分處，形成由樹脂膜14,15密封的中空構造17。依此藉由在佈線間形成中空構造，便可降低佈線容量，所以能增加特性阻抗。故，容易獲取阻抗整合、迴路設計較為容易。其他的構成及效果係同實施形態2。
實施形態4.
圖12所示係本發明實施形態4的半導體裝置剖視圖。在中空構造16,17的內部，形成支撐其上方之樹脂膜15的支柱21。藉此可防止樹脂膜15下垂、防止製程上出現不良情況。相較於實施形態3之下，雖裝置的靜電容有增加，但仍可安定地形成構造，所以生產安定性獲提升。其他的構成及效果係同實施形態3。
實施形態5.
圖13所示係本發明實施形態5的半導體裝置平面圖。圖14所示係沿圖13的I-II之剖視圖。在半導體基板1上，形成具有複數基座電極22、複數射極23、及複數集電極24的多指狀雙載子電晶體。複數基座電極22係經由基座佈線25連接於基座墊26。複數射極23係經由連接佈線27連接於射極墊28。複數集電極24係經由集電極佈線29連接於集電極墊30。
將複數射極23相互電氣式耦接的連接佈線27，係形成於樹脂膜15上。樹脂膜14係覆蓋著連接佈線27與複數射極23的接觸部分。在複數基座電極22與複數集電極24的周圍，形成由樹脂膜14,15密封的中空構造16。即便此種雙載子電晶體的情況，仍可獲得與實施形態1,2同樣的效果。
再者，亦可依照與實施形態3同樣地，在佈線的交叉部分處形成第2中空構造。藉此便可降低佈線容量，故能增加特性阻抗。所以，容易獲取阻抗整合、迴路設計較為容易。

Claims (6)

  1. 一種半導體裝置，係包括：半導體基板；多指狀電晶體，其乃具有形成於上述半導體基板上的複數控制電極、複數第1電極、及複數第2電極；樹脂膜，其乃覆蓋上述電晶體；以及的第1佈線，其乃形成於上述樹脂膜上，且將上述複數第1電極相互電氣式耦接；其中，上述樹脂膜係覆蓋著上述第1佈線與上述複數第1電極間之接觸部分；在上述複數控制電極及上述複數第2電極的周圍，形成由上述樹脂膜密封的第1中空構造。
  2. 如申請專利範圍第1項之半導體裝置，其中，更進一步包括：形成於上述半導體基板上且由上述樹脂膜覆蓋，並將上述複數控制電極相互電氣式耦接的第2佈線；在上述第1佈線與上述第2佈線的交叉部分處，形成由上述樹脂膜密封的第2中空構造。
  3. 如申請專利範圍第1項之半導體裝置，其中，上述第1佈線係形成於上述複數控制電極與上述複數第2電極的上方。
  4. 如申請專利範圍第3項之半導體裝置，其中，包括：下層佈線，其乃由上述樹脂膜覆蓋；以及上層佈線，其乃形成於上述樹脂膜上；在上述下層佈線與上述上層佈線的交叉部分處，形成由上述樹脂膜密封的第2中空構造。
  5. 如申請專利範圍第4項之半導體裝置，其中，在上述第2中空構造的內部，形成支撐著上述樹脂膜的支柱。
  6. 一種半導體裝置之製造方法，係包括：在半導體基板上，形成具有控制電極、第1電極及第2電極的電晶體之步驟；在上述半導體基板上，形成覆蓋上述第1電極，且包圍上述控制電極與上述第2電極的第1樹脂膜之步驟；以及使第2樹脂膜接合於上述第1樹脂膜的上面，在上述控制電極與上述第2電極的周圍，形成由上述第1與第2樹脂膜密封的中空構造之步驟。
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