CN110476231A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN110476231A
CN110476231A CN201780089183.0A CN201780089183A CN110476231A CN 110476231 A CN110476231 A CN 110476231A CN 201780089183 A CN201780089183 A CN 201780089183A CN 110476231 A CN110476231 A CN 110476231A
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resin film
wiring
electrode
electrodes
semiconductor device
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前田和弘
日坂隆行
久留须整
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Mitsubishi Corp
Mitsubishi Electric Corp
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Mitsubishi Corp
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Abstract

在半导体衬底(1)之上形成有多指晶体管，该多指晶体管具有多个控制电极(2)、多个第1电极(3)及多个第2电极(4)。树脂膜(14、15)覆盖晶体管。在树脂膜(14、15)之上形成有将多个第1电极(3)彼此电连接的第1配线(8)。树脂膜(14、15)覆盖第1配线(8)和多个第1电极(3)的接触部分。在多个控制电极(2)及多个第2电极(4)周围形成有由树脂膜(14、15)密闭的中空构造(16)。

Description

半导体装置及其制造方法
技术领域
本发明涉及形成有由树脂膜密闭的中空构造的半导体装置及其制造方法。
背景技术
由于由化合物半导体构成的高电子迁移率晶体管(HEMT)具有优异的高频特性和低噪声性，因此被应用于微米波和毫米波的放大器。为了使HEMT的高频特性提高，需要使截止频率(fT)及最大动作频率(fmax)提高。为了提高fT及fmax，互导的增大及栅极电极-源极电极间的静电电容的降低是有效的手段。
另一方面，报道了下述情况，即，就应用了晶片级封装技术的HEMT而言，由于将树脂膜填充于Y型栅极的檐部之下，因此静电电容增大，高频特性劣化(例如，参照非专利文献1)。为了解决该课题，作为用于防止高频特性的劣化的手段而已知去除栅极电极周围的树脂膜(例如，参照专利文献1～3)。另外，除了在栅极电极周围形成中空构造之外，为了尽可能对电容的增加进行抑制，提出了将该中空构造扩展至源极、漏极电极周围的晶体管及其制造方法(例如，参照专利文献4、5)。
专利文献1：日本特开平05-335343号公报
专利文献2：日本特开2015-046445号公报
专利文献3：日本特开2016-039319号公报
专利文献4：日本特开2014-209522号公报
专利文献5：日本特开2009-176930号公报
非专利文献1：T.Hisaka1,H.Sasaki1,T.Katoh1,K.Kanaya1,N.Yoshida1,A.A.Villanueva,and J.A.del Alamo,IEICE Electronics Express,Vol.7,No.8,P.558-562
发明内容
但是，在树脂膜并未形成于整个晶体管的构造中，存在下述问题，即，在之后的工序中使用的抗蚀剂或无机水溶液等药品从树脂膜和电极之间的间隙进入中空构造。另外，就应用了晶片级封装技术的半导体装置而言，晶体管之外的配线部被树脂膜覆盖，装置整体的静电电容增加。其结果，存在增益或噪音特性等高频特性劣化这样的问题。
本发明就是为了解决上述那样的课题而提出的，其目的在于得到能够防止药品进入中空构造，使静电电容减小而使高频特性提高的半导体装置及其制造方法。
本发明涉及的半导体装置的特征在于，具备：半导体衬底；多指的晶体管，其形成于所述半导体衬底之上，具有多个控制电极、多个第1电极及多个第2电极；树脂膜，其覆盖所述晶体管；以及第1配线，其形成于所述树脂膜之上，将所述多个第1电极彼此电连接，所述树脂膜覆盖所述第1配线和所述多个第1电极的接触部分，在所述多个控制电极及所述多个第2电极周围形成有由所述树脂膜密闭的第1中空构造。
发明的效果
在本发明中，在多个控制电极及多个第2电极周围形成有由树脂膜密闭的第1中空构造。这样，通过扩展晶体管的中空构造，从而与仅在控制电极周围形成了中空构造的情况相比能够尽可能地减小晶体管的静电电容。由此，能够使静电电容减小而使高频特性提高。另外，树脂膜覆盖第1配线和多个第1电极的接触部分。由此，能够防止在形成了第1中空构造后的工序中使用的抗蚀剂或无机水溶液等药品进入第1中空构造。
附图说明
图1是表示本发明的实施方式1涉及的半导体装置的俯视图。
图2是沿图1的I-II的剖视图。
图3是沿图1的III-IV的剖视图。
图4是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图5是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图6是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图7是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图8是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图9是表示本发明的实施方式2涉及的半导体装置的俯视图。
图10是沿图9的I-II的剖视图。
图11是表示本发明的实施方式3涉及的半导体装置的剖视图。
图12是表示本发明的实施方式4涉及的半导体装置的剖视图。
图13是表示本发明的实施方式5涉及的半导体装置的俯视图。
图14是沿图13的I-II的剖视图。
具体实施方式
参照附图对本发明的实施方式涉及的半导体装置及其制造方法进行说明。对相同或对应的结构要素标注相同标号，有时省略重复说明。
实施方式1.
图1是表示本发明的实施方式1涉及的半导体装置的俯视图。图2是沿图1的I-II的剖视图。图3是沿图1的III-IV的剖视图。在半导体衬底1之上形成有多指(Multi finger)场效应晶体管，该多指场效应晶体管具有多个栅极电极2、多个源极电极3及多个漏极电极4。栅极电极2的剖面形状为T型或Y型。多个栅极电极2经由栅极配线5与栅极焊盘6连接。多个源极电极3经由源极配线7及连接配线8与源极焊盘9连接。多个漏极电极4经由漏极配线10与漏极焊盘11连接。
绝缘膜12、13及树脂膜14、15覆盖晶体管。连接配线8形成于树脂膜15之上。连接配线8及源极配线7将多个源极电极3彼此电连接。树脂膜14覆盖连接配线8和多个源极电极3的接触部分。在多个栅极电极2及多个漏极电极4周围形成有由树脂膜14、15密闭的中空构造16。另外，在栅极配线5和连接配线8的交叉部分形成有由树脂膜14、15密闭的中空构造17。
树脂膜14、15的厚度为2～20μm。中空构造16、17的高度为1～10μm。中空构造16、17的宽度、纵深为几μm～几百μm。中空构造16、17并非是形成于芯片整体，而是针对晶体管及配线这样的每个电路要素而形成的。
接着，对本实施方式涉及的半导体装置的制造工序进行说明。图4～8是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。图4、6、8与图2的剖视图对应，图5、7与图3的剖视图对应。
首先，如图4、5所示，在半导体衬底1之上形成晶体管，该晶体管具有栅极电极2、源极电极3及漏极电极4。此时，也同时形成栅极配线5等下层配线。在整面形成绝缘膜12。在之后的工序中使绝缘膜12在连接电配线的位置进行开口。接着，通过使用了旋涂机的涂敷法或层压法或STP(Spin-coating film Transfer and hot-Pressing technology)法在整面形成感光性树脂膜即树脂膜14。通过曝光和显影而将树脂膜14图案化，覆盖源极电极3，并且不覆盖而是包围栅极电极2及漏极电极4。这样，通过使用感光性树脂膜，从而能够简单地将树脂膜14图案化。另外，之后在成为配线的交叉部分的位于栅极配线5之上的区域也使树脂膜14开口。之后，进行固化处理而使树脂膜14固化。
接着，如图6、7所示，通过层压法或STP法使感光性树脂膜的薄膜作为树脂膜15接合于树脂膜14的上表面。由此，在栅极电极2及漏极电极4周围形成由树脂膜14、15密闭的中空构造16。同时，能够在处于同一平面之上的栅极配线5的上方区域也形成中空构造17。
接着，如图8所示，对树脂膜15进行曝光和显影，在源极电极3等之上形成通孔18。之后，进行固化处理而使树脂膜15固化。此外，树脂膜15也可以为非感光性树脂，在该情况下，在形成通孔18时使用干蚀刻。
接着，通过镀敷或蒸镀在树脂膜15之上形成经由通孔18与源极电极3连接的连接配线8。在镀敷的情况下，在对供电层进行成膜，通过抗蚀剂进行了图案化后，进行电镀。之后，去除抗蚀剂及供电层。另一方面，在蒸镀法的情况下，通过抗蚀剂进行图案化，通过蒸镀对金属膜进行成膜，通过剥离法去除抗蚀剂。最后，通过绝缘膜13覆盖树脂膜14的外侧及树脂膜15的外侧。其中，接触所需要的位置进行开口。由此，制造出本实施方式涉及的半导体装置。
在本实施方式中，在栅极电极2及漏极电极4周围形成有由树脂膜14、15密闭的中空构造16。这样，通过扩展晶体管的中空构造，从而与仅在栅极电极2周围形成了中空构造的情况相比能够尽可能地减小晶体管的静电电容。由此，能够减小静电电容而使高频特性提高。
另外，树脂膜14覆盖连接配线8和源极电极3的接触部分。由此，在如图6所示粘贴了树脂膜15时中空构造16被完全密闭。因此，能够防止在形成了中空构造16后的工序中使用的抗蚀剂或无机水溶液等药品进入中空构造16。
另外，在栅极配线5和连接配线8的交叉部分形成有由树脂膜14、15密闭的中空构造17。这样，通过在配线间形成中空构造而减小配线电容，因此能够增大特性阻抗。因此，阻抗匹配变得容易，电路设计变得容易。此外，也可以在栅极配线5和漏极配线10的交叉部分形成中空构造17。
实施方式2.
图9是表示本发明的实施方式2涉及的半导体装置的俯视图。图10是沿图9的I-II的剖视图。连接配线8位于多个栅极电极2及多个漏极电极4的上方，形成于树脂膜15之上，将多个源极电极3彼此电连接。连接配线8在相对于漏极电极4的长度方向垂直的方向延伸。其它结构与实施方式1相同，在该情况下也能够得到与实施方式1相同的效果。
实施方式3.
图11是表示本发明的实施方式3涉及的半导体装置的剖视图。在场效应晶体管之外的区域形成有下层配线19及上层配线20。下层配线19被树脂膜14、15覆盖，上层配线20形成于树脂膜15之上。在下层配线19和上层配线20的交叉部分形成有由树脂膜14、15密闭的中空构造17。这样，通过在配线间形成中空构造而减小配线电容，因此能够增大特性阻抗。因此，阻抗匹配变得容易，电路设计变得容易。其它的结构及效果与实施方式2相同。
实施方式4.
图12是表示本发明的实施方式4涉及的半导体装置的剖视图。在中空构造16、17的内部，形成有对其上部的树脂膜15进行支撑的支撑柱21。由此，能够防止树脂膜15下垂，防止工艺上的不良情况。与实施方式3相比器件的静电电容增加，但由于能够稳定地形成构造，因此生产稳定性提高。其它的结构及效果与实施方式3相同。
实施方式5.
图13是表示本发明的实施方式5涉及的半导体装置的俯视图。图14是沿图13的I-II的剖视图。在半导体衬底1之上形成有多指双极晶体管，该多指双极晶体管具有多个基极电极22、多个发射极电极23及多个集电极(collector)电极(electrode)24。多个基极电极22经由基极配线25与基极焊盘26连接。多个发射极电极23经由连接配线27与发射极焊盘28连接。多个集电极电极24经由集电极配线29与集电极焊盘30连接。
在树脂膜15之上形成有将多个发射极电极23彼此电连接的连接配线27。树脂膜14覆盖连接配线27和多个发射极电极23的接触部分。在多个基极电极22及多个集电极电极24周围形成有由树脂膜14、15密闭的中空构造16。在这样的双极晶体管的情况下也能够得到与实施方式1、2相同的效果。
另外，也可以与实施方式3相同地在配线的交叉部分形成第2中空构造。由此，配线电容变小，因此能够增大特性阻抗。因此，阻抗匹配变得容易，电路设计变得容易。
标号的说明
1半导体衬底，2栅极电极(控制电极)，3源极电极(第1电极)，4漏极电极(第2电极)，5栅极配线(第2配线)，8、27连接配线(第1配线)，14、15树脂膜，16、17中空构造，19下层配线，20上层配线，21支撑柱，22基极电极(控制电极)，23发射极电极(第1电极)，24集电极电极(第2电极)。

Claims (6)

1.一种半导体装置，其特征在于，具备：
半导体衬底；
多指的晶体管，其形成于所述半导体衬底之上，具有多个控制电极、多个第1电极及多个第2电极；
树脂膜，其覆盖所述晶体管；以及
第1配线，其形成于所述树脂膜之上，将所述多个第1电极彼此电连接，
所述树脂膜覆盖所述第1配线和所述多个第1电极的接触部分，
在所述多个控制电极及所述多个第2电极周围形成有由所述树脂膜密闭的第1中空构造。
2.根据权利要求1所述的半导体装置，其特征在于，
还具备第2配线，该第2配线形成于所述半导体衬底之上且由所述树脂膜覆盖，将所述多个控制电极彼此电连接，
在所述第1配线和所述第2配线的交叉部分形成有由所述树脂膜密闭的第2中空构造。
3.根据权利要求1所述的半导体装置，其特征在于，
所述第1配线形成于所述多个控制电极及所述多个第2电极的上方。
4.根据权利要求3所述的半导体装置，其特征在于，具备：
下层配线，其由所述树脂膜覆盖；以及
上层配线，其形成于所述树脂膜之上，
在所述下层配线和所述上层配线的交叉部分形成有由所述树脂膜密闭的第2中空构造。
5.根据权利要求4所述的半导体装置，其特征在于，
在所述第2中空构造的内部形成有对所述树脂膜进行支撑的支撑柱。
6.一种半导体装置的制造方法，其特征在于，具备下述工序：
在半导体衬底之上形成晶体管，该晶体管具有控制电极、第1电极及第2电极；
在所述半导体衬底之上，形成覆盖所述第1电极并且包围所述控制电极及所述第2电极的第1树脂膜；以及
使第2树脂膜与所述第1树脂膜的上表面接合而在所述控制电极及所述第2电极周围形成由所述第1及第2树脂膜密闭的中空构造。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111710715A (zh) * 2020-05-14 2020-09-25 西安电子科技大学 具有空气腔的氮化镓微波毫米波晶体管结构及制备方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11302609B2 (en) 2020-08-31 2022-04-12 Nxp Usa, Inc. Radio frequency power dies having flip-chip architectures and power amplifier modules containing the same
TWI751008B (zh) * 2021-01-27 2021-12-21 鴻鎵科技股份有限公司 雙電晶體的封裝結構
FR3121544B1 (fr) * 2021-03-31 2023-11-24 St Microelectronics Crolles 2 Sas Structure d'isolation thermique et électrique
US20230299172A1 (en) * 2022-03-17 2023-09-21 Analog Devices, Inc. Sealed cavity embedded in a semiconductor wafer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102969289A (zh) * 2011-09-01 2013-03-13 三菱电机株式会社 半导体装置及其制造方法
CN105374743A (zh) * 2014-08-08 2016-03-02 三菱电机株式会社 半导体装置的制造方法
CN106098757A (zh) * 2015-04-30 2016-11-09 三菱电机株式会社 场效应晶体管

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6195536A (ja) * 1984-10-16 1986-05-14 Sanken Electric Co Ltd 樹脂封止型半導体装置の製造方法
US5408742A (en) * 1991-10-28 1995-04-25 Martin Marietta Corporation Process for making air bridges for integrated circuits
JPH05335343A (ja) 1992-05-27 1993-12-17 Sony Corp 電界効果トランジスタ
DE19522364C1 (de) * 1995-06-20 1996-07-04 Siemens Ag Halbleiter-Bauelement
US5659267A (en) * 1995-11-03 1997-08-19 Motorola, Inc. High gain K-band power amplifier with unconditionally stable MMIC FET cells
US5789791A (en) * 1996-08-27 1998-08-04 National Semiconductor Corporation Multi-finger MOS transistor with reduced gate resistance
KR20020035841A (ko) * 1999-07-28 2002-05-15 가나이 쓰토무 반도체장치
JP3600544B2 (ja) * 2001-03-30 2004-12-15 ユーディナデバイス株式会社 半導体装置の製造方法
US6724067B2 (en) * 2001-04-13 2004-04-20 Anadigics, Inc. Low stress thermal and electrical interconnects for heterojunction bipolar transistors
JP2003332508A (ja) * 2002-05-16 2003-11-21 Renesas Technology Corp 半導体装置及びその製造方法
TWI288443B (en) * 2002-05-17 2007-10-11 Semiconductor Energy Lab SiN film, semiconductor device, and the manufacturing method thereof
JP4284639B2 (ja) 2002-08-29 2009-06-24 富士通株式会社 半導体装置の製造方法
JP4489485B2 (ja) * 2004-03-31 2010-06-23 株式会社ルネサステクノロジ 半導体装置
JP5343301B2 (ja) * 2005-11-28 2013-11-13 三菱電機株式会社 半導体装置およびその製造方法
US8193526B2 (en) * 2007-08-07 2012-06-05 Panasonic Corporation Transistor having an organic semiconductor with a hollow space
JP2009176930A (ja) 2008-01-24 2009-08-06 Toshiba Corp 半導体装置およびその製造方法
US8907473B2 (en) * 2009-02-02 2014-12-09 Estivation Properties Llc Semiconductor device having a diamond substrate heat spreader
JP5269045B2 (ja) * 2010-11-26 2013-08-21 株式会社東芝 電力増幅装置及び連結電力増幅装置
JP5733616B2 (ja) * 2011-04-21 2015-06-10 住友電工デバイス・イノベーション株式会社 半導体装置
JP2014060245A (ja) * 2012-09-18 2014-04-03 Mitsubishi Electric Corp 半導体装置
US8869085B2 (en) * 2012-10-11 2014-10-21 International Business Machines Corporation Multi-finger transistor layout for reducing cross-finger electric variations and for fully utilizing available breakdown voltages
JP2014209522A (ja) 2013-04-16 2014-11-06 富士通株式会社 半導体装置及びその製造方法
JP2015046445A (ja) 2013-08-27 2015-03-12 富士通株式会社 化合物半導体装置及びその製造方法
JP6810350B2 (ja) * 2016-12-28 2021-01-06 富士通株式会社 半導体装置、半導体装置の製造方法及び電子装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102969289A (zh) * 2011-09-01 2013-03-13 三菱电机株式会社 半导体装置及其制造方法
CN105374743A (zh) * 2014-08-08 2016-03-02 三菱电机株式会社 半导体装置的制造方法
CN106098757A (zh) * 2015-04-30 2016-11-09 三菱电机株式会社 场效应晶体管

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111710715A (zh) * 2020-05-14 2020-09-25 西安电子科技大学 具有空气腔的氮化镓微波毫米波晶体管结构及制备方法

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