TW201442229A - 異質接面雙極電晶體佈局結構 - Google Patents

異質接面雙極電晶體佈局結構 Download PDF

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Publication number
TW201442229A
TW201442229A TW102113675A TW102113675A TW201442229A TW 201442229 A TW201442229 A TW 201442229A TW 102113675 A TW102113675 A TW 102113675A TW 102113675 A TW102113675 A TW 102113675A TW 201442229 A TW201442229 A TW 201442229A
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Taiwan
Prior art keywords
collector
emitter
pad
bipolar transistor
heterojunction bipolar
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TW102113675A
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English (en)
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TWI540722B (zh
Inventor
Shu-Hsiao Tsai
Hsiu-Chen Chang
Shinichiro Takatani
Cheng-Kuo Lin
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Win Semiconductors Corp
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Priority to TW102113675A priority Critical patent/TWI540722B/zh
Priority to US13/913,290 priority patent/US9356127B2/en
Publication of TW201442229A publication Critical patent/TW201442229A/zh
Priority to US15/142,948 priority patent/US20160247797A1/en
Application granted granted Critical
Publication of TWI540722B publication Critical patent/TWI540722B/zh

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  • Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

一種異質接面雙極電晶體佈局結構，包括一或多個異質接面雙極電晶體，其中每一個包含一基極、一射極以及一集極電極，於異質接面雙極電晶體上方設有一被動層、一第一介電層、一集極重分布層、一或多個射極銅柱以及一或多個集極銅柱，其中被動層包含一射極焊墊與一集極焊墊，第一介電層具有一或多個射極導孔與集極導孔，分別位於射極焊墊與集極焊墊之上，射極銅柱係設於射極導孔上並電性連接於射極電極，而集極銅柱係設於集極重分布層之上並電性連接於集極電極，使射極銅柱與集極銅柱之佈局具有彈性，並同時提升元件散熱效率。

Description

異質接面雙極電晶體佈局結構
本發明係有關一種異質接面雙極電晶體佈局結構，尤指一種同時具有重分布層(redistribution layer,RDL)與銅柱之異質接面雙極電晶體佈局結構。
隨著行動通訊產業的蓬勃發展，對高性能、體積小的電子元件的需求也日益增加，由於化合物半導體異質接面雙極電晶體積體電路具有高功率、低雜訊、小尺寸等優點，目前已被普遍應用於行動通訊電子產品中，因此，若能改進化合物半導體異質接面雙極電晶電路之性能與尺寸，將能有效提高產品競爭力。
傳統的覆晶技術在砷化鎵異質接面雙極電晶體元件的應用上，為了提升元件的散熱特性，會將銅柱覆蓋在元件的射極上方，並搭配原有的金屬導線製程技術建立元件的集極、基極銅柱，但由於銅柱之間有製程上最小距離的限制，使元件尺寸會因此受到限制而無法縮小，並導致銅柱與銅柱間的空間浪費，大幅降低產品市場競爭力，此外，因異質接面雙極電晶體之射極與集極磊晶層高度落差大，於其上設置銅柱高度不易一致，導致晶片封裝時容易產生焊點接觸不良的問題，限制晶片封裝良率的提昇。
本發明之主要目的在於提供一種同時具有重分布層(redistribution layer)與銅柱之異質接面雙極電晶體佈局結構，藉由整合覆晶技術與導線重佈技術，使元件散熱效率得以提升，而射極銅柱與集極銅柱之佈局具有彈性，搭配使用具有低介電係數及優異平坦化能力之介電材料，使傳統覆晶技術中的射極銅柱與集極銅柱之高度差能被縮減，進而提升產品良率。
本發明之另一目的在於提供一種同時具有重分布層(redistribution layer)與銅柱之異質接面雙極電晶體佈局結構，其能利用射極銅柱與集極銅柱佈局之彈性，並能充分利用晶片空間設置電路所需的被動元件，達到晶片尺寸微縮之目的。
本發明之再一目的在於提供一種同時具有重分布層(redistribution layer)與銅柱之異質接面雙極電晶體佈局結構，其藉由填補導孔以補償射極銅柱與集極銅柱之高度差，更進一步提升產品良率。
為達上述目的，本發明提供一種異質接面雙極電晶體佈局結構，其包括一或多個異質接面雙極電晶體、一被動層、一第一介電層、一集極重分布層、一或多個射極銅柱以及一或多個集極銅柱，其中前述一或多個異質接面雙極電晶體係形成於一基板上方，其中每一個異質接面雙極電晶體包含一基極電極、一射極電極以及一集極電極；前述被動層係形成於該異質接面雙極電晶體上方，包括一射極焊墊與一集極焊墊，其中前述射極焊墊係電性連接於每一個射極電極，而前述集極焊墊係電性連接於每一個集極電極；前述第一介電層係覆蓋於該被動層之上，並於前述射極焊墊上方形成一或多個貫通該第一介電層之射極導孔，並於該集極焊墊上方形成一或多個貫通該第一介電層之集極導孔；前述集極重分布層係位於前 述第一介電層之上，並延伸進入前述集極導孔而電性連接於前述集極焊墊；前述射極銅柱中的每一個係位於至少一個前述射極導孔上方並填滿該射極導孔而電性連接於前述射極焊墊；而前述一或多個集極銅柱係位於前述集極重分布層之上並電性連接於該集極重分布層。此外，本發明所提供之一種異質接面雙極電晶體佈局結構，可於前述第一介電層上包含一射極重分布層，其延伸進入前述射極銅柱與射極導孔之間而電性連接於前述射極焊墊。
為達尺寸微縮之目的，本發明提供幾種佈局設計於上述異質接面雙極電晶體佈局結構中形成銅柱及電路所需的被動元件：前述集極焊墊係與該射極銅柱相鄰；前述集極銅柱中的每一個係位於前述至少一個前述集極導孔之上方並填滿該集極導孔；前述異質接面雙極電晶體佈局結構更包含一或多個電容及電阻，耦接於前述異質接面雙極電晶體，且該一或多個電容及電阻設置於前述集極焊墊與射極焊墊間區域之被動層中；前述集極焊墊係與該射極銅柱相鄰；前述集極銅柱係形成於前述集極焊墊之上、前述集極導孔上方之外的區域；而前述射極銅柱藉由填滿射極導孔補償射極銅柱與集極銅柱之高度差；前述異質接面雙極電晶體佈局結構更包含一或多個電容及電阻，耦接於前述異質接面雙極電晶體，且設置於前述集極焊墊與射極焊墊間區域之被動層中；延伸上述異質接面雙極電晶體佈局結構中之集極重分布層，使集極銅柱可從前述與射極銅柱相鄰的位置移至他處以充分利用晶片空間，進而縮小晶片尺寸；前述集極重分布層於前述第一介電層之上形成一集極重分布層延伸區域，前述集極銅柱係形成於前述集極重分布層延伸區域上、前述 集極導孔上方以外的位置，而前述射極銅柱藉由填滿該射極導孔補償該射極銅柱與集極銅柱之高度差；前述異質接面雙極電晶體佈局結構更包含一或多個電容及電阻，耦接於前述異質接面雙極電晶體；前述一或多個電容及電阻係設置於前述射極焊墊與集極焊墊間區域之外、鄰近前述射極焊墊處之被動層中，或設置於前述射極銅柱下方、前述射極焊墊與集極焊墊間區域之外、鄰近前述射極焊墊處之被動層中；此外亦可延伸上述異質接面雙極電晶體佈局結構中之集極焊墊，使集極導孔可從前述與射極導孔平行相鄰的位置移至他處以充分利用晶片空間，進而縮小晶片尺寸；前述集極焊墊於前述被動層中形成一集極焊墊延伸區域，前述一或多個集極導孔中至少一個係形成於該集極焊墊延伸區域之上，前述集極銅柱中的每一個係位於至少一個該集極焊墊延伸區域上方之集極導孔之上並填滿該集極導孔，而前述射極銅柱藉由填滿該射極導孔補償該射極銅柱與集極銅柱之高度差；前述異質接面雙極電晶體佈局結構更包含一或多個電容及電阻，耦接於前述異質接面雙極電晶體；前述一或多個電容及電阻係設置於前述射極焊墊與集極焊墊間區域之外、鄰近前述射極焊墊處之被動層中，或設置於前述射極銅柱下方、前述射極焊墊與集極焊墊間區域之外、鄰近前述射極焊墊處之被動層中。
於實施時，前述基板係以化合物半導體材料砷化鎵(GaAs)、氮化鎵(GaN)、炭化矽(SiC)或藍寶石(sapphire)形成。
為對於本發明之特點與作用能有更深入之瞭解，茲藉實施例配合圖式詳述於後。
100‧‧‧基板
110‧‧‧異質接面雙極電晶體
111‧‧‧次集極層
112‧‧‧集極層
113‧‧‧基極層
114‧‧‧射極層
121‧‧‧基極電極
122‧‧‧射極電極
123‧‧‧集極電極
130‧‧‧被動層
131‧‧‧第一金屬層
132‧‧‧第二金屬層
131a、131b‧‧‧焊墊
132a‧‧‧射極焊墊
132b‧‧‧集極焊墊
132c‧‧‧集極焊墊延伸區域
133、134、135‧‧‧覆蓋層
141‧‧‧射極重分布層
142‧‧‧集極重分布層
142a‧‧‧集極重分布層延伸區域
151‧‧‧第一介電層
152‧‧‧第二介電層
161‧‧‧射極銅柱
162‧‧‧集極銅柱
163、164‧‧‧焊球
171‧‧‧射極導孔
172‧‧‧集極導孔
181‧‧‧電容
182‧‧‧電阻
第1A圖係為本發明所提供之異質接面雙極電晶體佈局結構 之一種實施例之俯視結構示意圖。
第1B及1C圖係為沿第1A圖之虛線AA’及虛線BB’之剖面結構示意圖。
第1D圖係為本發明所提供之異質接面雙極電晶體佈局結構之另一種實施例之俯視結構示意圖。
第1E係為沿第1D圖之虛線AA’之剖面結構示意圖。
第1F及1G圖係為本發明所提供之異質接面雙極電晶體佈局結構之另二種實施例之俯視結構示意圖。
第2A及2B圖係為本發明所提供之異質接面雙極電晶體佈局結構之另一種實施例之俯視結構示意圖及沿第2A圖中虛線AA’之剖面結構示意圖。
第2C及2D圖係為本發明所提供之異質接面雙極電晶體佈局結構之另一種實施例之俯視結構示意圖及沿第2C圖中虛線AA’之剖面結構示意圖。
第3A及3B圖係為本發明所提供之異質接面雙極電晶體佈局結構之另二種實施例之俯視結構示意圖。
第1A-1C圖為本發明所提供的異質接面雙極電晶體佈局結構之一種實施例之示意圖，其中第1B圖為沿第1A圖之虛線AA’之剖面示意圖，第1C圖為沿第1A圖之虛線BB’之剖面示意圖。如圖所示，該異質接面雙極電晶體佈局結構包括一或多個異質接面雙極電晶體110、一被動層130、一第一介電層151、一集極重分布層142、一射極銅柱161以及一集極 銅柱162，其中前述一或多個異質接面雙極電晶體110係位於一基板100上方，其中每一個異質接面雙極電晶體包含一次集極層111、一集極層112、一基極層113以及一射極層114，其中基極層113上設有一基極電極121，射極層114上設有一射極電極122，而次集極層111上設有一集極電極123；被動層130係形成於異質接面雙極電晶體110上方，包括一射極焊墊132a與一集極焊墊132b，其中射極焊墊132a係電性連接於每一個射極電極122，而集極焊墊132b係電性連接於每一個集極電極123；第一介電層151係覆蓋於被動層130之上，並於射極焊墊132a上方形成一貫通第一介電層151之射極導孔171，且於集極焊墊132b上方形成一貫通第一介電層151之集極導孔172；集極重分布層142係位於第一介電層151之上並延伸進入集極導孔172而電性連接於集極焊墊132b；射極銅柱161係位於射極導孔171之上方並填滿射極導孔171而電性連接於射極焊墊132a；集極銅柱162係位集極導孔172之上方並填滿集極導孔172而電性連接於集極重分布層142；射極銅柱161與集極銅柱162上並可分別形成一銲球163及164。上述異質接面雙極電晶體佈局結構可更於第一介電層151之上形成一射極重分布層141，如第1D及1F圖所示，射極重分布層141並延伸進入射極銅柱161與射極導孔171之間而電性連接於前述射極焊墊132a。
在上述實施例中，異質接面雙極電晶體之射極電極可為平行指狀電極；射極焊墊132a與集極焊墊132b為長條形，其長軸為平行排列；射極導孔171、集極導孔172與位於其上方之射極銅柱161與集極銅柱162亦為長條形，集極銅柱162係與射極銅柱161相鄰，其長軸係為平行排列；射極銅柱與集極銅柱邊緣之間距d1受覆晶技術的限制，通常為介於10到75 μm之間；集極焊墊與射極焊墊之間的空間可用以設置電路所需之被動元件以節省晶片空間，如第1A-1E圖所示，於集極焊墊132b與射極焊墊132a 間區域之被動層130中設置一或多個電容181及電阻182，並使其耦接於異質接面雙極電晶體110。
前述實施例中，亦可使用一或多個圓形集極銅柱取代長條型集極銅柱，並使用一或多個較短的集極導孔取代一長條型集極導孔，每一個圓形集極銅柱162係設置於一集極導孔172之上方，並使集極銅柱162填滿集極導孔172，如第1F圖所示；此外，亦可將前述圓形集極銅柱162設置於集極導孔172上方以外的區域，而透過集極重分布層142電性連接於集極焊墊132b，如第1G圖所示。為了達到良好的散熱功能，通常會使用具有較大截面積的射極銅柱，而製程中具有較大截面積的射極銅柱其生成高度最後常會高於截面積較小的集極銅柱，使元件封裝後因銅柱的高度落差而導致接觸不良；在本發明所提供的實施例中，射極銅柱可藉由填補射極導孔補償射極與集極銅柱高度落差(如第1G圖)，射極銅柱與集極銅柱皆位於導孔上方時，亦可透過控制導孔的大小(如第1D及1F圖)或是否設置射極重分布層(如第1A圖)等方法補償射極與集極銅柱高度落差。
延伸上述異質接面雙極電晶體佈局結構中之集極重分布層，並將集極銅柱從前述與射極銅柱平行相鄰的位置移至他處，如此可充分利用晶片空間，達到縮小晶片尺寸的目的；第2A至2D圖為本發明所提供之另一種實施例，其中集極重分布層142於第一介電層152之上形成一集極重分布層延伸區域142a，將集極銅柱162設置於集極重分布層延伸區域142a上、集極導孔172上方以外的位置，集極焊墊及其上方之集極導孔與集極重分布層因此可更向射極銅柱161靠近，以縮小晶片尺寸；射極銅柱161之邊緣與集極重分布層142之邊緣的最小距離設為d2，d2之大小並無上限然實施時d2以越小為越佳，本實施例中d2通常為介於1到30 μm之間，較佳為介於1到20 μm之間，更佳為介於1到10 μm之間，最佳為介於1到5 μm之間；此外亦可縮小集極焊墊的面積，以更進一步縮小晶片尺寸，同時節省製造材料。
上述實施例中，集極焊墊與射極焊墊間距離縮短後，電路所需的被動元件如電容及電阻則從集極焊墊與射極焊墊間區域移至異質接面雙極電晶體之外緣，如第2A及2B圖所示，於射極焊墊132a與集極焊墊132b間區域之外、鄰近射極焊墊132a處之被動層中130設置一或多個電容181及電阻182，並使其耦接於異質接面雙極電晶體110；將射極焊墊132a與其下方之異質接面雙極電晶體磊晶層往集極焊墊132b方向移動，使射極銅柱161下方與基板之間形成一空間，此空間可供設置電路所需的被動元件，以更進一步縮小晶片尺寸，如第2C及2D圖所示，於射極銅柱161下方、射極焊墊132a與集極焊墊132b間區域之外、鄰近射極焊墊132a處之被動層中130設置一或多個電容181及電阻182，並使其耦接於異質接面雙極電晶體110。
第3A及3B圖為本發明所提供之另一種實施例，其中集極焊墊132b於被動層130中形成一集極焊墊延伸區域132c，集極導孔172與集極重分布層142係設置於此集極焊墊延伸區域132c之上，集極銅柱162則設置於集極導孔172之上並填滿該集極導孔，，集極焊墊因此可更向射極焊墊132a靠近，以縮小晶片尺寸；射極焊墊132a之邊緣與集極焊墊132b之邊緣的最小距離設為d3，d3之大小並無上限然實施時d3以越小為越佳，本實施例中d3通常為介於1到20 μm之間，較佳為介於1到15 μm之間，更佳為介於1到10 μm之間，最佳為介於1到5 μm之間。
上述實施例中，集極焊墊與射極焊墊間距離縮短後，電路所需的被動元件須設置於異質接面雙極電晶體之外緣，如第3A圖所示，於射極焊墊132a與集極焊墊132b間區域之外、鄰近射極焊墊132a處之被動層 中130設置一或多個電容181及電阻182，並使其耦接於異質接面雙極電晶體110；將射極焊墊132a與其下方之異質接面雙極電晶體磊晶層往集極焊墊132b方向移動，使射極銅柱161下方與基板之間形成一空間，此空間可供設置電路所需的被動元件，以更進一步縮小晶片尺寸，如第3B圖所示，於射極銅柱161下方、射極焊墊132a與集極焊墊132b間區域之外、鄰近射極焊墊132a處之被動層中130設置一或多個電容181及電阻182，並使其耦接於異質接面雙極電晶體110。
本發明所提供之被動層130可包含複數層金屬層，其中至少有位於最下層與異質接面雙極電晶體110之基極、集極與射極電極接觸之一第一金屬層131，以及位於最上層與重分布層接觸之一第二金屬層132，第一金屬層131可於電晶體電極上形成焊墊(如131a及131b)或導線，因與異質接面雙極電晶體直接接觸，其通常由含金金屬形成且不包含銅，以避免銅原子對電子元件造成污染；最上層之第二金屬層用以形成射極焊墊132a與集極焊墊132b，由於不會直接接觸電子元件，其可以含金金屬或含銅金屬形成；第一金屬層131與第二金屬層132間可更包含一或多層金屬層供互連之用；異質接面雙極電晶體上以及每兩層金屬層之間除電性接觸以外的區域以一覆蓋層(如133-135)覆蓋，供絕緣以及保護之用，覆蓋層係以具絕緣性的材料形成，其中以氮化矽(SiN)為較佳；被動層130中之金屬層除作為電性連之用，亦可用於製作電容等被動元件，如第1B、2B及3B圖所示，第一金屬層131、第二金屬層132與介於兩者間之覆蓋層134可用以形成一金屬-絕緣層-金屬(metal-insulator-metal,MIM)電容，更可於第一及第二金屬層中插入一或多層金屬層及覆蓋層，用以形成一堆疊式金屬-絕緣層-金屬(stacked MIM)電容。
前述實施例中之異質接面雙極電晶體為一化合物半導體電子 元件，其下方之基板100係以化合物半導體材料砷化鎵(GaAs)、氮化鎵(GaN)、炭化矽(SiC)或藍寶石(sapphire)形成，其中以砷化鎵為較佳；射極重分布層141與集極重分布層142可由含金或銅等導電性佳的金屬形成，其中以含銅金屬形成為較佳；並可利用重分布層於第一介電層之上形成電感，以充份利用晶片之表面空間；為達成異質接面雙極電晶體封裝製程中表面平坦化的需求，第一介電層151以具有絕佳孔隙填充能力與優良平坦化特性的旋塗式介電材料形成為較佳，介電材料經由旋塗(spin coating)技術塗佈於最上層之覆蓋層上，再以加熱方式固化，第一介電層151可以介電材料聚酰亞胺(polyimide)、苯環丁烯(benzocyclobutene,BCB)或聚苯噁唑(polybenzoxazole,PBO)形成，其中聚苯噁唑(PBO)具有低介電係數及高拉伸強度，且此材料具有較高的固化厚度，可有效填補異質接面雙極電晶體射極與集極的高度落差，使形成於其上之導電銅柱能有一致的高度，為較佳介電材料選擇；此外，本發明所提供之異質接面雙極電晶體佈局結構可更包含一第二介電層152，其係覆蓋於第一介電層151、射極重分布層141以及集極重分布層142之上與射極銅柱161和集極銅柱162電性連接以外之區域；第二介電層152可以介電材料聚酰亞胺(polyimide)、苯環丁烯(benzocyclobutene,BCB)或聚苯噁唑(polybenzoxazole,PBO)形成，其中以聚苯噁唑(PBO)為較佳。
本發明所提供之設計，根據第1A-1G圖所示之任一實施例所製作的晶片，相較於先前技術其尺寸約可縮小16%；根據第2A圖所示實施例所製作的晶片，相較於先前技術其尺寸約可縮小34%；而根據第2C圖所示實施例所製作的晶片，相較於先前技術其尺寸縮小率更可高達約40%，因此，本發明所提供之設計確實能有效縮小元件尺寸。
本發明具有以下優點：
1.本發明所提供之異質接面雙極電晶體佈局結構中，可將射極銅柱直接設置於異質接面雙極電晶體的射極之上，因此能增進異質接面雙極電晶體的散熱效率。
2.本發明所提供之異質接面雙極電晶體佈局結構中，當射極焊墊與集極焊墊間距離較大時，可將電容及電阻等被動元件設置於平行排列之射極焊墊與集極焊墊間的區域，能有效利用晶片空間，縮小晶片尺寸。
3.本發明所提供之異質接面雙極電晶體佈局結構中，藉由重分布層，可將銅柱設置於任意位置上，因此能避免覆晶技術對相鄰銅柱最小間距的限制，達到縮小晶片尺寸的目的，並能縮小集極焊墊的尺寸，進而；此外，本發明可縮短射極焊墊與集極焊墊間的距離，使射極銅柱變為部份覆蓋射極焊墊，電容及電阻等被動元件則可設置於射極銅柱下方之空間，更進一步縮小晶片尺寸。
4.本發明所提供之異質接面雙極電晶體佈局結構中，使用低介電常數的旋塗式介電材料，可有效填補異質接面雙極電晶體射極與集極的高度落差，使形成於其上之導電銅柱能有一致的高度；而具有較大截面積之射極銅柱，可藉由填補射極導孔補償射極與集極銅柱高度落差，藉此提高封裝良率。
綜上所述，本發明提供之同時具有重分布層與銅柱之異質接面雙極電晶體佈局結構確實可達到預期之目的，在利用射極銅柱散熱的同時，能縮小晶片尺寸，並能改善銅柱的高度分布，進而提高封裝良率。其確具產業利用之價值，爰依法提出專利申請。
又上述說明與圖示僅是用以說明本發明之實施例，凡熟於此業技藝之人士，仍可做等效的局部變化與修飾，其並未脫離本發明之技術與精神。
110‧‧‧異質接面雙極電晶體
121‧‧‧基極電極
122‧‧‧射極電極
123‧‧‧集極電極
131b‧‧‧焊墊
132a‧‧‧射極焊墊
132b‧‧‧集極焊墊
141‧‧‧射極重分布層
142‧‧‧集極重分布層
142a‧‧‧集極重分布層延伸區域
161‧‧‧射極銅柱
162‧‧‧集極銅柱
171‧‧‧射極導孔
172‧‧‧集極導孔
181‧‧‧電容
182‧‧‧電阻

Claims (11)

  1. 一種異質接面雙極電晶體佈局結構，包括：一或多個異質接面雙極電晶體，其形成於一基板上方，其中每一個異質接面雙極電晶體包含一基極電極、一射極電極以及一集極電極；一被動層，其形成於該異質接面雙極電晶體上方，包括一射極焊墊與一集極焊墊，其中該射極焊墊係電性連接於每一個射極電極，而該集極焊墊係電性連接於每一個集極電極；一第一介電層，其覆蓋於該被動層之上，並於該射極焊墊上方形成一或多個貫通該第一介電層之射極導孔，以及於該集極焊墊上方形成一或多個貫通該第一介電層之集極導孔；一集極重分布層，其位於該第一介電層之上並延伸進入該集極導孔而電性連接於該集極焊墊；一或多個射極銅柱，其中每一個係位於至少一個射極導孔上方並填滿該射極導孔而電性連接於該射極焊墊；以及一或多個集極銅柱，位於該集極重分布層之上並電性連接於該集極重分布層。
  2. 如申請專利範圍第1項所述之異質接面雙極電晶體佈局結構，其中該第一介電層上更包含一射極重分布層，其延伸進入該射極銅柱與射極導孔之間而電性連接於該射極焊墊。
  3. 如申請專利範圍第1或2項所述之異質接面雙極電晶體佈局結構，其中該集極重分布層於該第一介電層之上形成一集極重分布層延伸區域，該集極銅柱係形成於該集極重分布層延伸區域上、該集極導孔上方以外的 位置；該射極銅柱藉由填滿該射極導孔補償該射極銅柱與集極銅柱之高度差。
  4. 如申請專利範圍第3項所述之異質接面雙極電晶體佈局結構，更包含一或多個電容及電阻，耦接於該異質接面雙極電晶體；該一或多個電容及電阻係設置於該射極焊墊與該集極焊墊間區域之外、鄰近該射極焊墊處之該被動層中。
  5. 如申請專利範圍第3項所述之異質接面雙極電晶體佈局結構，更包含一或多個電容及電阻，耦接於該異質接面雙極電晶體；該一或多個電容及電阻係設置於該射極銅柱下方、該射極焊墊與該集極焊墊間區域之外、鄰近該射極焊墊處之該被動層中。
  6. 如申請專利範圍第1或2項所述之異質接面雙極電晶體佈局結構，其中該集極焊墊於該被動層中形成一集極焊墊延伸區域，該一或多個集極導孔中至少一個係形成於該集極焊墊延伸區域之上，該集極銅柱中的每一個係位於至少一個該集極焊墊延伸區域上方之集極導孔之上並填滿該集極導孔；該射極銅柱藉由填滿該射極導孔補償該射極銅柱與集極銅柱之高度差。
  7. 如申請專利範圍第6項所述之異質接面雙極電晶體佈局結構，更包含一或多個電容及電阻，耦接於該異質接面雙極電晶體；該一或多個電容及電阻係設置於該射極焊墊與該集極焊墊間區域之外、鄰近該射極焊墊之該被動層中。
  8. 如申請專利範圍第6項所述之異質接面雙極電晶體佈局結構，更包含一或多個電容及電阻，耦接於該異質接面雙極電晶體；該一或多個電容及電阻係設置於該射極銅柱下方、該射極焊墊與該集極焊墊間區域之外、鄰近該射極焊墊處之該被動層中。
  9. 如申請專利範圍第1或2項所述之異質接面雙極電晶體佈局結構，其中該集極銅柱係與該射極銅柱相鄰；該集極銅柱中的每一個係位於至少一個該集極導孔之上並填滿該集極導孔；該異質接面雙極電晶體佈局結構更包含一或多個電容及電阻，耦接於該異質接面雙極電晶體，且該一或多個電容及電阻係設置於該集極焊墊與該射極焊墊間區域之該被動層中。
  10. 如申請專利範圍第1或2項所述之異質接面雙極電晶體佈局結構，其中該集極銅柱係與該射極銅柱相鄰；該集極銅柱中的每一個係位於該集極焊墊之上、該集極導孔上方之外的區域；該射極銅柱藉由填滿該射極導孔補償射極銅柱與集極銅柱之高度差；該異質接面雙極電晶體佈局結構更包含一或多個電容及電阻，耦接於該異質接面雙極電晶體，且該一或多個電容及電阻係設置於該集極銅柱與該射極銅柱間區域之該被動層中。
  11. 如申請專利範圍第1或2項所述之異質接面雙極電晶體佈局結構，其中該基板係以化合物半導體材料砷化鎵(GaAs)、氮化鎵(GaN)、炭化矽(SiC)或藍寶石(sapphire)形成。
TW102113675A 2013-04-17 2013-04-17 異質接面雙極電晶體佈局結構 TWI540722B (zh)

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