TW201740563A - 半導體裝置的鰭狀結構以及鰭式場效電晶體裝置 - Google Patents

半導體裝置的鰭狀結構以及鰭式場效電晶體裝置 Download PDF

Info

Publication number
TW201740563A
TW201740563A TW105124385A TW105124385A TW201740563A TW 201740563 A TW201740563 A TW 201740563A TW 105124385 A TW105124385 A TW 105124385A TW 105124385 A TW105124385 A TW 105124385A TW 201740563 A TW201740563 A TW 201740563A
Authority
TW
Taiwan
Prior art keywords
semiconductor material
fin
field effect
effect transistor
transistor device
Prior art date
Application number
TW105124385A
Other languages
English (en)
Other versions
TWI696286B (zh
Inventor
劉昇旭
李鎮全
陳致中
呂曼綾
蔡宗閔
陳意維
Original Assignee
聯華電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聯華電子股份有限公司 filed Critical 聯華電子股份有限公司
Publication of TW201740563A publication Critical patent/TW201740563A/zh
Application granted granted Critical
Publication of TWI696286B publication Critical patent/TWI696286B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

一種半導體裝置的鰭狀結構，例如鰭式場效電晶體(FinFET)結構，具有第一半導體層、第二半導體層以及位於第一半導體層與第二半導體層之間的空氣間隔。空氣間隔可防止漏電。鰭式場效電晶體裝置可由先進行掘入再進行磊晶再成長的方式形成源極/汲極鰭，而此再成長可開始於一管狀空氣間隔的上方。

Description

半導體裝置的鰭狀結構以及鰭式場效電晶體裝置
本發明係關於一種半導體裝置以及半導體裝置的製造方法，尤指一種鰭式場效電晶體(fin-type field effect transistor)裝置以及其製造方法。
按比例縮小化之半導體裝置已應用於各種類型的場效電晶體。在此些裝置之微縮已導向電性以及製程的極限時，需開發其他技術來維持或/及達到所需的效能。其中，鰭式場效電晶體(fin-type field effect transistor，FinFET)裝置係被開發用以在閘極尺寸縮減的狀態下維持或/及達到更佳的效能。例如於美國專利號US 9,123,744中揭露之鰭式場效電晶體裝置，而US 9,123,744的全部公開內容係通過引用併入本文。
在現今的電子裝置(包括鰭式場效電晶體裝置)的主要問題在於漏電。習知可於半導體裝置中導入絕緣層覆矽(silicon-on-insulator，SOI)結構來減少漏電，例如於美國專利號US 8,395,217中所揭露的SOI結構。SOI結構相對來說較昂貴，且SOI結構還尚未能相容於現已普及使用之塊材基底結構。
本發明可對上述習知裝置及方法的缺點提供很大程度的改善。
依據本發明之一層面，一種半導體裝置的鰭狀結構包括一第一半導體材料、一空氣間隔以及一第二半導體材料。舉例來說，該半導體裝置可為鰭式場效電晶體(fin-type field effect transistor，FinFET)裝置。該第一半導體材料可為例如一成長於鰭之凹陷內的磊晶材料，該第二半導體材料可為例如一基底材料，而該空氣間隔可位於該第一半導體材料與該第二半導體材料之間。
依據本發明之另一層面，該空氣間隔可具有一管狀型態。該空氣間隔可具有一中心軸平行於該鰭狀結構中自源極區至一汲極區之方向。該空氣間隔可減少關於該鰭狀結構之漏電。如果需要的話，該空氣間隔之剖面形狀可似具有兩尖端之檸檬形狀或一橄欖形狀。
依據本發明之另一層面，該第一半導體材料可位於一下凹陷部，且該下凹陷部具有一向上開口角介於10度至55度。
依據本發明之另一層面，一個或多個該鰭狀結構可存在於一鰭式場效電晶體裝置中，特別是未具有絕緣層覆矽(silicon-on-insulator，SOI)結構之鰭式場效電晶體裝置，以及特別是藉由先掘入再磊晶再成長形成一個或多個源極/汲極鰭之製造方式形成之鰭式場效電晶體裝置。
依據本發明之另一層面，該第一半導體材料包括一磷化矽(SiP)緩衝層位於該空氣間隔上方，且一磷化矽基體層係成長於位於該磷化矽緩衝層上。如果需要的話，該磷化矽基體層的一部分可形成一對稱之鏟狀部。
本發明之其他特徵、實施例以及其他額外層面可參考詳細的實施方式以及圖式內容。此外，必須了解的是，上述之發明內容以及後述之實施方式僅為範例用以提供更進一步說明而並未對本發明之範圍構成限制。
在此所述之製程步驟、方法步驟或類似者之進行順序可在可施行的狀態下進行順序調整。換句話說，在此說明之步驟順序並不意味此些步驟必須以此順序施行。在此說明之製程與方法的步驟可以任何可行的順序執行。此外，除了特別有說明不行，否則部分之步驟亦可同步進行。
請參考圖式，其中元件係以參考數字及符號標示，而第1圖繪示了依據本發明之一層面之鰭式場效電晶體裝置10的結構。鰭式場效電晶體裝置10具有一矽基底(基底12)、一閘極14以及三個鰭16，各鰭16矽延伸穿過閘極14且具有相對之源極區20與汲極區22。本發明並不以此圖式結構為限。例如，本發明之鰭式場效電晶體裝置可具有一個、兩個或多於三個的鰭16。
如果需要的話，基底12可由單晶矽材料或一磊晶矽材料所形成。如果需要的話，基底12可由一個或多個其他材料所形成，此材料可包括但不限於鍺化矽(SiGe)、碳化矽(SiC)與砷化鎵(GaAs)。多個鰭16的下部係藉由多個淺溝隔離(shallow trench isolation，STI)區26彼此分開。各淺溝隔離區26之表面的剖面形狀可如第2圖與第3圖所示之碗形或V字形。各鰭16於剖線2-2之方向上的節距65可為例如480埃(angstrom)。
第2圖繪示了兩個鰭16於一製造過程中的狀態。在所繪示的狀態下，各個鰭16已經過數道製程，此些製程較佳可包括但不限於依此順序之一垂直矽蝕刻製程、一側向矽蝕刻製程以及一額外氧電漿製程。
在各個鰭16中，一個大體上為直線形成的凹陷部40係於該垂直係蝕刻製程中形成。一下凹陷部42係於該側向矽蝕刻製程中形成。下凹陷部42之底面68應遠深於牆44以及牆46(牆44以及牆46亦可被視為間隙子)與淺溝隔離區26之間的介面67。舉例來說，底面68可比介面67更深約60至140埃。凹陷部40與下凹陷部42係與介電間隙物之牆44與牆46相連。各個牆44與牆46可具有一氮化矽(SiN)層48(可被視為一硬遮罩)、一氮碳化矽層50(可被視為一硬遮罩)以及第二個氮碳化矽層52(可被視為一密封層)。凹陷部40與下凹陷部42可作為例如第1圖所示之鰭式場效電晶體裝置10的源極/汲極凹陷。
上述之額外氧電漿製程可使用高溫電漿且其目的在於移除凹陷部40與下凹陷部42內的雜質，此雜質可包括但不限於光阻、由主蝕刻製程產生之碳-氫-氟-溴-氮-矽(C-H-F-Br-N-Si)型聚合物、由沉積製程所產生之碳-氫(C-H)型聚合物、由過蝕刻製程所產生之碳-氫-氟-氮-矽(C-H-F-N-Si)型聚合物、由垂直蝕刻製程所產生之碳-氫-溴-矽(C-H-Br-Si)型聚合物以及由側向蝕刻製程所產生之碳-氫-氯-氟-矽(C-H-Cl-F-Si)型聚合物。
額外氧電漿製程係比一臨場(in-situ)氧剝離(O2 -strip)製程更適合。臨場氧剝離製程可於垂直蝕刻製程或/及側向蝕刻製程中執行，且臨場氧剝離製程容易產生過度氧化而因此造成作為間隙子之牆44與牆46之上端60與上端62(特別是作為間隙材料之氮化矽層48)過度劣化。特別是，臨場氧剝離製程容易使得牆44與牆46之限制間隙物高度(constrain spacer heights，CSH)64變小而導致不一致的現象。不同的鰭16之可能會經歷無法預期之不一致的限制間隙物高度64之損失。此不一致的高度縮減(Δ CSH)可能使得後續磊晶成長之磷化矽的差排(dislocation)、疊差(stacking faults)發生異常(例如不對稱)之狀況，進而導致元件劣化、汲極引致能障下降(drain-induced barrier lowering，DIBL)、基體漏電(bulk leakage，Isb)以及自對準接觸(self-aligned contact，SAC)形成不完全或形成不良等問題。
在本發明中，位於各個鰭16之牆44與牆46上的磊晶成長物(例如第3圖中標示74之物體)應較佳為對稱的形狀，例如在其剖面上可為鏟狀、六邊形、八邊形或其他的形狀。在第3圖所繪示的例子中，多個鏟狀部(也就是鏟狀部74)並未彼此合併。在一替代實施例中，多個鏟狀部可彼此相連合併。
上述於側向蝕刻製程之後進行的額外氧電漿製程並不會導致作為間隙子之牆44與牆46之上端60與上端62(如第2圖所示)產生過度劣化。上端60與上端62在額外氧電漿製程中並不會如在上述之臨場氧剝離製程中那樣程度地被氧化。因此，使用額外氧電漿製程可使鰭之牆44與牆46獲得更一致且高之限制間隙物高度64。
此外，使用額外氧電漿製程可提供充分的清潔效率以維持下兩者之間的關係處於可接受的狀態：(1)下凹陷部42之向上開口角θ與(2)確保可避免異常(例如非對稱)之緩衝成長。在本發明之一較佳實施例中，下凹陷部42之向上開口角θ的範圍可藉於約10度至約55度。因此，下凹陷部42的下部之剖面(如第2圖所示)為V字型且底面68處為弧面而非尖角。
另一方面，額外氧電漿製程可於下凹陷部42形成之後再進行，故可於下凹陷部42之底面68處產生一弱化氧化區。
請參考第3圖，在接續的製造步驟中，下凹陷部42中可生長成一磷化矽緩衝層70，且一磷化矽基體(SiP bulk)層72可接著於磷化矽緩衝層70上成長形成(自下而上式地)。磷化矽基體層72的成長係於鏟狀部74形成之後停止。如果需要的話，可於磷化矽緩衝層70開始成長之前先進行一SiCoNi清洗製程，用以移除下凹陷部42之表面的原生氧化物(native oxide)。
為了防止自鰭16通過下凹陷部42之底面68所產生之漏電，磷化矽緩衝層70係自下凹陷部42之側壁80與側壁82以側向並向內的方式成長而形成一空氣間隔100。磷化矽緩衝層70係藉由空氣間隔100與矽基底(也就是基底12)以一定程度分離(但非完全分離)。空氣間隔100係位於磷化矽緩衝層70與基底12之間。雖然於鰭之凹陷部的底面68未發生磷化矽生長，如果需要的話，位於空氣間隔100另一面之少部分的磷化矽緩衝層70亦可與基底12接觸。於如第2圖所繪示之製造狀態至如第3圖所繪示之製造狀態中，於凹陷部40以及下凹陷部42中以及其上所進行之自下而上的磷化矽磊晶成長係在未於鰭之凹陷部的底面68進行任何磷化矽成長的狀況下進行。
如第3圖所示，空氣間隔100係位於磷化矽緩衝層70之下。空氣間隔100可具有一管狀型態並具有一中心軸102。空氣間隔100可沿鰭16的整體長度延伸，除了鰭16被閘極14之牆所覆蓋處。在各個鰭16中，空氣間隔100之中心軸102係平行於鰭16自鰭16之源極區20延伸至鰭16之汲極區22之方向。如第3圖所示，空氣間隔100之剖面形狀可似具有兩尖端之檸檬形狀或一橄欖形狀。
在運作上，空氣間隔100分離磷化矽緩衝層70(可被視為一第一半導體材料之一例)與矽基底(基底12，可被視為一第二半導體材料之一例)。在本發明所繪示之實施例中，空氣間隔100佔據了約20%至約80%之位於第一半導體材料(例如磷化矽緩衝層70)與第二半導體材料(例如基底12)之間的空間，且空氣間隔100係位於淺溝隔離區26之表面最低處以下的區域。其中，空氣間隔100可用以降低鰭式場效電晶體裝置10之基體漏電(Isb)。
美國專利號US 8,395,217(自此簡稱Cheng專利)已揭露一種已知的方式，藉由於半導體裝置中控制磊晶成長來形成空氣間隔。然而，依據Cheng專利之內容，其空氣間隔係形成於埋入介電層(buried dielectric，BOX)上且係基於絕緣層覆矽(SOI)結構，且Cheng專利之空氣間隔並未分離第一半導體材料與第二半導體材料。
相對於Cheng專利，如果需要的話，本發明可應用於不具有SOI結構之狀態。如第1圖所示之本發明的鰭式場效電晶體裝置10並不具有SOI結構，且亦不具有關於鰭16之操作的埋入介電層，但本發明的鰭式場效電晶體裝置10的確具有被空氣間隔100形成互相分離之第一半導體材料(例如磷化矽緩衝層70)與第二半導體材料(例如基底12)。
本發明並不限於N型場效電晶體及其製程。如果需要的話，本發明亦可適用於P型場效電晶體(使用鍺化矽SiGe)及其製程。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧鰭式場效電晶體裝置
12‧‧‧基底
14‧‧‧閘極
16‧‧‧鰭
20‧‧‧源極區
22‧‧‧汲極區
26‧‧‧淺溝隔離區
40‧‧‧凹陷部
42‧‧‧下凹陷部
44‧‧‧牆
46‧‧‧牆
48‧‧‧氮化矽層
50‧‧‧氮碳化矽層
52‧‧‧氮碳化矽層
60‧‧‧上端
62‧‧‧上端
64‧‧‧限制間隙物高度
65‧‧‧節距
67‧‧‧介面
68‧‧‧底面
70‧‧‧磷化矽緩衝層
72‧‧‧磷化矽基體層
74‧‧‧鏟狀部
80‧‧‧側壁
82‧‧‧側壁
100‧‧‧空氣間隔
102‧‧‧中心軸
θ‧‧‧向上開口角
第1圖繪示了依據本發明之一層面之鰭式場效電晶體裝置的結構透視示意圖(為了清楚說明而簡化)。 第2圖為沿第1圖中剖線2-2所繪示之處於製造過程中狀態的鰭式場效電晶體裝置之兩相鄰鰭的細部剖視圖。 第3圖為沿第1圖中剖線2-2所繪示之處於第2圖之後的製造過程中狀態的該等鰭的剖視圖。
12‧‧‧基底
16‧‧‧鰭
26‧‧‧淺溝隔離區
42‧‧‧下凹陷部
44‧‧‧牆
46‧‧‧牆
48‧‧‧氮化矽層
50‧‧‧氮碳化矽層
52‧‧‧氮碳化矽層
67‧‧‧介面
68‧‧‧底面
70‧‧‧磷化矽緩衝層
72‧‧‧磷化矽基體層
74‧‧‧鏟狀部
80‧‧‧側壁
82‧‧‧側壁
100‧‧‧空氣間隔
102‧‧‧中心軸

Claims (17)

  1. 一種半導體裝置的鰭狀結構，包括： 一第一半導體材料； 一空氣間隔；以及 一第二半導體材料； 其中該空氣間隔係位於該第一半導體材料以及該第二半導體材料之間，且該第一半導體材料包括一磊晶材料。
  2. 如請求項1所述之鰭狀結構，其中該空氣間隔具有一管狀型態。
  3. 如請求項2所述之鰭狀結構，其中該鰭狀結構沿一第一方向拉長，該第一半導體材料沿該第一方向延伸，且該空氣間隔具有一中心軸平行於該第一方向。
  4. 如請求項1所述之鰭狀結構，更包括一下凹陷部，其中該空氣間隔係位於該下凹陷部的底部。
  5. 如請求項4所述之鰭狀結構，其中該下凹陷部具有一向上開口銳角大於0度且小於90度。
  6. 如請求項1所述之鰭狀結構，其中該第二半導體材料包括一單晶矽。
  7. 如請求項1所述之鰭狀結構，其中該第一半導體材料包括一個或多個選自於矽、磷摻雜矽、鍺化矽、碳化矽與砷化鎵之材料。
  8. 一種鰭式場效電晶體裝置，包括： 一基底； 一鰭，具有源極區與汲極區；以及 一閘極，跨過該鰭； 其中該鰭包括一第一半導體材料以及一空氣間隔，該基底包括一不同於該第一半導體材料之第二半導體材料，且該空氣間隔係位於該第一半導體材料以及該第二半導體材料之間。
  9. 如請求項8所述之鰭式場效電晶體裝置，其中該空氣間隔具有一管狀型態。
  10. 如請求項9所述之鰭式場效電晶體裝置，其中該鰭狀結構沿一第一方向拉長，該閘極沿一與該第一方向正交之第二方向拉長，且該空氣間隔具有一中心軸平行於該第一方向。
  11. 如請求項10所述之鰭式場效電晶體裝置，更包括一下凹陷部，其中該第一半導體材料係位於該第一下凹陷部中，該下凹陷部具有一向上開口角，該向上開口角係介於10度至55度且位於一與該第一方向垂直的平面。
  12. 如請求項8所述之鰭式場效電晶體裝置，其中該第二半導體材料包括一單晶矽。
  13. 如請求項8所述之鰭式場效電晶體裝置，其中該第二半導體材料包括一個或多個選自於矽、鍺化矽、碳化矽與砷化鎵之材料。
  14. 如請求項8所述之鰭式場效電晶體裝置，更包括複數個牆用以定義出一源極/汲極凹陷，其中該第一半導體材料係位於該等牆之間。
  15. 如請求項14所述之鰭式場效電晶體裝置，其中該等牆包括一個或多個的硬遮罩與介電材料。
  16. 如請求項14所述之鰭式場效電晶體裝置，其中該第一半導體材料包括一磷化矽緩衝層，且該鰭式場效電晶體裝置更包括一磷化矽基體層位於該磷化矽緩衝層上。
  17. 如請求項16所述之鰭式場效電晶體裝置，更包括一鏟狀部，其中該鏟狀部為該磷化矽基體層的一部分。
TW105124385A 2016-05-02 2016-08-02 半導體裝置的鰭狀結構以及鰭式場效電晶體裝置 TWI696286B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/144,204 2016-05-02
US15/144,204 US9780218B1 (en) 2016-05-02 2016-05-02 Bottom-up epitaxy growth on air-gap buffer

Publications (2)

Publication Number Publication Date
TW201740563A true TW201740563A (zh) 2017-11-16
TWI696286B TWI696286B (zh) 2020-06-11

Family

ID=59928573

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105124385A TWI696286B (zh) 2016-05-02 2016-08-02 半導體裝置的鰭狀結構以及鰭式場效電晶體裝置

Country Status (3)

Country Link
US (2) US9780218B1 (zh)
CN (1) CN107342322B (zh)
TW (1) TWI696286B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9780218B1 (en) * 2016-05-02 2017-10-03 United Microelectronics Corp. Bottom-up epitaxy growth on air-gap buffer
US10453943B2 (en) 2016-11-29 2019-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. FETS and methods of forming FETS
US10074558B1 (en) 2017-09-28 2018-09-11 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET structure with controlled air gaps
CN109872953B (zh) * 2017-12-04 2022-02-15 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US10347456B1 (en) * 2018-06-11 2019-07-09 International Business Machines Corporation Vertical vacuum channel transistor with minimized air gap between tip and gate

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6627974B2 (en) * 2000-06-19 2003-09-30 Nichia Corporation Nitride semiconductor substrate and method for manufacturing the same, and nitride semiconductor device using nitride semiconductor substrate
JP2005228781A (ja) * 2004-02-10 2005-08-25 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US8912602B2 (en) * 2009-04-14 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US8519481B2 (en) * 2009-10-14 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Voids in STI regions for forming bulk FinFETs
US8492235B2 (en) * 2010-12-29 2013-07-23 Globalfoundries Singapore Pte. Ltd. FinFET with stressors
US8937366B1 (en) 2011-04-26 2015-01-20 Stc.Unm Selective epitaxial overgrowth comprising air gaps
US8395217B1 (en) * 2011-10-27 2013-03-12 International Business Machines Corporation Isolation in CMOSFET devices utilizing buried air bags
US20130200455A1 (en) * 2012-02-08 2013-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dislocation smt for finfet device
US8779554B2 (en) * 2012-03-30 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. MOSFETs with channels on nothing and methods for forming the same
US8703556B2 (en) * 2012-08-30 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
KR102049774B1 (ko) * 2013-01-24 2019-11-28 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9123744B1 (en) 2014-03-07 2015-09-01 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US9159630B1 (en) * 2014-07-14 2015-10-13 Globalfoundries Inc. Fin field-effect transistor (FinFET) device formed using a single spacer, double hardmask scheme
US20160190239A1 (en) * 2014-12-26 2016-06-30 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US9666581B2 (en) * 2015-08-21 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with source/drain structure and method of fabrication thereof
US9905641B2 (en) * 2015-09-15 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
KR102366295B1 (ko) * 2015-09-15 2022-02-22 삼성전자주식회사 반도체 장치 및 그 제조 방법
US10177143B2 (en) * 2015-10-28 2019-01-08 Taiwan Semiconductor Manufacturing Company Limited FinFET device and method for fabricating the same
US10038095B2 (en) * 2016-01-28 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. V-shape recess profile for embedded source/drain epitaxy
US9780218B1 (en) * 2016-05-02 2017-10-03 United Microelectronics Corp. Bottom-up epitaxy growth on air-gap buffer

Also Published As

Publication number Publication date
US10158022B2 (en) 2018-12-18
CN107342322B (zh) 2022-04-08
CN107342322A (zh) 2017-11-10
US20170345938A1 (en) 2017-11-30
US9780218B1 (en) 2017-10-03
TWI696286B (zh) 2020-06-11

Similar Documents

Publication Publication Date Title
US12046673B2 (en) Vertical transistor and method of forming the vertical transistor
US10699941B2 (en) MOSFETs with channels on nothing and methods for forming the same
US9892912B2 (en) Method of manufacturing stacked nanowire MOS transistor
JP5291736B2 (ja) フィン型ｆｅｔを有する半導体装置およびその製造方法
US9130058B2 (en) Forming crown active regions for FinFETs
US10192746B1 (en) STI inner spacer to mitigate SDB loading
TWI642181B (zh) Iii-v族環繞式閘極半導體元件及其製造方法
US10158022B2 (en) Bottom-up epitaxy growth on air-gap buffer
KR102612342B1 (ko) 반도체 디바이스용 층간 유전체 구조물 내의 라이너 구조물
TWI497722B (zh) 具有底切之半導體帶及其製造方法
KR20190078818A (ko) 반도체 장치 및 그 제조 방법
KR102123919B1 (ko) 상향식 갭 충전을 위한 선택적 막 성장
KR102260237B1 (ko) 리세싱된 실리콘 캡이 있는 트랜지스터 및 그 형성 방법
CN107564859B (zh) 半导体装置及其制造方法
US20240113205A1 (en) Source/drain formation with reduced selective loss defects
CN111029406A (zh) 一种半导体器件及其制备方法
US9099309B2 (en) Method providing an epitaxial growth having a reduction in defects and resulting structure
CN105405881B (zh) 半导体器件及其制造方法
KR102629827B1 (ko) N-타입 finfet들 및 p-타입 finfet들을 위한 상이한 소스/드레인 프로파일들
JP2010010382A (ja) 半導体装置およびその製造方法