TWI497722B - 具有底切之半導體帶及其製造方法 - Google Patents

具有底切之半導體帶及其製造方法 Download PDF

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TWI497722B
TWI497722B TW102135538A TW102135538A TWI497722B TW I497722 B TWI497722 B TW I497722B TW 102135538 A TW102135538 A TW 102135538A TW 102135538 A TW102135538 A TW 102135538A TW I497722 B TWI497722 B TW I497722B
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semiconductor
dielectric
region
semiconductor strip
strip
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TW201436217A (zh
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Taichun Huang
Chihtang Peng
Chiawei Chang
Minghua Yu
Haoming Lien
Chaocheng Chen
Tzeliang Lee
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Taiwan Semiconductor Mfg Co Ltd
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Description

具有底切之半導體帶及其製造方法 【相關申請案】
本國際申請案主張於2013年3月12日提交申請之名稱「Semiconductor Strips with Undercuts and Methods for Forming the Same」之美國專利申請案第61/778,303號的優先權。該美國申請案之內容以全文引用之方式併入本文。
本發明是有關於一種鰭式場效電晶體的結構與製程，且特別是有關於一種具有底切之半導體帶的結構與其製程。
電晶體為現今積體電路的關鍵元件。為了滿足逐漸增加愈快速度的需求，電晶體的驅動電流需要逐漸變得更大。為了達成此效能的增加，電晶體的閘極長度持續地縮小。然而，閘極長度的縮減，導致部必要的效應，已知為「短通道效應」，其中將危害透過閘極的的電流控制。在短通道效應中有汲極引致能障下降(Drain-Induced Barrier Lowering，DIBL)及次臨界斜率退化(degradation of sub-threshold slope)，二者導致電晶體效能退化。
電晶體為現今積體電路的關鍵元件。為了滿足逐漸增加愈快速度的需求，電晶體的驅動電流需要逐漸變得更大。為了達成此效能的增 加，電晶體的閘極長度持續地縮小。然而，閘極長度的縮減，導致部必要的效應，已知為「短通道效應」，其中將危害透過閘極的的電流控制。在短通道效應中有汲極引致能障下降(Drain-Induced Barrier Lowering，DIBL)及次臨界斜率退化(degradation of sub-threshold slope)，二者導致電晶體效能退化。
多閘極電晶體結構的使用，可以有助於短通道效應的緩解。因此發展出鰭式場效電晶體。鰭式場效電晶體具有增加的通道寬度。藉由包括在半導體鰭側壁上的部分及半導體鰭上表面的部分形成通道，可達成通道寬度的增加。由於電晶體的驅動電流正比於通道寬度，鰭式場效電晶體的驅動電流將增加。
在一存在的鰭式場效電晶體的形成製程，首先形成淺溝渠區域於一矽基板中。接著使淺溝渠區域凹陷以形成矽鰭，矽鰭為矽基板的部分且在凹陷的淺溝渠區域上。接著，形成一閘極介電層，一閘極電極，及源極與汲極，以完成鰭式場效電晶體的形成。在對應的鰭式場效電晶體中，通道包括半導體鰭的側壁及上表面，以及因此有關於鰭式場效電晶體所使用的晶片區域，鰭式場效電晶體的驅動電流為高的。因此，鰭式場效電晶體在積體電路的近世代中變成一種趨勢。
根據某些實施例，一積體電路裝置包括一半導體基板，及一半導體帶延伸至該半導體基板中。一第一及一第二介電區域位於該半導體帶相對的二側，且與該半導體帶連接。每一該第一介電區域及該第二介電區域包括一第一部分與該半導體帶齊平，以及一第二部分低於該半導體 帶。該第二部分更包括一部分與該半導體帶重疊。
根據其他實施例，一積體電路裝置包括一半導體基板，及複數個半導體帶延伸至該半導體基板中。該等半導體帶彼此相互平行。該等半導體帶具有不平坦底面。複數個介電帶介於該等半導體帶之間，且使該等半導體帶彼此相互分隔。一介電區域在該等半導體帶下方，其中該介電區域連接該等半導體帶的該等不平坦底面。
根據另外其他實施例，一方法包括進行一第一蝕刻，以蝕刻一半導體基板，且以形成複數個溝渠的頂部，其中該半導體基板的部分，藉由該等溝渠分隔以形成複數個半導體帶。進行一第二蝕刻，以蝕刻該半導體基板，且以形成該等溝渠的底部。一第一介電材料填入該等溝渠的頂部及底部，其中該第一介電材料的部分位於該等溝渠的頂部以形成複數個介電帶。蝕刻該等介電帶及該等半導體帶的端部以形成一第一及一第二額外溝渠。該第一及該第二額外溝渠填入一第二介電材料以形成複數個額外介電區域。
20‧‧‧基板
22‧‧‧墊層
24‧‧‧罩幕層
26，40，44‧‧‧溝渠
26A，26B‧‧‧溝渠部分
28‧‧‧高分子
46‧‧‧磊晶半導體區域
48‧‧‧半導體鰭
50‧‧‧閘極介電層
52‧‧‧閘極電極
54‧‧‧鰭式場效電晶體
56‧‧‧源極區域
30，32‧‧‧半導體帶
30A‧‧‧底面
30B‧‧‧連接部分
30A1，30A2‧‧‧部分
31‧‧‧基板部分
36，42‧‧‧介電區域
38‧‧‧空氣間隙
58‧‧‧汲極區域
60‧‧‧源極及汲極矽化物區域
D1，D2‧‧‧深度
W1，W2，W3，W4‧‧‧寬度
T1‧‧‧厚度
α‧‧‧角度
為了可以更完整理解實施例及其優點，現在請參照後續說明並結合伴隨的圖示，其中：第1A圖至第9C圖為根據某些代表性實施例，一種鰭式場效電晶體製造方法中，中間步驟的剖面圖及上視圖；第10圖繪示根據某些替代實施例，隔離半導體帶具有大致平坦底面之剖面圖； 第11圖繪示根據某些代表性實施例，隔離半導體帶未與下方半導體基板完全分離的剖面圖；第12圖繪示根據某些代表性實施例，隔離半導體帶具有非垂直側壁的剖面圖；第13圖繪示根據某些代表性實施例，隔離半導體帶具有非垂直側壁及平坦底面的剖面圖。
本發明之實施例的製造與使用將詳細討論如後。然而可以理解的是，實施例所提供的許多可應用觀念，可以在特定上下文的廣泛變化下實施。後續討論的這些特定實施例僅為舉例，並非用以限定本發明範圍。
根據各種代表性的實施例，提供一場效電晶體(鰭式場效電晶體及其製造方法。形成鰭式場效電晶體的中間階段將以圖例說明。根據本實施例，鰭式場效電晶體的各種變化與操作將進行討論。所有各種視圖及圖示實施例中，類似標號用來指定類似元件。
第1A圖至第9C圖為根據某些代表性實施例，一種鰭式場效電晶體製造方法中，中間步驟的剖面圖及上視圖。第1A圖至第9C圖中每一圖都關聯一字母「A」，「B」及「C」，其中所有圖式數字結尾為字母「A」為對應晶圓100的上視圖，鰭式場效電晶體形成於其上。所有圖式數字結尾為字母「B」係取自對應上視圖的剖面線B-B’之平面。所有圖式數字結尾為字母「C」係取自對應上視圖的剖面線C-C’之平面。
第1A圖，第1B圖及第1C圖繪示在基板20中溝渠26的形成，基板20為一晶圓的一部分。基板20可以為半導體基板，舉例而言，可以是 一矽基板，一矽鍺基板，或一以其他半導體材料形成的基板。根據某些實施例，基板20為一大塊基板。在某些實施例中，基板20以一P型或N形摻質輕摻雜。
參照第1B圖，墊層22及罩幕層24可以形成在半導體基板20上。墊層22可以是一薄膜包括氧化矽，例如利用一熱氧化製程形成。墊層22可以作為一黏著層介於半導體基板20與罩幕層24之間。墊層22也可以做為針對蝕刻罩幕層24的一蝕刻終止層。在某些實施例中，罩幕層24以氮化矽形成，例如利用低壓化學氣相沉積(LPCVD)形成。在其他實施例中，罩幕層24藉由矽的熱氮化，電漿加強化學氣相沉積(PECVD)，或電漿陽極氮化形成。罩幕層24用來在後續微影製程中作為一硬罩幕。
如第1B圖所示，為了形成溝渠26，將罩幕層24及墊層22蝕刻，暴露出下方的半導體基板20。接著暴露的半導體基板20進行蝕刻，形成溝渠26。相鄰溝渠26之間的部分半導體基板形成半導體帶30。溝渠26可以是帶狀(當以晶圓100的上視圖，第1A圖觀之)，溝渠26彼此互相平行。相鄰溝渠26之間的部份半導體基板20自此稱之為半導體帶30。
再參照第1B圖，根據某些實施例，溝渠26的形成包括二階段。在第一階段，形成溝渠部分26A，溝渠部分26A具有大致直的側壁。溝渠26的形成可以包括一非等向性乾式蝕刻。在為了形成溝渠部分26的蝕刻中，蝕刻劑氣體比如可以使用溴化氫(HBr)，二氟甲烷(CH2 F2 )，氧氣，氯氣，及/或諸如此類，其中電漿藉由蝕刻劑氣體產生，以進行蝕刻。根據某些實施例，在第一蝕刻步驟中，一偏壓電壓範圍自約100V至約300V施加在基板20上。根據某些實施例，執行蝕刻的腔室之壓力可以介於約5毫托爾與30毫 托爾之間。根據某些實施例，溝渠部分26A的深度D1可以介於30埃與1500埃之間。
在第一蝕刻階段中，蝕刻寄氣體是如此選擇，使得高分子28的生成如一蝕刻的一副產品。舉例而言，二氟甲烷可以被選用，由於他傾向產生高分子28。此外，將調整製程條件，且製程條件適於產生可以選擇的厚高分子28。在第一蝕刻階段期間，溝渠部分26A的側壁藉由高分子28而受到保護，且溝渠部分26A的底部不被高分子28保護。在第一蝕刻階段之後，進行一第二蝕刻階段，以進一步向下延伸溝渠26，且橫向擴張溝渠26，以形成溝渠部分26B。在某些實施例中，第二蝕刻階段比第一蝕刻階段更加等向性，且可以包括非等向性分量及等向性分量。在替代的實施例中，第二蝕刻階段為一等向性蝕刻。第二蝕刻階段可以利用乾式電漿蝕刻而進行，且可以利用較不傾向生成高分子的一蝕刻劑氣體來進行。舉例而言，蝕刻氣體可以包括氟化硫及氧氣。根據某些代表性實施例中，在第二蝕刻階段中，施加於基板20的偏壓電壓，小於在第一蝕刻階段期間施加的偏壓電壓。在第二蝕刻階段後，高分子28將被移除。
由於高分子28的保護，在第二蝕刻階段中，溝渠部分26A並未橫向擴張。溝渠部分26A的底部並未受高分子28的保護，且因此基板20自溝渠部分26A底部被蝕刻，導致溝渠部分26B被形成。由於第二蝕刻階段的等向性行為，溝渠部分26B橫向及垂直方向同時擴張。藉由控制蝕刻時間，相鄰的溝渠部分26B可以彼此連接，且因此形成一連續開口在複數個半導體帶30的下方。第1B圖中相鄰溝渠部分26B的相連可以達成，例如是藉由確保溝渠部分26B的深度D2大於半導體帶30的寬度W1。
根據某些實施例，由於等向性蝕刻，半導體帶30的底面30A並不平坦。某些半導體帶30的底面30A可以包括部分30A1及部分30A2，二者皆為彎曲的。部分30A1及部分30A2面向相反方向。舉例而言，在代表性第2B圖中，繪示的部分30A1面向左方，而繪示的部分30A2面向右方。部分30A1及部分30A2的連接部分30B為對應半導體帶30的最低點。雖然在剖面圖中所繪示為一個點，連接部分30B為一條線，在半導體帶30長度的方向延伸，如第1C圖所示。此外，繪示的溝渠部分26B的最左邊部分及最右邊部分，具有彎曲的邊界，且此邊界具有部分圓或部分橢圓的形狀。在某些實施例中，連接部分30B大致對齊對應下方半導體帶30的一中線。
第1C圖繪示取自第1A圖中剖面線C-C’的平面之另一剖面圖，其中顯示半導體帶30鄰近溝渠部分26B。
參照第2A圖，第2B圖及第2C圖，一介電材料填入溝渠26(第1A，1B，1C圖)，接著藉由一平坦化，比如化學機械研磨(CMP)，以形成介電區域36。介電材料可以包括一氧化物(比如氧化矽)，一氮化物(比如氮化矽)，一氮氧化物(比如氮氧化矽)，一碳化物(比如碳化矽)，或諸如此類。在某些實施例中，介電區域36的形成係利用流動式化學氣相沉積(FCVD)進行。在其他實施例中，介電區域36利用其他間隙填入方法形成，比如高密度電漿化學氣相沉積(HDPCVD)。介電區域36填充溝渠26A，26B(第1B圖)。半導體帶30的底面30A與介電區域36接觸，介電區域36部分與半導體帶30重疊。填入溝渠部分26B的介電區域36可以相互連接，而形成一連續的介電區域，連續的介電區域具有一非平坦的上表面及一非平坦的底面。
在填入介電區域36後，進行一退火步驟。舉例而言，退火可 以一溫度介於約200度C與約1200度C之間，持續約介於約30分鐘與約120分鐘之間而進行。退火腔室可以填入製程氣體，比如氮氣，氬，氦，氧氣，臭氧，氫氣，水蒸氣，及/或諸如此類。在替代的實施例中，退火並不在此階段進行。在某些實施例，罩幕層24及墊層22(第1B圖及第1C圖)在介電區域36形成後移除。在替代的實施例中，罩幕層24及墊層22在介電區域42形成後移除，如第4A，4B及4C圖所示。
在某些實施例中，全部溝渠26皆填滿。在替代的實施例中，某些溝渠區域26B並未完全填滿，而空氣間隙38將形成於其中。可以理解的是，雖然使用名詞「空氣間隙」，然而間隙38並非必須填滿空氣，也可以填入空氣，氮氣或其他氣體，這些氣體當介電區域36形成時，填入製程腔室中。如第2B圖所示，可以有複數個空氣間隙38，每一個下方可能與半導體帶32其中之一重疊。第2C圖繪示空氣間隙38也可以形成一長帶狀具有長度方向與半導體帶30的長度方向平行。
第3A，3B，3C圖繪示介電區域36及半導體帶30端部的蝕刻，而溝渠40因此形成。在蝕刻後，剩餘的半導體帶30中間部分，物理上及電性上與基板20不連接。由於介電區域36包括部分位於半導體帶30下方，半導體帶30保持懸吊而未倒塌。根據某些實施例，蝕刻係利用一非等向性蝕刻方法進行，其中使用蝕刻劑氣體係配置以攻擊介電區域36，及半導體帶30。在某些實施例中，蝕刻劑氣體包括四氟化碳。
接著，一介電材料填入溝渠40中，及形成之介電區域42如第4A，4B，4C圖所示。介電區域42的材料可以選自於形成介電區域36的候選材料之相同族群，這些候選材料包括氧化物，氮化物，氮氧化物，碳化物 及諸如此類。再者，介電區域42可以利用形成介電區域36類似的方法形成，這些方法包括流動式化學氣相沉積(FCVD)，高密度電漿化學氣相沉積(HDPCVD)及諸如此類。在形成介電區域42之後，可以進行一退火。在某些實施例中，進行退火在一溫度介於約200度C與約1200度C之間，持續一時間週期介於約30分鐘與約120分鐘之間。退火腔室可以填入製程氣體，比如氮氣，氬，氦，氧氣，臭氧，氫氣，水蒸氣，及/或諸如此類。在替代的實施例中，退火步驟可以省略。
在某些實施例中介電區域36及42可以用相同介電材料形成。因此，介電區域36及42無法彼此區隔，或者可以藉由其不同特性而區隔，比如不同的密度，這些特性可以歸因於不同製程條件及/或不同退火條件。在替代實施例中，介電區域36及42可以不同材料形成，因此可以彼此區隔。在這些實施例中，介電區域36及42之間的介面是明顯可見的。
第5A，5B及5C圖及第6A，6B及6C圖繪示某些代表性實施例，其中半導體帶頂部的材料，以其他半導體材料所取代。在替代的實施例中，在第5A圖至第6C圖中的步驟是可以省略的。請參照第5A，5B及5C圖，進行一蝕刻步驟以凹陷半導體帶30，因此半導體帶30的頂部被移除，且形成溝渠44。半導體帶30的底部依然保留，且暴露於形成之溝渠44。半導體帶30殘留部分的厚度T1可以大於約2奈米，以至於殘留的半導體帶30可以作為後續磊晶的種子。溝渠44可以具有深度例如介於約30奈米及約1500奈米之間。
接著，如第6A，6B及6C圖所示，磊晶半導體區域46係磊晶生長於溝渠44(第5B圖)中。磊晶半導體區域46可以包括矽鍺，矽碳，矽磷， III-V族複合半導體，或諸如此類。在磊晶之後，進行一平坦化比如化學機械研磨(CMP)，使得磊晶半導體區域46的頂面大致與介電區域36及42的頂面齊平。
接著，亦如第7A，7B及7C圖所示，將介電區域36及42凹陷。部分半導體帶30突出於殘留介電區域36及42的頂面，而變成半導體鰭48。介電區域36及42的凹陷步驟可以利用一乾式蝕刻或一濕式蝕刻進行。在某些實施例中，介電區域36及42的凹陷步驟可以利用一乾式蝕刻進行，其中使用製程氣體包括氨及氟化氫。在替代實施例中，介電區域36及42的凹陷步驟可以利用一濕式蝕刻進行，其中蝕刻溶液包括三氟化氮及氫氟酸。在其他實施例中，介電區域36及42的凹陷步驟可以利用一稀釋的氫氟酸溶液進行。
如第8A，8B及8C圖所示，形成閘極介電層50以覆蓋鰭48的頂面及側壁。閘及介電層50可以透過一熱氧化製程而形成，而因此可以包括一熱氧化矽。可替代的是，閘極介電層50可以藉由一沉積步驟而形成，而可以包括高介電係數介電材料。接著閘極電極形成於閘極介電層50上。在某些實施例中，閘極電極52覆蓋複數個鰭48，以至於形成的鰭式場效電晶體54包括複數個鰭48。在替代的實施例中，每一鰭48可以用來形成一鰭式場效電晶體。接著形成鰭式場效電晶體54剩下的元件，這些元件包括源極區域56，汲極區域58，與源極及汲極矽化物區域60(第8A及8C圖)。如第8A，8B及8C圖所示，半導體帶30/44藉由介電區域36及42，完全與基板20隔離，且因此形成之鰭式場效電晶體54的漏電流可以很小。
第9A，9B及9C圖繪示根據替代實施例，形成鰭式場效電晶 體54。在這些實施例中，第5A圖至第6C圖中的製程步驟被省略，而因此半導體帶30維持未被磊晶區域取代。因此，半導體鰭48以與基板20相同材質形成。在這些實施例中剩餘的製程步驟與材質實質上與第8A，8B及8C圖所示相同。
根據某些實施例，在溝渠部分26B的形成中，如第1B圖所示，蝕刻時間被延長。因此，半導體帶30的底面30A可以是大致平坦的。形成之結構顯示於第10圖中。
根據替代實施例，如第11圖所示，蝕刻時間被縮減，而因此相鄰的溝渠部分26B彼此不連接。在這些實施例中，半導體帶30透過連接基板部分31連接下方的半導體基板20，基板部分31比上方的半導體帶30狹窄。基板部分31可以具有逐漸改變的寬度，其中基板部分31的中間部分具有寬度W2小於上部的寬度W3及下部的寬度W4。在這些實施例中，溝渠部分26B的剖面形狀可以具有形狀接近圓形或橢圓形。在第11圖中溝渠部分26B的外型可以達成，例如利用確保溝渠部分26B的深度D2小於半導體帶30的寬度W1來達成。
根據某些實施例，在溝渠部分26B的形成中，如第1B圖所示，調整製程條件以使得半導體帶30的側壁為垂直的。在替代的實施例中，亦如第11及12圖所示，半導體帶30的側壁為傾斜的。舉例而言，半導體帶30側壁的傾斜角度α可以小於約87度。類似第1B圖中所示的結構，第12圖繪示半導體帶30的底面為非平坦的。
類似第10圖中所示的結構，第13圖繪示半導體帶30的底面為平坦的，其中平坦的底面可以藉由在溝渠部分26B(第1B圖)的形成中，延長 蝕刻時間而達成。在第13圖中半導體帶30的側壁為傾斜的，且具有傾斜角α。
在本發明的實施例中，在絕緣區域形成中，藉由擴張凹陷底部的寬度，形成的絕緣區域可以直接延伸於半導體帶的下方。因此，半導體帶可以完全與對應的基板隔離，且因此降低生成之鰭式場效電晶體的漏電流。
雖然實施例與其優點已詳細陳述於上，可以理解的是，在不脫離如後附請求項所界定實施例的精神與範圍，可以進行各種修改，替代與變更。此外，本發明的範圍並不受限於特定實施例中的製程，機器，製造，內容組成，裝置，方法及步驟，其描述於說明書中。由於熟習此技藝者可以從本揭露書，已存在，或將被開發的製程，機器，製造，內容組成，裝置，方法或步驟，清楚理解，所以可以藉以利用，並根據這些揭露內容，實施大致與在此所述對應實施例相同的功能或達成大致相同的結果。如上所述，後附的請求項應包含在其範圍中的這些製程，機器，製造，內容組成，裝置，方法或步驟。
20‧‧‧基板
22‧‧‧墊層
24‧‧‧罩幕層
26‧‧‧溝渠
26A，26B‧‧‧溝渠部分
28‧‧‧高分子
30‧‧‧半導體帶
30A‧‧‧底面
30B‧‧‧連接部分
30A1，30A2‧‧‧部分
D1，D2‧‧‧深度
W1‧‧‧寬度

Claims (10)

  1. 一種積體電路裝置，包括：一半導體基板；一半導體帶延伸至該半導體基板中；一第一及一第二介電區域位於該半導體帶相對的二側，且與該半導體帶連接，其中每一該第一介電區域及該第二介電區域包括：一第一部分與該半導體帶高度齊平，以及一第二部分低於該半導體帶，其中該第二部分更包括一部分與該半導體帶重疊；以及一空氣間隙位於該半導體帶下方且與該半導體帶重疊，其中該空氣間隙藉由介電材料所包圍。
  2. 如請求項1所述的積體電路裝置，其中該第一介電區域的該第二部分連續地連接該第二介電區域的該第二部分。
  3. 如請求項1所述的積體電路裝置，其中該半導體帶包括一非平坦底面，且其中該非平坦底面具有一最低點靠近該半導體帶的一中線。
  4. 如請求項1所述的積體電路裝置，其中該第一介電區域及該第二介電區域具有長度方向平行於該半導體帶的長度方向，且其中該積體電路裝置更包括：一第三及一第四介電區域位於該半導體帶相對的二側，且與該半導體帶連接，其中每一該第三介電區域及該第四介電區域連接該第一及該第二介電區域。
  5. 如請求項4所述的積體電路裝置，其中該第一介電區域及該第二介電區域 以一第一介電材料形成，且其中該第三介電區域及該第四介電區域以一第二介電材料形成，該第二介電材料不同於該第一介電材料。
  6. 如請求項1所述的積體電路裝置，其中該半導體帶的一頂部高於該第一及該第二介電區域的頂面，而該半導體帶的該頂部形成一半導體鰭，且其中該積體電路裝置更包括：一閘極介電層位於該半導體鰭的側壁與頂面上；一閘極電極在該閘極介電層上；以及一源極區域及一汲極區域位於該閘極介電層相對的二側上。
  7. 一半導體製造方法，包括：進行一第一蝕刻，以蝕刻一半導體基板，且以形成複數個溝渠的頂部，其中該半導體基板的部分，藉由該等溝渠分隔以形成複數個半導體帶；進行一第二蝕刻，以蝕刻該半導體基板，且以形成該等溝渠的底部，其中該等溝渠的該等底部較寬於該等溝渠的該等頂部；一第一介電材料填入該等溝渠的該等頂部及該等底部，其中該第一介電材料的部分位於該等溝渠的頂部以形成複數個介電帶；蝕刻該等介電帶及該等半導體帶的端部以形成一第一及一第二額外溝渠；以及該第一及該第二額外溝渠填入一第二介電材料以形成複數個額外介電區域。
  8. 如請求項7所述的半導體製造方法，更包括： 在該第一及該第二額外溝渠填入該第二介電材料之後，蝕刻該等半導體帶的頂部，而遺留該等半導體帶的底部未蝕刻；以及磊晶生長一半導體材料在該等半導體帶之該等頂部遺留的凹陷中。
  9. 如請求項7所述的半導體製造方法，更包括：使該等介電帶與該等額外介電區域凹陷，其中該等半導體帶的部分形成複數個半導體鰭位於該等介電帶與該等額外介電區域的頂面上；形成一閘極介電層在該等半導體鰭的側壁及一頂面上；形成一閘極電極與該閘極介電層上；以及形成一源極區域及一汲極區域位於該閘極介電層相對的二側上。
  10. 一種積體電路裝置，包括：一半導體基板；一半導體帶延伸至該半導體基板中，其中該半導體帶具有一第一長度方向平行於該半導體基板之一主要表面；一第一介電區，包括：一第一及一第二部分位於該半導體帶相對的二側，且與該半導體帶之側壁接觸，其中該第一部分及該第二部分具有長度方向平行於該第一長度方向：以及一第三部分延伸至該半導體帶下方，其中該第三部分包括一頂表面與該半導體的一底表面接觸；一第二介電區域延伸入該半導體基板，其中該第二介電區具有一第二長度方向垂直於該第一長度方向，且該第二長度方向包括一側邊與該半導體帶之終端側及該介電區之該第一及第二部分接觸，且其中該第一介電區 及該第二介電區形成可區別的介面；以及一空氣間隙位於該第一介電區之該第三部分中。
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