TW201735142A - 用於製造半導體裝置之方法 - Google Patents

用於製造半導體裝置之方法 Download PDF

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TW201735142A
TW201735142A TW105138673A TW105138673A TW201735142A TW 201735142 A TW201735142 A TW 201735142A TW 105138673 A TW105138673 A TW 105138673A TW 105138673 A TW105138673 A TW 105138673A TW 201735142 A TW201735142 A TW 201735142A
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dielectric layer
layer
planarization
semiconductor device
dielectric
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TW105138673A
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吳俊毅
李亮嶢
蔡宗杰
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台灣積體電路製造股份有限公司
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Abstract

在一種用於製造半導體裝置的方法中，第一介電層形成於設置於基板上之下方結構上。抗平坦化層形成於第一介電層上。第二介電層形成於第一介電層及抗平坦化層上。對第二介電層、抗平坦化層及第一介電層執行平坦化作業。抗平坦化層由異於第一介電層之材料所製成。

Description

用於製造半導體裝置之方法
本發明實施例係關於一種半導體積體電路，特別是關於一種包含平坦化作業的半導體裝置之製造方法，例如化學機械研磨。
隨著半導體產業進展到奈米技術製程節點以尋求較高裝置密度、較高表現及較低成本的關係，來自製造及設計方面的挑戰驅使著三維設計的發展，例如鰭式場效電晶體(Fin FET)。Fin FET裝置典型來說包含附有高深寬比之半導體鰭片及於其中形成半導體電晶體裝置之通道及源極/汲極區。閘極形成於並沿著鰭裝置的側邊(例如，包覆)，利用增加通道及源極/汲極區之表面積的優點以生產較快、較可靠及較好控制的半導體電晶體裝置。一或多個層間介電(介電)層形成於鰭狀結構及/或閘極結構上，及對介電層執行平坦化作業，例如化學機械研磨製程。
本揭露一實施態樣係提供一種製造半導體裝置之方法，包含：形成一第一介電層於設置於一基板上之下方結構上；形成一抗平坦化層於該第一介電層上；形成一第二介電層於該第一介電層及該抗平坦化層上；以及對該第二介電層、該抗平坦化層及該第一介電層執行一平坦化作業，其中該抗平坦化層係由異於該第一介電層之材料所製成。
10‧‧‧基板
20‧‧‧下方結構
30‧‧‧第一介電層
40‧‧‧抗平坦化膜
42‧‧‧抗平坦化層
44‧‧‧抗平坦化層
45‧‧‧抗平坦化層
50‧‧‧遮罩層
55‧‧‧遮罩圖案
60‧‧‧第二介電層
70‧‧‧電漿處理
75‧‧‧離子
100‧‧‧基板
105‧‧‧遮罩層
200‧‧‧鰭狀結構
205‧‧‧鰭狀結構
210‧‧‧虛設鰭狀結構
250‧‧‧閘極結構
255‧‧‧閘極結構
260‧‧‧虛設閘極結構
300‧‧‧第一介電層
350‧‧‧第三介電層
450‧‧‧第一抗平坦化層
460‧‧‧第二抗平坦化層
500‧‧‧第二介電層
550‧‧‧第四介電層
AR1‧‧‧區域
AR2‧‧‧區域
AR3‧‧‧區域
AR4‧‧‧區域
AR5‧‧‧區域
D1‧‧‧距離
D2‧‧‧距離
H2‧‧‧碟陷量
當結合附圖閱讀以下詳細描述時將更好地理解本揭露內容之態樣。但須強調的是，依照本產業的標準做法，各種特徵未按照比例繪製。事實上，各種特徵的尺寸為了清楚的討論而可被任意放大或縮小。
第1-8圖係依據本揭露之一實施方式，顯示用於製造半導體裝置之例示性連續製程。
第9圖係依據本揭露之一實施方式，顯示半導體裝置之例示性佈局結構。
第10-17圖係依據本揭露之一實施方式，顯示用於製造半導體裝置之例示性連續製程。
第18圖及第19圖係依據本揭露之另一實施方式，顯示用於製造半導體裝置之例示性連續製程。
第20圖及第21圖係依據本揭露之另一實施方式，顯示用於製造半導體裝置之例示性連續製程。
本揭露接下來將會提供許多不同的實施方式或實施例以實施本揭露中不同的特徵。各特定實施例中的組成及配置將會在以下作描述以簡化本揭露。這些為實施例僅作為示範並非用於限定本揭露。例如，元件的尺寸並非限定於揭露的範圍或數值，但可取決於製程條件及/或理想的裝置特性。此外，敘述中一第一特徵形成於一第二特徵之上可包含實施例中的第一特徵與第二特徵直接接觸，亦可包含第一特徵與第二特徵之間更有其他額外特徵形成介於第一及第二特徵間，使第一特徵與第二特徵無直接接觸。為了簡單及清晰，各種特徵可任意地以不同比例繪製。
進一步，空間關係的用語像是“下方”、“之下”、“較低”、“上方”、“較高”及類似用語，可用於此處以便描述圖式中一元件或特徵與另一元件與特徵之間的關係。該等相對空間關係的用語乃為了涵蓋除了圖式所描述的方向以外，元件於使用或操作中之各種不同的方向。裝置可另有其他導向方式(旋轉90度或朝其他方向)，此時的空間相對關係也可依上述方式解讀。此外，用語像是“由...所製成”可意 味著“包含”或“由...組成”。
第1-8圖係依據本揭露之一實施方式，說明用於製造半導體裝置之例示性連續製程。第1-8圖說明用於製造一種介電層之例示性連續製程，其形成於下方結構及基板上。下方結構包含，例如，鰭狀結構、閘極結構、金屬配線及其組成。第1-8圖中，關於下方結構及/或任何額外元件的詳細說明被簡化或省略。
如第1圖中所示，下方結構20設置於基板10上。第2圖中，第一介電層30形成於下方結構20及未設置下方結構的基板10區域上。第一介電層30由例如，一或多層氧化矽為基底的絕緣材料所製成，例如SiO2、TEOS(矽酸乙酯)、BPSG(硼磷矽玻璃)或低介電係數(low-k)介電材料。低介電係數介電材料具有k值(介電常數)低於約4.0。一些低介電係數介電材料具有k值低於約3.5及可具有k值低於約2.5。
用於第一介電層30的材料可包含元素Si、O、C及/或H，例如SiCOH及SiOC。有機材料例如聚合物可用於第一介電層30。例如，第一介電層30由一或多層含碳材料、有機矽玻璃、含成孔劑材料及/或其組合所製成。
第一介電層30可利用例如，電漿增強化學氣相沉積(PECVD)、低壓CVD(LPCVD)、可流動式CVD、原子層CVD(ALCVD)及/或旋轉技術來形成。 在一些實施方式中，第一介電層30的厚度落於範圍自約500nm至約1500nm。
接著，如第3圖中所示，抗平坦化膜利用PECVD、LPCVD或其他適合的膜形成法形成於第一介電層30上。抗平坦化膜40包含具有於後續平坦化作業中(例如，化學機械研磨(CMP))蝕刻速率低於第一介電層30的材料。在一些實施方式中，抗平坦化膜包含一或多層氮化矽為基底的絕緣材料，例如SiN、SiON或SiCN、碳化矽(SiC)或鋁為基底的絕緣材料，例如AlO或AlON。在一些實施方式中抗平坦化膜40的厚度落於範圍自約50nm至約300nm，及在其他實施方式中落於範圍自約100nm至約200nm。
如第4圖及第5圖中所示，圖案化製程，包含對抗平坦化膜40進行微影及蝕刻製程以獲得抗平坦化層45。在一些實施方式中，如第4圖中所示，遮罩層50，例如光阻層或硬遮罩層，形成於抗平坦化膜40上。接著，如第5圖中所示，對抗平坦化膜40進行蝕刻以獲得抗平坦化層45。
如第5圖中所示，抗平坦化層45形成於第一介電層30之凹部上。在凹部中，形成於基板10的第一介電層30頂面的高度低於在其他地方形成的第一介電層30頂面的高度，例如，在下方結構20上。特別是，凹部形成於基板10區域，其無下方結構20形成。在一些實施方式中，凹部的尺寸大於50nm2。
在一些實施方式中，下方結構20包含複數個圖案，例如，鰭狀結構、閘極結構或傳導性圖案，及設置於基板10的密集區。抗平坦化層45形成於粗糙區(實質地對應到凹部)上，此處複數個結構的密度小於門檻密度。在一實施方式中，門檻密度可由複數個結構間的間距來決定。例如，密集區為一區域其所在的相鄰下方圖案間的距離等於或小於門檻間距S1及粗糙區為一區域介於相鄰下方圖案之間，其距離大於門檻間距S1。在一些實施方式中，門檻間距S1為k×密集區中相鄰下方圖案間最小間距，此處k大於一(1)。在某些實施方式中，k為2、3、4或更多。
接著，如第6圖中所示，第二介電層60形成於抗平坦化層45及第一介電層30上。可使用相似於第一介電層30的材料及膜形成法以形成第二介電層60。在一些實施方式中，第二介電層60的厚度落於範圍自約50nm至約300nm，及在其他實施方式中，落於範圍自約100nm至約200nm。
如第7圖及第8圖中所示，對第二介電層60、抗平坦化層45及第一介電層30執行平坦化作業，例如回蝕作業或CMP。
蝕刻或研磨位於粗糙區(凹部)的第二介電層60比下方結構20上方的密集區還快。如第7圖中所示，在抗平坦化層45曝露後，由於抗平坦化層45 的蝕刻速度比第一及第二介電層還慢，在密集區及粗糙區的蝕刻速度可獲得平衡。結果，如第8圖中所示，比起未使用抗平坦化層的情況，平坦的第一介電層可帶有較為平坦的表面輪廓。換句話說，可降低所謂的“碟化效應(dishing effect)”。
在一些實施方式中，碟陷量H2，其為第一介電層30的最低頂面部分與近粗糙區第一介電層的最高頂面部分間高度的差異，當抗平坦化層45未使用時，碟陷量落於範圍自約15%至約30%。在某些實施方式中，碟陷量H2落於範圍約自1nm至約10nm。
第9圖係依據本揭露之一實施方式，顯示半導體裝置之例示性佈局結構。第9圖說明鰭狀結構及閘極結構(閘極電極)之例示性佈局結構，其形成一或多個鰭式場效電晶體(FinFETs)。
第9圖中的區域AR1，設置鰭狀結構200朝Y方向延伸，同時閘極結構250朝X方向延伸設置於鰭狀結構上，及第9圖中的區域AR2，設置鰭狀結構205朝X方向延伸，同時閘極結構255朝Y方向延伸設置於鰭狀結構上。進一步在區域AR3中，設置虛設閘極結構260，及在區域AR4中，設置虛設鰭狀結構210。在一實施方式中，區域AR3及AR4包含主動(非虛設)閘極結構及/或鰭狀結構。
在區域AR1及AR2中，鰭狀結構及/或閘極 結構分別以特定間距Sf及/或Sg做配置。在區域AR3及AR4中的虛設結構可具有相似的配置。相較而言，在區域AR5中，無設置鰭狀結構及閘極結構。
區域AR1及AR2間的距離D1及區域AR3及AR4間的距離D2為k×Sf或k×Sg，此處k大於一(1)。在某些實施方式中，k為2、3、4或更多。
第10-17圖係依據本揭露之一實施方式，顯示用於製造半導體裝置之例示性連續製程。第10-17圖顯示對應到第9圖中線X1-X1的例示性剖視圖。可使用相同或相似於第1-8圖的作業、製程、配置及/或材料於後續的實施方式中，及詳細的說明可被省略。
如第10圖中所示，遮罩層105形成於基板100上，由例如Si所製成。遮罩層的圖案對應至第9圖的鰭狀結構200及205。
如第11圖中所示，Si基板100利用遮罩層105做為蝕刻遮罩而被蝕刻出溝槽，藉以形成鰭狀結構200及205。
如第12圖中所示，接著，執行相似第2-6圖所述的作業，從而形成第一介電層300、第一抗平坦化層450及第二介電層500。第一抗平坦化層450設置於區域AR5中。
在一些實施方式中，第一抗平坦化層450形成於區域AR3之部分中，其無設置鰭狀結構。
如第13圖中所示，接著，執行相似第7及第8圖所述的作業，從而獲得平坦化的第一介電層300。在第13圖中，於平坦化作業後，曝露出鰭狀結構200、205之頂面。
然後，如第14圖中所示，第一介電層300凹陷使得自第一介電層300曝露出來的鰭狀結構之頂部，可被用作FinFET的通道。
如第15圖中所示，在鰭狀結構之頂部曝露之後，形成閘極結構250、255。
然後，如第16圖中所示，執行相似第2-6圖所述的作業，從而形成第三介電層350、第二抗平坦化層460及第四介電層550。第二抗平坦化層460設置於區域AR5中。在一些實施方式中，第二抗平坦化層460也形成於區域AR4之部分中，其無設置閘極結構。
接著，如第17圖中所示，執行相似於第7及第8圖所述的作業，從而獲得平坦化的第三介電層350。第17圖中，於平坦化作業後，曝露出閘極結構250、255之頂面。
第18圖及第19圖係依據本揭露另一實施方式，顯示用於製造半導體裝置之例示性連續製程。可使用相同或相似於第1-17圖的作業、製程、配置及/或材料於後續的實施方式中，及詳細的說明可被省略。
在此實施方式中，如第18圖及第19圖中所示，進行電漿處理70以修改第一介電層30之頂面。氨氣(NH3)及氮氣(N2)可用作電漿處理的氣體來源。電漿處理可包含直接電漿或遠距離電漿於約100℃至約400℃之溫度，小於100Torr之壓力下。
藉由電漿處理，第一介電層30中，深度約10nm至100nm的頂面部分被修改成抗平坦化層42。在一些實施方式中，抗平坦化層42的厚度落於範圍自約20nm至約50nm。
第20圖及第21圖係依據本揭露另一實施方式，顯示用於製造半導體裝置之例示性連續製程。
在此實施方式中，使用離子佈植將氮引進第一介電層30的表面。如第20圖中所示，遮罩圖案55具有開口形成於如第2圖中的結構上。然後，氮離子(或離子包含氮)75佈植入第一介電層30的表面。如第21圖中所示，藉由離子佈植，第一介電層30中，深度約10nm至100nm的頂面部分被修改成抗平坦化層44。在一些實施方式中，抗平坦化層44的厚度落於範圍自約20nm至約50nm。
在此所述的各種實施方式或實施例提供許多勝過現存技術的優點。例如，在本揭露中，由於抗平坦化層形成於一部分中其無下方圖案，可降低碟化效應。
應將理解的是，並非所有的優點須在此 討論，無特定優點用於限定所有實施方式或實施例，及其他實施方式或實施例可提供不同的優點。
依據本揭露之一實施態樣，用於製造半導體裝置的方法中，第一介電層形成於設置於基板上之下方結構上。抗平坦化層形成於第一介電層上。第二介電層形成於第一介電層及抗平坦化層上。對第二介電層、抗平坦化層及第一介電層執行平坦化作業。抗平坦化膜由異於第一介電層之材料所製成。
依據本揭露之另一實施態樣，用於製造半導體裝置的方法中，鰭狀結構形成於基板之第一區域上。基板進一步包含第二區域其中未形成鰭狀結構。第一介電層形成於第一區域中之鰭狀結構及基板之第二區域上。第一抗平坦化層形成於第二區域中之第一介電層上。第二介電層形成於第一介電層及第一抗平坦化層上。對第二介電層、第一抗平坦化層及第一介電層執行第一平坦化作業。抗平坦化膜由異於第一介電層之材料所製成。
依據本揭露之另一實施態樣，半導體裝置包含設置於基板上之下方結構，及設置於下方結構及基板上之介電層。基板包含第一區域其下方結構以小於門檻間距的間距設置及第二區域其無設置下方結構。相鄰第二區域間的距離等於或多於門檻間距。絕緣材料層由異於介電層之材料所製成設置 於第二區域中，及未形成於第一區域中。
前文概述數個實施例之特徵以使得熟習該項技術者可更好地理解本揭露之態樣。熟習該項技術者應瞭解，可容易地將本揭露內容用作設計或修改用於實現相同目的及/或達成本文引入之實施例的相同優點之其他製程及結構之基礎。熟習該項技術者亦應認識到，此類等效物構造不違背本揭露內容之精神及範疇，且可在不違背本揭露內容之精神及範疇之情況下於此作出各種變化、替代以及變更。
10‧‧‧基板
20‧‧‧下方結構
30‧‧‧第一介電層
45‧‧‧抗平坦化層

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  1. 一種製造半導體裝置之方法，其特徵在於，包含：形成一第一介電層於設置於一基板上之一下方結構上；形成一抗平坦化層於該第一介電層上；形成一第二介電層於該第一介電層及該抗平坦化層上；以及對該第二介電層、該抗平坦化層及該第一介電層執行一平坦化作業，其中該抗平坦化層係由異於該第一介電層之材料所製成。
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