TW201535643A - 半導體裝置及方法 - Google Patents

半導體裝置及方法 Download PDF

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TW201535643A
TW201535643A TW103145032A TW103145032A TW201535643A TW 201535643 A TW201535643 A TW 201535643A TW 103145032 A TW103145032 A TW 103145032A TW 103145032 A TW103145032 A TW 103145032A TW 201535643 A TW201535643 A TW 201535643A
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dielectric layer
semiconductor device
layer
hard mask
width
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TW103145032A
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TWI536520B (zh
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Ming-Hui Chu
Chih-Yuan Ting
Jyu-Horng Shieh
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Taiwan Semiconductor Mfg Co Ltd
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Abstract

提供一種形成半導體裝置的方法。金屬互連件形成於半導體裝置之介電層中。硬遮罩用以避免製造時常面臨之問題，例如當介層窗與溝槽之間有重疊時，產生橋接不同導電元件的可能性以及介層窗圖案化的問題。硬遮罩經過多次蝕刻以擴展介層窗置放窗，同時保持導電元件間的距離以避免橋接問題。

Description

半導體裝置及方法
本發明是關於一種製造半導體裝置的系統及方法，特別是有關於一種製作半導體裝置中之金屬互連件的系統及方法。
為符合摩爾定律(Moore’s Law)，半導體製造商面臨無盡的探索。製造商一直致力於持續地減少零件尺寸，例如主動及非主動裝置、互連線之寬度和厚度以及功率消耗。此外，為增加裝置密度、導線密度以及操作頻率作出了極大的努力。
這些挑戰使得半導體產業設計出若干突破以製造不同的邏輯電路，例如微處理器及隨機存取記憶體晶片(random access memory chip)。目前，業界面臨的挑戰為提出更好的互連件及介電質，以彌補裝置之功能所面臨的瓶頸。針對互連件，製造商利用具有較好之電及熱傳導性之金屬。舉例而言，以銅線代替基於鋁或鋁合金之材料。銅具有較低之電阻率，較高之熱傳導率及電遷移壽命，消除許多與鋁相關之問題，且較適合用於低功率、低電壓及高速的應 用。然而，製作銅互連件也有困難之處。由於缺乏揮發性銅化合物，銅無法以先前技術之用於鋁並大獲成功之光阻遮罩及電漿蝕刻而被圖案化。此外，銅會擴散至許多介電材料，使得銅佈線的製作過程複雜化。製造商需創造全新的圖案化製程，此舉導致引進所謂的鑲嵌及雙鑲嵌製程。在鑲嵌的過程中，將介電質用習知方法圖案化以界定溝槽(trench)及介層窗(via)。接著，將銅用電鍍沉積，隨後藉由化學機械研磨去除多餘的銅。
另一種改善裝置功能的方法係引入低介電常數材料。此種介電質之介電常數的降低係由降低極化性、降低密度、引入孔隙或其組合而達成。由於介電常數的降低通常係以製作金屬互連件所需之有用的材料性能為代價而達成，這對製造商帶來了進一步的整合挑戰。
因此，目前需要於低介電常數材料製作金屬互連佈線的改進方法，其可解決半導體產業所面臨的一些挑戰。
在一實施方式，一種半導體裝置包含基板以及位於基板上之第一導電元件。第一導電元件包含具有二階梯式結構之第一側壁。第一導電元件可更包含具有單階梯式結構之第二側壁。
在一實施方式，一種半導體裝置包含基板、位於基板上之介電層以及位於介電層中之第一導電元件。第一 導電元件可具有第一寬度、第二寬度以及第三寬度。第一寬度、第二寬度以及第三寬度彼此不同。
在一實施方式，一種形成半導體裝置之方法包含設置硬遮罩層於第二介電層上，且第二介電層位於第一介電層上。接著，對硬遮罩層執行第一蝕刻以去除一部分之硬遮罩層並形成第一開口。對硬遮罩層執行第二蝕刻以加寬硬遮罩層中之第一開口，並形成加寬硬遮罩層。執行第三蝕刻，其中將第二介電層以及該第一介電層蝕刻以於第一介電層中形成第二開口。執行第四蝕刻，其中用加寬硬遮罩層將第二介電層以及第一介電層蝕刻以於第一介電層中形成第三開口。接著，導電元件形成於第一介電層之第三開口中。
100‧‧‧半導體裝置
101‧‧‧基板
103‧‧‧裝置
105‧‧‧金屬化層
107‧‧‧第一介電層
109‧‧‧第二介電層
111‧‧‧硬遮罩層
113‧‧‧第一光阻層
201‧‧‧第一凹槽
301‧‧‧第二光阻層
401‧‧‧第二凹槽
403‧‧‧第三凹槽
405‧‧‧第一階
501‧‧‧第三光阻層
503‧‧‧介層窗開口
601‧‧‧第二階
603‧‧‧第三階
605‧‧‧溝槽開口
701‧‧‧導電元件
801‧‧‧第一導電元件
803‧‧‧第二導電元件
805‧‧‧第一側壁
807‧‧‧第二側壁
D1‧‧‧第一深度
D2‧‧‧第二深度
D3‧‧‧第三深度
D4‧‧‧介層窗臨界尺寸
D5‧‧‧覆蓋規格
D6‧‧‧額外遮罩間隔尺寸
D7‧‧‧半節距尺寸
W1‧‧‧第一寬度
W2‧‧‧第二寬度
W3‧‧‧第三寬度
W4‧‧‧第四寬度
H1‧‧‧第一高度
H2‧‧‧第二高度
H3‧‧‧第三高度
為更充分了解本實施方式及其優點，請參照下述之詳細說明並伴隨相關圖式，其中：第1A至7B圖係簡化之上視圖及剖視圖繪示根據一實施方式之半導體裝置的製作過程。
第8圖係簡化之部分剖視圖繪示根據一實施方式之半導體裝置。
除非特別敘明，不同圖示中相對應之數字及符號大致上代表相對應之部分。圖示係用以清楚說明實施例之相對外觀，且不一定按照比例繪製。
以下詳細敘述了本實施方式之製造及使用。然而，本揭露提供多個可應用之發明觀點，其可被實施於各種特定內容。以下敘述之特定實施方式僅說明製造及使用所揭露之主題的特定方式，並不限制不同實施方式的範圍。
提供於集成電路之金屬化層形成金屬特徵的方法，並說明製造實施方式之中間階段。
請參照第1A及1B圖，其分別為半導體裝置100的上視圖及部分剖視圖(沿第1A圖之BB’剖線)。半導體裝置100可包括基板101、位於基板上之裝置103、裝置103上之金屬化層105、金屬化層105上之第一介電層107、第一介電層107上之第二介電層109、第二介電層109上之硬遮罩層111以及硬遮罩層111上之第一光阻層113。基板101可包含摻雜或未摻雜的本體矽或絕緣體上矽(silicon-on-insulator，SOI)基板之主動層。一般而言，SOI基板包含一層半導體材料，例如矽、鍺，矽鍺、SOI、絕緣體上矽鍺(silicon germanium on insulator，SGOI)或其組合。其它可用之基板包括多層基板(multi-layered substrate)、梯度基板(gradient substrate)或混合式方向基板(hybrid orientation substrate)。
第1B圖所示之裝置103為單個電晶體。然而，裝置103可包含多種主動及/或非主動裝置，例如電晶體、二極體、電容、電阻、電感器及類似物，其可用以產生半導體裝置100之設計所需的結構性及功能性需求。裝置103可用任何合適之方法形成於基板101之內或其表面上。本領域 具通常知識者應當了解前述所提供之實例係用以進一步說明一些示例性實施方式的應用，並不以任何形式限定本揭露。
金屬化層105係形成於基板101及裝置103上，且係設計用以連接各種裝置103以形成功能電路。雖然第1B圖僅繪示單層，金屬化層105係由介電材料及導電材料之交替層所形成，且可由任何合適之方法形成(例如沉積、鑲嵌、雙鑲嵌等)。金屬化層105的確切數目係取決於半導體裝置100之設計。
第一介電層107可包含二氧化矽、低介電常數材料(low-K dielectric material，即具有介電常數比二氧化矽低的材料)，例如氮氧化矽(silicon oxynitride)、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼磷矽玻璃(borophosphosilicate glass，BPSG)、氟矽玻璃(fluorinated silicate glass，FSG)、有機矽酸鹽玻璃(organosilicate glass，OSG)、含氧碳化矽(SiOxCy)、旋塗式玻璃(Spin-On-Glass)、旋塗式聚合物(Spin-On-Polymer)、矽碳材料(silicon carbon material)、其複合材料、其組合或類似物，且可通過任何合適的方法沉積，例如旋塗(spin-on)、化學氣相沉積(chemical vapor deposition，CVD)以及電漿輔助化學氣相沈積(plasma-enhanced CVD，PECVD)或類似方法。亦可使用上述材料之多孔性版本。這些提供之材料及製程係作為實例，亦可使用其他材料及製程。根據一實施方式，第 一介電層107可作為層間介電質(interlayer dielectric，ILD)。第一介電層107可被形成為厚度介於約50奈米(nm)至約900nm之間，例如約為100nm。
根據一實施方式，第二介電層109作為蓋(cap)或蝕刻終止層(etch stop layer，ESL)。一般而言，蝕刻中止層提供一種機制用以在形成介層窗及/或接觸窗時，停止蝕刻製程。在一實施方式，第二介電層109係由具有與相鄰層不同之蝕刻選擇性的介電材料所形成，相鄰層例如硬遮罩層111(於以下說明)。第二介電層109可包含SiN、SiCN、SiCO、CN、其組合或類似物，且可通過CVD、PECVD或類似方法沉積。第二介電層109可被形成為厚度介於約5nm至約100nm之間，例如約為45nm。
硬遮罩層111係作為蝕刻製程之輔助工具(於以下伴隨第7A及7B圖說明)。在一實施方式，硬遮罩層111可包含氮化物(例如氧氮化矽或氮化矽)、金屬(例如鈦氮化物或鈦氧化物)、其組合或類似物。硬遮罩層111可通過任何合適的方法形成，例如CVD、低壓化學氣相沉積(Low-pressure CVD)、PECVD、物理氣相沉積(physical vapor deposition，PVD)或類似方法。硬遮罩層111可被形成為厚度介於約5nm至約50nm之間，例如約為20nm。
第一光阻層113係用以形成欲轉移至硬遮罩層111的圖案。在一實施方式，第一光阻層113係通過先沉積第一光阻層113於硬遮罩層111上，然後可暴露於圖案化的輻射，例如紫外光或通過標線片(未繪示)之準分子雷射 (excimer laser)所形成及圖案化。加溫烘烤(bake)或固化(cure)操作可被執行，且顯影劑(developer)可用以去除第一光阻層113之曝光或未曝光部分，其取決於欲使用正光阻或負光阻。因此，用以於半導體裝置100中形成溝槽的圖案形成於第一光阻層113。此處所述之第一光阻層113的特定圖案係僅用於說明目的，其它圖案可根據半導體裝置100的設計而形成。
請參照第2A及2B圖，硬遮罩層111經過第一次蝕刻，舉例而言，係用各向異性乾式蝕刻法以去除硬遮罩層111之曝光部分。此蝕刻進一步於第二介電層109中形成具有與第一光阻層113相似圖案之第一凹槽201。在一實施方式，第一凹槽201被形成為具有深度D1介於約1nm至約30nm之間，例如約為5nm。在一實施方式，硬遮罩層111可具有相對於第二介電層109約2至約10倍的蝕刻選擇性，例如約為4。接著，第一光阻層113被去除，舉例而言，係利用灰化法結合濕式清潔法。
請參照第3A及3B圖，第二光阻層301沉積於半導體裝置100上用於硬遮罩層111之第二蝕刻，以擴展第二介電層109中之介層窗置放窗(via landing window)。第二光阻層301經沉積、曝光及顯影以於硬遮罩層111中形成圖案，藉以移除部份之具有第一寬度W1之硬遮罩層111，第一寬度W1介於約7nm至約100nm之間，例如約為23nm。然而，如上所述，第一寬度W1僅欲作為說明性示例。
在另一實施方式，第一寬度W1可用例如電腦模 擬而決定。舉例而言，一旦已經設計第一光阻層113之圖案，可進行成型(modeling)以確保製程符合所需之設計規格。若不符合，例如具有比所欲之介層窗置放窗小，可於製程中設計並包括第二光阻層301，以減輕第一光阻層113之原設計所造成之任何負面影響。
第4A及4B圖係繪示第二光阻層301經曝光及顯影後，且硬遮罩層111經第二蝕刻以擴展介層窗置放窗。第二蝕刻可為各向異性乾式蝕刻法或類似方法以蝕刻硬遮罩層111以及第二介電層109。在一實施方式，第二凹槽401、第三凹槽403以及第一階405(位於第二凹槽401與第三凹槽403之間)形成於第二介電層109中。第二介電層109中之第二凹槽401被形成為具有第二深度D2，其介於約1nm至約30nm之間，例如約為5nm。第二介電層109中之第三凹槽403被形成為具有第三深度D3，其介於約2nm至約60nm之間，例如約為10nm。
第二介電層109中之第一階405被形成為具有第一高度H1。第一高度H1與第三深度D3及第二深度D2之間的差值相等，且可介於約1nm至約30nm之間，例如約為5nm。在一實施方式，硬遮罩層111之第二蝕刻係在第二蝕刻時間t2內執行，其係少於、等於或多於第一蝕刻時間t1。接著，第二光阻層301被去除，舉例而言，係利用灰化法結合濕式清潔法。
第5A及5B圖係繪示第三光阻層501之配置。第三光阻層501經圖案化、曝光及顯影以輔助第一介電層107 中之介層窗開口(via opening)503的圖案。此外，藉由加寬之硬遮罩層111(於以上伴隨第3A及3B圖說明)，介層窗可被形成為具有第二寬度W2，其介於約10nm至約70nm之間，例如約為23nm。第5A圖所示之第三光阻層501的特定圖案係僅用於說明目的以進一步說明一些示例性實施方式的應用，並不以任何形式限定本揭露。
第二介電層109及第一介電層107被蝕刻以圖案化第一介電層107中之介層窗開口503。在一實施方式，蝕刻可如第5B圖所示，停止於第一介電層107內。在另一實施方式，蝕刻可延伸至抵達金屬化層105。接著，第三光阻層501被去除，舉例而言，係利用灰化法結合濕式清潔法。
第6A及6B圖係繪示於後續蝕刻製程使用加寬硬遮罩層111以擴展介層窗開口503，並暴露金屬化層105之導電區域。由於硬遮罩層111之高蝕刻選擇性，第一介電層107及第二介電層109可被蝕刻而不顯著地改變硬遮罩層111。此外，在同一蝕刻製程中，第二介電層109及第一介電層107被蝕刻以圖案化第一介電層107中之溝槽開口605。第一介電層107被蝕刻直至抵達金屬化層105。第一介電層107之蝕刻選擇性相對於第二介電層109可介於約1至約4倍，例如約為2。
第6B圖另示出於蝕刻製程中，示於第4B圖的第二介電層109內之第一階405轉變成第一介電層107內之第二階601。此外，如第6B圖所示，第三階603於蝕刻製程中在第一介電層107內形成。第一介電層107內之第二階601 被形成為具有第二高度H2，其介於約5nm至約50nm之間，例如約為13nm。第一介電層107內之第三階603被形成為具有第三高度H3，其介於約20nm至約100nm之間，例如約為80nm。
第6A圖另示出硬遮罩層111內開口的間隔。在一實施方式，這些間隔可用於決定硬遮罩層111內之最小及最大的間隔。舉例而言，硬遮罩層111之最小間隔尺寸可藉由增加介層窗臨界尺寸D4至所欲覆蓋規格(overlayer specification)D5而決定。在一具體的實施方式中，介層窗臨界尺寸D4可介於約10nm至約90nm，例如可約為23nm，且覆蓋規格D5可介於約0nm至約15nm，例如可約為6nm。因此，最小間隔尺寸至少部分取決於製造技術。在一實施方式，硬遮罩層111之最小間隔尺寸可介於約10nm至約50nm，例如可約為35nm。硬遮罩層111之最大間隔尺寸可視情況而定，以保持額外遮罩間隔尺寸D6大於或等於硬遮罩層111之開口間的半節距尺寸(half pitch dimension)D7。額外遮罩間隔尺寸D6可介於約7nm至約100nm，例如可約為23nm，且半節距尺寸D7可介於約5nm至約40nm，例如可約為23nm。因此，最大間隔尺寸至少部分取決於製造技術。在一實施方式，硬遮罩層111之最大間隔尺寸可介於約7nm至約100nm，例如可約為23nm。
第7A及7B圖係繪示導電元件701形成於第一介電層107內。此外，導電元件701可包含一個或多個阻障/黏著層(未繪示)以保護導電元件701免於擴散或金屬中 毒。阻障層可包含鈦、氮化鈦、鉭、氮化鉭或其它替代物。阻障層可用PVD、CVD或類似方法形成。阻障層之厚度可介於約20埃(Å)至約200Å。然而，本領域具通常知識者應當瞭解說明書中所記載之尺寸係與用以形成集成電路之形成技術有關，且將會隨著形成技術之尺度化而縮小。
導電元件701之材料可包含銅或銅合金。然而，導電元件701可包含其它導電材料，例如銀、金、鎢、鋁及類似物。在一實施方式，形成阻障層及導電元件701之步驟可包括毯覆式形成阻障層、沉積導電材料之薄晶種層以及填充導電材料至溝槽及介層窗，例如利用電鍍。接著，執行化學機械研磨(chemical mechanical planarization，CMP)以去除多餘之阻障層及導電材料。
在前述之實施方式中，硬遮罩層111經第二蝕刻而被加寬。改良式硬遮罩層111可用以改善半導體裝置100之性能。尤其是，加寬硬遮罩層111可改善介層窗開口表現，並保持漏窗(leakage window)打開同時避免不同導電元件間可能產生之橋接，此係因為製造過程中所用之弱光阻劑。
請參照第7B圖，一個或多個導電元件701可被形成以具有第二寬度W2、第三寬度W3以及第四寬度W4。在一實施方式，第三寬度W3可介於約10nm至約120nm，例如約為20nm，且第四寬度W4可介於約7nm至約120nm，例如約為40nm。
第8圖係繪示一實施例具有第一導電元件801 以及第二導電元件803。在此實施方式中，第一導電元件801係根據前述伴隨第1A至7B圖說明之步驟所形成。尤其是，如前述伴隨第1A至4B圖之說明，第一導電元件801係由硬遮罩層111經兩次蝕刻所形成。如此一來，第一導電元件801之第一側壁805顯示出具有第二高度H2之第二階601以及具有第三高度H3之第三階603。因此，第一導電元件801之第一側壁805顯示出二階梯式結構。
第8圖另示出第二導電元件803，其非由硬遮罩層111經兩次蝕刻所形成。反而，於如前述伴隨第1A至2B圖說明之硬遮罩層111之第一蝕刻後，對第二介電層109以及第一介電層107執行介層窗蝕刻，為了第二導電元件803而不加寬硬遮罩層111。第二導電元件803之第二側壁807顯示出溝槽側壁平滑地過渡至介層窗側壁。此種過渡使第二導電元件803之第二側壁807具有單階梯式結構。
在一實施方式，一種半導體裝置包含基板以及位於基板上之第一導電元件。第一導電元件包含具有二階梯式結構之第一側壁。第一導電元件可更包含具有單階梯式結構之第二側壁。
在一實施方式，一種半導體裝置包含基板、位於基板上之介電層以及位於介電層中之第一導電元件。第一導電元件可具有第一寬度、第二寬度以及第三寬度。第一寬度、第二寬度以及第三寬度彼此不同。
在一實施方式，一種形成半導體裝置之方法包含設置硬遮罩層於第二介電層上，且第二介電層位於第一介 電層上。接著，對硬遮罩層執行第一蝕刻以去除一部分之硬遮罩層並形成第一開口。對硬遮罩層執行第二蝕刻以加寬硬遮罩層中之第一開口，並形成加寬硬遮罩層。執行第三蝕刻，其中將第二介電層以及該第一介電層蝕刻以於第一介電層中形成第二開口。執行第四蝕刻，其中用加寬硬遮罩層將第二介電層以及第一介電層蝕刻以於第一介電層中形成第三開口。接著，導電元件形成於第一介電層之第三開口中。
雖然本發明已參照示例性的實施例進行說明，這些敘述並不旨在具有限制意義的解讀。對於本領域的技術人員參照本案說明書後，示例性實施例之各種修飾或組合，以及本發明之其它實施例將是顯而易見的。因此，應當了解所附申請專利範圍涵蓋任何此種修改或實施例。
100‧‧‧半導體裝置
101‧‧‧基板
103‧‧‧裝置
105‧‧‧金屬化層
107‧‧‧第一介電層
701‧‧‧導電元件
W2‧‧‧第二寬度
W3‧‧‧第三寬度
W4‧‧‧第四寬度

Claims (20)

  1. 一種半導體裝置，包含：一基板；以及一第一導電元件，位於該基板上，該第一導電元件包含一具有二階梯式結構之第一側壁。
  2. 如請求項1所述之半導體裝置，更包含一不同於該第一導電元件之第二導電元件位於該基板上，該第二導電元件包含一具有單階梯式結構之第二側壁。
  3. 如請求項1所述之半導體裝置，其中該二階梯式結構包含一具有第一高度之第一階以及一具有第二高度之第二階，其中該第一高度大致相等於該第二高度。
  4. 如請求項1所述之半導體裝置，其中該二階梯式結構包含一具有第一高度之第一階以及一具有第二高度之第二階，其中該第一高度不同於該第二高度。
  5. 如請求項4所述之半導體裝置，其中該第一高度介於約5奈米至約20奈米之間。
  6. 如請求項5所述之半導體裝置，其中該第二高度介於約5奈米至約20奈米之間。
  7. 如請求項1所述之半導體裝置，其中該第一導電元件包含一具有單階梯式結構之第二側壁。
  8. 一種半導體裝置，包含：一基板；一介電層，位於該基板上；以及一第一導電元件，位於該介電層中，該第一導電元件具有一第一寬度、一第二寬度以及一第三寬度，其中該第 一寬度、該第二寬度以及該第三寬度彼此不同。
  9. 如請求項8所述之半導體裝置，更包含一不同於該第一導電元件之第二導電元件位於該介電層中，該第二導電元件具有一第四寬度以及一第五寬度，其中該第四寬度與該第五寬度不同。
  10. 如請求項8所述之半導體裝置，更包含一不同於該第一導電元件之第二導電元件位於該介電層中，該第二導電元件具有一直形側壁。
  11. 如請求項8所述之半導體裝置，其中該第一寬度介於約10奈米至約70奈米之間。
  12. 如請求項11所述之半導體裝置，其中該第二寬度介於約10奈米至約120奈米之間。
  13. 如請求項12所述之半導體裝置，其中該第三寬度介於約7奈米至約120奈米之間。
  14. 一種形成半導體裝置之方法，該方法包含：設置一硬遮罩層於一第二介電層上，且該第二介電層位於一第一介電層上；對該硬遮罩層執行一第一蝕刻以去除一部分之該硬遮罩層並形成複數個第一開口；對該硬遮罩層執行一第二蝕刻以加寬該硬遮罩層中之該些第一開口，該第二蝕刻形成一加寬硬遮罩層。執行一第三蝕刻，其中該第三蝕刻將該第二介電層以及該第一介電層蝕刻以於該第一介電層中形成複數個第二開口； 執行一第四蝕刻，其中該第四蝕刻用該加寬硬遮罩層將該第二介電層以及該第一介電層蝕刻以於該第一介電層中形成複數個第三開口；以及形成複數個導電元件於該第一介電層之該些第三開口中。
  15. 如請求項14所述之方法，其中於該第二蝕刻與該第四蝕刻之間執行該第三蝕刻。
  16. 如請求項14所述之方法，其中該第三蝕刻係用一光阻遮罩執行。
  17. 如請求項14所述之方法，其中將一導電材料電鍍至該第一介電層之該些第三開口中。
  18. 如請求項14所述之方法，其中該第四蝕刻於該第一介電層中形成一第一階以及一第二階。
  19. 如請求項18所述之方法，其中該第一階具有一第一高度，且該第二階具有該第一高度。
  20. 如請求項18所述之方法，其中該第一階具有一第一高度，該第二階具有一第二高度，且該第一高度與該第二高度不同。
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