CN107230636A - 制造半导体装置的方法 - Google Patents

制造半导体装置的方法 Download PDF

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Publication number
CN107230636A
CN107230636A CN201611044666.2A CN201611044666A CN107230636A CN 107230636 A CN107230636 A CN 107230636A CN 201611044666 A CN201611044666 A CN 201611044666A CN 107230636 A CN107230636 A CN 107230636A
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dielectric layer
layer
planarization
exposure
region
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吴俊毅
李亮峣
蔡宗杰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在一种制造半导体装置的方法中，第一介电层形成于设置于基板上的下方结构上。抗平坦化层形成于第一介电层上。第二介电层形成于第一介电层及抗平坦化层上。对第二介电层、抗平坦化层及第一介电层执行平坦化作业。抗平坦化层由异于第一介电层的材料所制成。

Description

制造半导体装置的方法
技术领域
本发明实施例是关于一种半导体集成电路，特别是关于一种包含平坦化作业的半导体装置的制造方法，例如化学机械研磨。
背景技术
随着半导体产业进展到纳米技术制程节点以寻求较高装置密度、较高表现及较低成本的关系，来自制造及设计方面的挑战驱使着三维设计的发展，例如鳍式场效晶体管(Fin FET)。Fin FET装置典型来说包含附有高深宽比的半导体鳍片及于其中形成半导体晶体管装置的通道及源极/漏极区。栅极形成于并沿着鳍装置的侧边(例如，包覆)，利用增加通道及源极/漏极区的表面积的优点以生产较快、较可靠及较好控制的半导体晶体管装置。一或多个层间介电(介电)层形成于鳍状结构及/或栅极结构上，及对介电层执行平坦化作业，例如化学机械研磨制程。
发明内容
本揭露一实施态样是提供一种制造半导体装置的方法，包含：形成一第一介电层于设置于一基板上的下方结构上；形成一抗平坦化层于第一介电层上；形成一第二介电层于第一介电层及抗平坦化层上；以及对第二介电层、抗平坦化层及第一介电层执行一平坦化作业，其中抗平坦化层是由异于第一介电层的材料所制成。
附图说明
当结合附图阅读以下详细描述时将更好地理解本揭露内容的态样。但须强调的是，依照本产业的标准做法，各种特征未按照比例绘制。事实上，各种特征的尺寸为了清楚的讨论而可被任意放大或缩小。
图1-8是依据本揭露的一实施方式，显示用于制造半导体装置的例示性连续制程；
图9是依据本揭露的一实施方式，显示半导体装置的例示性布局结构；
图10-17是依据本揭露的一实施方式，显示用于制造半导体装置的例示性连续制程；
图18及图19是依据本揭露的另一实施方式，显示用于制造半导体装置的例示性连续制程；
图20及图21是依据本揭露的另一实施方式，显示用于制造半导体装置的例示性连续制程。
具体实施方式
本揭露接下来将会提供许多不同的实施方式或实施例以实施本揭露中不同的特征。各特定实施例中的组成及配置将会在以下作描述以简化本揭露。这些为实施例仅作为示范并非用于限定本揭露。例如，元件的尺寸并非限定于揭露的范围或数值，但可取决于制程条件及/或理想的装置特性。此外，叙述中一第一特征形成于一第二特征之上可包含实施例中的第一特征与第二特征直接接触，亦可包含第一特征与第二特征之间更有其他额外特征形成介于第一及第二特征间，使第一特征与第二特征无直接接触。为了简单及清晰，各种特征可任意地以不同比例绘制。
进一步，空间关系的用语像是“下方”、“之下”、“较低”、“上方”、“较高”及类似用语，可用于此处以便描述附图中一元件或特征与另一元件与特征之间的关系。这些相对空间关系的用语是为了涵盖除了附图所描述的方向以外，元件于使用或操作中的各种不同的方向。装置可另有其他导向方式(旋转90度或朝其他方向)，此时的空间相对关系也可依上述方式解读。此外，用语像是“由…所制成”可意味着“包含”或“由…组成”。
图1-8是依据本揭露的一实施方式，说明用于制造半导体装置的例示性连续制程。图1-8说明用于制造一种介电层的例示性连续制程，其形成于下方结构及基板上。下方结构包含，例如，鳍状结构、栅极结构、金属配线及其组成。图1-8中，关于下方结构及/或任何额外元件的详细说明被简化或省略。
如图1中所示，下方结构20设置于基板10上。图2中，第一介电层30形成于下方结构20及未设置下方结构的基板10区域上。第一介电层30由例如，一或多层氧化硅为基底的绝缘材料所制成，例如SiO2、TEOS(硅酸乙酯)、BPSG(硼磷硅玻璃)或低介电系数(low-k)介电材料。低介电系数介电材料具有k值(介电常数)低于约4.0。一些低介电系数介电材料具有k值低于约3.5及可具有k值低于约2.5。
用于第一介电层30的材料可包含元素Si、O、C及/或H，例如SiCOH及SiOC。有机材料例如聚合物可用于第一介电层30。例如，第一介电层30由一或多层含碳材料、有机硅玻璃、含成孔剂材料及/或其组合所制成。
第一介电层30可利用例如，等离子增强化学气相沉积(PECVD)、低压CVD(LPCVD)、可流动式CVD、原子层CVD(ALCVD)及/或旋转技术来形成。在一些实施方式中，第一介电层30的厚度落于范围自约500nm至约1500nm。
接着，如图3中所示，抗平坦化膜利用PECVD、LPCVD或其他适合的膜形成法形成于第一介电层30上。抗平坦化膜40包含具有于后续平坦化作业中(例如，化学机械研磨(CMP))蚀刻速率低于第一介电层30的材料。在一些实施方式中，抗平坦化膜包含一或多层氮化硅为基底的绝缘材料，例如SiN、SiON或SiCN、碳化硅(SiC)或铝为基底的绝缘材料，例如AlO或AlON。在一些实施方式中抗平坦化膜40的厚度落于范围自约50nm至约300nm，及在其他实施方式中落于范围自约100nm至约200nm。
如图4及图5中所示，图案化制程，包含对抗平坦化膜40进行微影及蚀刻制程以获得抗平坦化层45。在一些实施方式中，如图4中所示，遮罩层50，例如光阻层或硬遮罩层，形成于抗平坦化膜40上。接着，如图5中所示，对抗平坦化膜40进行蚀刻以获得抗平坦化层45。
如图5中所示，抗平坦化层45形成于第一介电层30的凹部上。在凹部中，形成于基板10的第一介电层30顶面的高度低于在其他地方形成的第一介电层30顶面的高度，例如，在下方结构20上。特别是，凹部形成于基板10区域，其无下方结构20形成。在一些实施方式中，凹部的尺寸大于50nm2。
在一些实施方式中，下方结构20包含多个图案，例如，鳍状结构、栅极结构或传导性图案，及设置于基板10的密集区。抗平坦化层45形成于粗糙区(实质地对应到凹部)上，此处多个结构的密度小于门槛密度。在一实施方式中，门槛密度可由多个结构间的间距来决定。例如，密集区为一区域其所在的相邻下方图案间的距离等于或小于门槛间距S1及粗糙区为一区域介于相邻下方图案之间，其距离大于门槛间距S1。在一些实施方式中，门槛间距S1为k×密集区中相邻下方图案间最小间距，此处k大于一(1)。在某些实施方式中，k为2、3、4或更多。
接着，如图6中所示，第二介电层60形成于抗平坦化层45及第一介电层30上。可使用相似于第一介电层30的材料及膜形成法以形成第二介电层60。在一些实施方式中，第二介电层60的厚度落于范围自约50nm至约300nm，及在其他实施方式中，落于范围自约100nm至约200nm。
如图7及图8中所示，对第二介电层60、抗平坦化层45及第一介电层30执行平坦化作业，例如回蚀作业或CMP。
蚀刻或研磨位于粗糙区(凹部)的第二介电层60比下方结构20上方的密集区还快。如图7中所示，在抗平坦化层45曝露后，由于抗平坦化层45的蚀刻速度比第一及第二介电层还慢，在密集区及粗糙区的蚀刻速度可获得平衡。结果，如图8中所示，比起未使用抗平坦化层的情况，平坦的第一介电层可带有较为平坦的表面轮廓。换句话说，可降低所谓的“碟化效应(dishing effect)”。
在一些实施方式中，碟陷量H2，其为第一介电层30的最低顶面部分与近粗糙区第一介电层的最高顶面部分间高度的差异，当抗平坦化层45未使用时，碟陷量落于范围自约15％至约30％。在某些实施方式中，碟陷量H2落于范围约自1nm至约10nm。
图9是依据本揭露的一实施方式，显示半导体装置的例示性布局结构。图9说明鳍状结构及栅极结构(栅极电极)的例示性布局结构，其形成一或多个鳍式场效晶体管(FinFETs)。
图9中的区域AR1，设置鳍状结构200朝Y方向延伸，同时栅极结构250朝X方向延伸设置于鳍状结构上，及图9中的区域AR2，设置鳍状结构205朝X方向延伸，同时栅极结构255朝Y方向延伸设置于鳍状结构上。进一步在区域AR3中，设置虚设栅极结构260，及在区域AR4中，设置虚设鳍状结构210。在一实施方式中，区域AR3及AR4包含主动(非虚设)栅极结构及/或鳍状结构。
在区域AR1及AR2中，鳍状结构及/或栅极结构分别以特定间距Sf及/或Sg做配置。在区域AR3及AR4中的虚设结构可具有相似的配置。相较而言，在区域AR5中，无设置鳍状结构及栅极结构。
区域AR1及AR2间的距离D1及区域AR3及AR4间的距离D2为k×Sf或k×Sg，此处k大于一(1)。在某些实施方式中，k为2、3、4或更多。
图10-17是依据本揭露的一实施方式，显示用于制造半导体装置的例示性连续制程。图10-17显示对应到图9中线X1-X1的例示性剖视图。可使用相同或相似于图1-8的作业、制程、配置及/或材料于后续的实施方式中，及详细的说明可被省略。
如图10中所示，遮罩层105形成于基板100上，由例如Si所制成。遮罩层的图案对应至图9的鳍状结构200及205。
如图11中所示，Si基板100利用遮罩层105作为蚀刻遮罩而被蚀刻出沟槽，借以形成鳍状结构200及205。
如图12中所示，接着，执行相似图2-6所述的作业，从而形成第一介电层300、第一抗平坦化层450及第二介电层500。第一抗平坦化层450设置于区域AR5中。
在一些实施方式中，第一抗平坦化层450形成于区域AR3的部分中，其无设置鳍状结构。
如图13中所示，接着，执行相似第7及图8所述的作业，从而获得平坦化的第一介电层300。在图13中，于平坦化作业后，曝露出鳍状结构200、205的顶面。
然后，如图14中所示，第一介电层300凹陷使得自第一介电层300曝露出来的鳍状结构的顶部，可被用作FinFET的通道。
如图15中所示，在鳍状结构的顶部曝露的后，形成栅极结构250、255。
然后，如图16中所示，执行相似图2-6所述的作业，从而形成第三介电层350、第二抗平坦化层460及第四介电层550。第二抗平坦化层460设置于区域AR5中。在一些实施方式中，第二抗平坦化层460也形成于区域AR4的部分中，其无设置栅极结构。
接着，如图17中所示，执行相似于图7及图8所述的作业，从而获得平坦化的第三介电层350。图17中，于平坦化作业后，曝露出栅极结构250、255的顶面。
图18及图19是依据本揭露另一实施方式，显示用于制造半导体装置的例示性连续制程。可使用相同或相似于图1-17的作业、制程、配置及/或材料于后续的实施方式中，及详细的说明可被省略。
在此实施方式中，如图18及图19中所示，进行等离子处理70以修改第一介电层30的顶面。氨气(NH3)及氮气(N2)可用作等离子处理的气体来源。等离子处理可包含直接等离子或远距离等离子于约100℃至约400℃的温度，小于100Torr的压力下。
通过等离子处理，第一介电层30中，深度约10nm至100nm的顶面部分被修改成抗平坦化层42。在一些实施方式中，抗平坦化层42的厚度落于范围自约20nm至约50nm。
图20及图21是依据本揭露另一实施方式，显示用于制造半导体装置的例示性连续制程。
在此实施方式中，使用离子布植将氮引进第一介电层30的表面。如图20中所示，遮罩图案55具有开口形成于如图2中的结构上。然后，氮离子(或离子包含氮)75布植入第一介电层30的表面。如图21中所示，通过离子布植，第一介电层30中，深度约10nm至100nm的顶面部分被修改成抗平坦化层44。在一些实施方式中，抗平坦化层44的厚度落于范围自约20nm至约50nm。
在此所述的各种实施方式或实施例提供许多胜过现存技术的优点。例如，在本揭露中，由于抗平坦化层形成于一部分中其无下方图案，可降低碟化效应。
应将理解的是，并非所有的优点须在此讨论，无特定优点用于限定所有实施方式或实施例，及其他实施方式或实施例可提供不同的优点。
依据本揭露的一实施态样，用于制造半导体装置的方法中，第一介电层形成于设置于基板上的下方结构上。抗平坦化层形成于第一介电层上。第二介电层形成于第一介电层及抗平坦化层上。对第二介电层、抗平坦化层及第一介电层执行平坦化作业。抗平坦化膜由异于第一介电层的材料所制成。
依据本揭露的另一实施态样，用于制造半导体装置的方法中，鳍状结构形成于基板的第一区域上。基板进一步包含第二区域其中未形成鳍状结构。第一介电层形成于第一区域中的鳍状结构及基板的第二区域上。第一抗平坦化层形成于第二区域中的第一介电层上。第二介电层形成于第一介电层及第一抗平坦化层上。对第二介电层、第一抗平坦化层及第一介电层执行第一平坦化作业。抗平坦化膜由异于第一介电层的材料所制成。
依据本揭露的另一实施态样，半导体装置包含设置于基板上的下方结构，及设置于下方结构及基板上的介电层。基板包含第一区域其下方结构以小于门槛间距的间距设置及第二区域其无设置下方结构。相邻第二区域间的距离等于或多于门槛间距。绝缘材料层由异于介电层的材料所制成设置于第二区域中，及未形成于第一区域中。
根据本揭露的一实施例，其中形成抗平坦化层的方法包含：形成一抗平坦化膜于第一介电层上；以及图案化抗平坦化膜以形成抗平坦化层。
根据本揭露的一实施例，其中抗平坦化膜在平坦化作业中具有低于第一介电层的一蚀刻速率。
根据本揭露的一实施例，其中抗平坦化膜包含一或多者的SiN、SiON、SiCN、SiC、AlO及AlON。
根据本揭露的一实施例，其中形成抗平坦化层的方法包含通过导入氮气于第一介电层中以修改第一介电层的表面层。
根据本揭露的一实施例，其中：氮气是以含氮气体利用等离子将氮气导入第一介电层的表面，及形成抗平坦化层的方法进一步包含图案化此修改的表面层以形成抗平坦化层。
根据本揭露的一实施例，其中氮气是通过离子布植穿过形成于第一介电层上的遮罩图案的一开口导入第一介电层的表面层中。
根据本揭露的一实施例，其中抗平坦化层形成于第一介电层的一凹部上。
根据本揭露的一实施例，其中抗平坦化作业包含化学机械研磨作业。
根据本揭露的一实施例，其中：下方结构包含多个结构，抗平坦化层形成于一区域上，其多个结构的密度小于一门槛密度以及门槛密度可由多个结构间的一间距来决定。
本揭露另一实施态样是提供一种制造半导体装置的方法，包含：形成多个鳍状结构于一基板的一第一区域上，基板进一步包含一第二区域其无鳍状结构形成；形成一第一介电层于第一区域中的鳍状结构及基板的第二区域上；形成一第一抗平坦化层于第二区域中的第一介电层上；以及对第二介电层、第一抗平坦化层及第一介电层执行一第一平坦化作业，其中抗平坦化层由异于第一介电层的材料所制成。
根据本揭露的一实施例，其中形成第一抗平坦化层的方法包含：形成一第一抗平坦化膜于第一介电层上；以及图案化第一抗平坦化膜以形成第一抗平坦化层。
根据本揭露的一实施例，其中第一抗平坦化膜包含一或多者的SiN、SiON、SiCN、SiC、AlO及AlON。
根据本揭露的一实施例，其中鳍状结构之间以多个间距设置于第一区域中，这些间距等于或小于一第一门槛间距。
根据本揭露的一实施例，其中：两个第一区域设置于基板上带有第二区域穿插于其之间，及这些第一区域之间的一距离大于第一门槛间距。
根据本揭露的一实施例，进一步包含：形成多个栅极结构于基板的一第三区域上，基板进一步包含一第四区域其无栅极结构形成；形成一第三介电层于第三区域中的栅极结构及此基板的第四区域上；形成一第二抗平坦化层于第四区域中的第三介电层上；形成一第四介电层于第三介电层及第二抗平坦化层上；以及对第四介电层、第二抗平坦化层及第三介电层执行一平坦化作业。
根据本揭露的一实施例，其中栅极结构之间以多个间距设置于第三区域中，这些间距等于或小于一第二门槛间距。
根据本揭露的一实施例，其中：两个第三区域设置于基板上带有第四区域穿插于其之间，及第三区域之间的一距离大于第二门槛间距。
根据本揭露的一实施例，进一步包含：在第一平坦化作业的后，凹陷第一介电层使得鳍状结构的多个顶部曝露出来；形成多个栅极结构于曝露的鳍状结构上；形成一第三介电层于栅极结构、鳍状结构及基板的第二区域上；形成一第二抗平坦化层于第二区域中的第三介电层上；以及对第四介电层、第二抗平坦化层及第三介电层执行一平坦化作业。
本揭露又一实施态样是提供一种半导体装置，包含：多个下方结构设置于一基板上；以及一介电层设置于下方结构及基板上，其中：基板包含多个第一区域其以小于一门槛间距的一间距设置下方结构及多个第二区域其未设置下方结构，相邻的第二区域间的一距离等于或多于此门槛间距，及一绝缘材料层由异于介电层的材料所制成设置于第二区域中，及未形成于第一区域中。
前文概述数个实施例的特征以使得熟悉该项技术者可更好地理解本揭露的态样。熟悉该项技术者应了解，可容易地将本揭露内容用作设计或修改用于实现相同目的及/或达成本文引入的实施例的相同优点的其他制程及结构的基础。熟悉该项技术者亦应认识到，此类等效物构造不违背本揭露内容的精神及范畴，且可在不违背本揭露内容的精神及范畴的情况下于此作出各种变化、替代以及变更。

Claims (1)

1.一种制造半导体装置的方法，其特征在于，包含：
形成一第一介电层于设置于一基板上的一下方结构上；
形成一抗平坦化层于该第一介电层上；
形成一第二介电层于该第一介电层及该抗平坦化层上；以及
对该第二介电层、该抗平坦化层及该第一介电层执行一平坦化作业，其中该抗平坦化层是由异于该第一介电层的材料所制成。
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