TW201732974A - 雙面互連裝置上的穿矽通孔之製造和使用 - Google Patents

雙面互連裝置上的穿矽通孔之製造和使用 Download PDF

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TW201732974A
TW201732974A TW105138463A TW105138463A TW201732974A TW 201732974 A TW201732974 A TW 201732974A TW 105138463 A TW105138463 A TW 105138463A TW 105138463 A TW105138463 A TW 105138463A TW 201732974 A TW201732974 A TW 201732974A
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substrate
coupled
interconnect layers
layer
device layer
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TW105138463A
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TWI706479B (zh
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布倫南 穆勒
派翠克 摩洛
全箕玟
保羅 費雪
丹尼爾 潘圖索
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英特爾股份有限公司
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Abstract

一種設備，包含電路結構，其包含裝置層；一或多個導電互連層，其在該裝置層的第一側上且耦接到該電晶體裝置中的一些電晶體裝置；以及基板，其包含導電穿矽通孔，其耦接到該一或多個導電互連層，使得該一或多個互連層介於該穿矽通孔和該裝置層之間。一種方法，包含在基板上形成複數個電晶體裝置，該複數個電晶體裝置限定裝置層；在該裝置層的第一側上形成一或多個互連層；移除該基板的一部分；以及將穿矽通孔耦接到該一或多個互連層，使得該一或多個互連層被設置在該裝置層和該穿矽通孔之間。

Description

雙面互連裝置上的穿矽通孔之製造和使用
一種包含含有來自裝置背側的電連接的裝置之半導體裝置。
在過去的數十年中，積體電路中的特性縮放一直是不斷增長的半導體產業背後的驅動力。縮放到越來越小的特性使得能夠在半導體晶圓的有限面積上增加功能單元的密度。例如，縮小電晶體尺寸使得併入增加數量的晶片上的記憶體，導致製造具有增加的容量之產品。驅動了更大的容量，但也不是沒有問題。最佳化每個裝置的效能的必要性變得日益顯著。
100‧‧‧部件
110‧‧‧晶粒
115‧‧‧裝置層
120‧‧‧互連
130‧‧‧互連
135‧‧‧穿矽通孔(TSV)
140‧‧‧載體基板
150‧‧‧接觸點
190‧‧‧封裝基板
195‧‧‧基板
1150A‧‧‧第一側
1150B‧‧‧第二側
200‧‧‧部件
210‧‧‧晶粒
215‧‧‧裝置層
220‧‧‧互連
225‧‧‧基板
230‧‧‧互連
235‧‧‧TSV
240‧‧‧載體基板
250‧‧‧接觸點
290‧‧‧封裝基板
2150A‧‧‧第一側
2150B‧‧‧第二側
300‧‧‧結構
310‧‧‧基板
320‧‧‧緩衝層
325‧‧‧閘極
330‧‧‧鰭
340A‧‧‧源極
340B‧‧‧汲極
350‧‧‧間隔物
355A‧‧‧介電材料
355B‧‧‧介電材料
355C‧‧‧介電材料
355D‧‧‧最終的介電層
370A‧‧‧互連
370B‧‧‧互連
375A‧‧‧接觸
375B‧‧‧接觸
381‧‧‧介電材料
382‧‧‧開口
385‧‧‧接觸點
386‧‧‧接觸
390‧‧‧互連
397‧‧‧接觸點
3000‧‧‧裝置層
3100‧‧‧互連
400‧‧‧結構
410‧‧‧基板
415‧‧‧表面
420‧‧‧TSV
430‧‧‧介電層
435‧‧‧介電層
440‧‧‧再分配層
500‧‧‧裝置結構
510‧‧‧半導體基板
597‧‧‧接觸點
5000‧‧‧裝置層
5100‧‧‧互連
5200‧‧‧互連
610‧‧‧基板
620‧‧‧TSV
630‧‧‧介電層
635‧‧‧介電層
640‧‧‧再分配層
710‧‧‧部件
720‧‧‧TSV
725‧‧‧焊料接合
730‧‧‧封裝基板
735‧‧‧接觸墊
740‧‧‧焊料接合
750‧‧‧晶粒
810‧‧‧部件
820‧‧‧TSV
825‧‧‧焊料接合
830‧‧‧封裝基板
835‧‧‧接觸墊
840‧‧‧直接金屬到金屬接合
850‧‧‧晶粒
910‧‧‧部件
920‧‧‧TSV
925‧‧‧焊料接合
930‧‧‧封裝基板
935‧‧‧接觸墊
945‧‧‧佈線接合
1000‧‧‧中介層
1002‧‧‧第一基板
1004‧‧‧第二基板
1006‧‧‧球閘陣列(BGA)
1008‧‧‧金屬互連
1010‧‧‧通孔
1012‧‧‧穿透矽通孔(TSV)
1014‧‧‧嵌入式裝置
1100‧‧‧計算裝置
1102‧‧‧積體電路晶粒
1104‧‧‧處理器
1106‧‧‧晶粒上記憶體
1108‧‧‧通訊晶片
1110‧‧‧揮發性記憶體
1112‧‧‧非揮發性記憶體
1114‧‧‧圖形處理單元
1116‧‧‧數位訊號處理器
1120‧‧‧晶片組
1122‧‧‧天線
1124‧‧‧觸控螢幕顯示器
1126‧‧‧觸控螢幕控制器
1128‧‧‧電池
1130‧‧‧羅盤
1132‧‧‧運動協同處理器或感測器
1134‧‧‧揚聲器
1136‧‧‧相機
1138‧‧‧用戶輸入裝置
1140‧‧‧大容量儲存裝置
1142‧‧‧加密處理器
1144‧‧‧全球定位系統(GPS)裝置
圖1顯示包含連接到封裝基板的積體電路晶片或晶粒的部件的實施例的橫截面示意性側視圖。
圖2顯示包含連接到封裝基板的積體電路晶 片或晶粒的部件的另一實施例的橫截面示意性側視圖。
圖3顯示半導體或半導體上絕緣體(SOI)基板的一部分，例如，晶圓上的積體電路晶粒或晶片的一部分的頂側透視圖，並顯示形成於其上具有到電晶體裝置的閘極電極和汲極的互連的三維電晶體裝置。
圖4顯示倒置並與載體基板對準的圖3的裝置基板的橫截面側視圖。
圖5顯示在圖3的裝置基板接合到載體基板之後圖4的結構。
圖6顯示在移除或薄化裝置基板以暴露電晶體的鰭的第二側或背側之後與將該鰭凹陷之後圖5的結構。
圖7A-7B顯示在電晶體裝置的鰭的凹陷之後圖6的結構的橫截面側視圖。
圖8A-8B顯示在利用通孔或開口將鰭的背側上的介電材料沉積和圖案化到電晶體裝置的源極的背側之後圖7A-7B的結構。
圖9A-9B顯示在磊晶生長用於用於背側接面形成的材料之後圖8A-8B的結構。
圖10A-10B顯示在利用諸如鎢的導電接觸材料填充介電材料中的通孔開口之後圖9A-9B的結構。
圖11A-11B顯示圖10A-10B的結構並顯示連接於到作為例如第一背側互連或金屬層的一部分的源極的接觸之互連。
圖12顯示在多個互連層以及用於將結構連接到裝置層的第二側或背側上的外部來源的接觸點的形成之後圖6的結構。
圖13顯示在將載體基板薄化以暴露穿過矽通孔之後圖12的結構。
圖14顯示根據形成組件的第二實施例的包含接合到載體基板裝置側下的多個裝置的裝置層的裝置基板。
圖15顯示在移除或薄化裝置基板以暴露裝置層的第二側或背側之後圖14的結構。
圖16顯示在形成用於將結構連接到裝置層的第二側或背側上的外部來源的多個互連層和接觸點之後圖15的結構。
圖17顯示將載體基板薄化之後圖16的結構。
圖18顯示在形成穿過載體基板到裝置層的第一側上的互連的接觸點的TSV之後圖17的結構。
圖19顯示包含如上面參照圖1描述的被接合到封裝基板的部件之總體的橫截面側視圖。
圖20顯示包含如上面參照圖1描述的被接合到封裝基板的部件之總體的另一實施例的橫截面側視圖。
圖21顯示包含如上面參照圖1描述的被接合到封裝基板的部件之總體的進一步實施例的橫截面側視圖。
圖22是實現一或多個實施例的中介層。
圖23顯示計算裝置的實施例。
【發明內容與實施方式】
未來的電路裝置，諸如中央處理單元裝置，將期望高效能裝置和低電容、整合在單一晶粒或晶片中的低功率裝置。本文描述的實施例係針對積體電路結構，其包含裝置層中的平面或非平面半導體裝置(例如，三維裝置)，該裝置層具有該裝置層的每一側上的一或多個互連或佈線層，以及落在該等佈線層其中一者上的一或多個穿矽通孔(TSV)。在一個實施例中，一種裝置包含電路結構，該電路結構包含裝置層，該裝置層包含複數個電晶體裝置，每個電晶體裝置包含第一側和相對的第二側；在該裝置層的第一側上並且連接到該電晶體裝置中的一些電晶體裝置的一或多個導電互連層；以及基板，包含連接到該結構的第一側上的一或多個導電互連層的導電TSV，使得該一或多個互連層在該TSV和該裝置層之間。在另一個實施例中，揭露了一種系統，包含：封裝基板，其包含電源連接和連接到該封裝基板的晶粒。在一個實施例中，該晶粒包含裝置層和包含連接到互連層的TSV的基板，使得互連層在TSV和連接到裝置層的第二側(背側或下側)的裝置層之間。也揭露了一種形成電路結構的方法。
圖1顯示包含連接到封裝基板的積體電路晶片或晶粒的部件的一個實施例的橫截面示意性側視圖。部 件100包含晶粒110，晶粒110包括含有多個裝置(例如，電晶體裝置)的裝置層或層115。裝置層115包含表示層的第一側的第一側1150A和與第一側1150A相對的第二側或背側1150B。電晶體裝置包含邏輯電路和可選的一或多個功率電晶體。在第一側1150A上連接到晶粒110的裝置層115的是互連120，在一個實施例中，互連120包含但不限於從第一側1150A連接到裝置層115的裝置的多個導電金屬線。互連中包含的是控制電路互連和/或電源互連(VDD、閘控VDD和VSS)。金屬線的各個列由介電材料(例如，層間介電質(ILD))分隔。在本實施例中，穿過裝置層115的第二側1150B電連接到裝置層115的裝置的是互連130。在一個實施例中，至少在一些情況下，互連130包含與裝置層115的裝置連接的一或多列金屬層中的電源互連和/或控制電路互連。金屬線的各個列由介電材料(例如，層間介電質(ILD))隔開。圖1也顯示設置在互連130之下的載體基板140(如圖所示)。在一個實施例中，如將在下面描述的，在邏輯電路的兩側上形成具有金屬層的晶粒110的程序中，載體基板140被接合到互連130(更具體地，介電材料絕緣金屬層)。穿過基板140設置的是一或多個穿矽通孔(TSV)135。圖1顯示連接到在裝置層115的第二側1150B上的互連130的TSV 135。TSV 135的相對側可用於與基板195(例如，封裝或其他裝置)電氣和實體連接，諸如藉由焊料連接或金屬對金屬(例如，銅對銅)連接。圖1也顯示連接到接 觸點150(例如，焊料凸塊)的互連120中的一些，接觸點150可操作以將晶粒110連接到基板190，諸如封裝190。圖1進一步代表性地顯示VDD和VSS經由封裝基板190連接到晶粒110。可以理解，接觸點150不限於VDD和VSS連接，但可以包含其它連接(例如，I/O連接)。
圖2顯示包含連接到封裝基板的積體電路晶片或晶粒的部件的另一實施例的橫截面示意性側視圖。部件200包含晶粒210，晶粒210包括含有多個裝置(例如，電晶體裝置)的裝置層或層215。裝置層215包含表示層的第一側的第一側2150A和與第一側2150A相對的第二側或背側2150B。在本實施例中，裝置層215的第二側2150B係連接到基板225。基板225例如是半導體材料，諸如矽、鍺或者其它材料或適合在一個實施例中形成薄型裝置的其它一或多種材料。裝置層215的電晶體裝置包含邏輯電路和可選的一或多個功率電晶體。也可以可選地包含其他類型的電晶體或裝置(例如，嵌入式記憶體)。在一個實施例中，在第一側2150A上連接到晶粒210的裝置層215的是互連220，互連220包含但不限於從第一側2150A連接到裝置層215的裝置的多個導電金屬線或金屬層。互連中包含的是控制電路互連和/或電源互連(VDD、閘控VDD和VSS)。金屬線的各個列由介電材料(例如，層間介電質(ILD))分隔。在本實施例中，穿過裝置層的第二側2150B連接到裝置層215的裝置中的一些的是包含一或多列金屬線的互連230。在一個實施例 中，互連230包含電源互連和/或邏輯電路互連。互連230包含穿過基板225連接到TSV 245的電接點，其連接到裝置層215的裝置(例如裝置的背側)。
如圖所示，在裝置層215的第二側2150B上的互連230下方設置有載體基板240。在一個實施例中，以在裝置層的兩側上的金屬層形成晶粒210的程序中，載體基板240被接合到互連230。穿過載體基板240設置的是一或多個TSV 235。TSV係連接到裝置層215的第二側2150B上的互連230。TSV 235的相對側可用於電氣和實體連接到基板295，諸如封裝或裝置。圖2也顯示在裝置層215的第一側2150A上的這種互連220中的一些是連接到可操作以將晶粒210連接到封裝290的接觸點250(例如，焊料凸塊)。圖2進一步代表性地顯示VDD和VSS藉由封裝基板290連接到晶粒210。
圖3-13描述形成類似於在圖1中的晶粒110的晶粒的方法或程序，其包含在裝置層的相對側上的一或多個互連，與落在該一或多個互連中的一個的一或多個TSV，使得該一或多個互連在TSV和裝置層之間。在一個實施例中，在裝置層中使用的裝置是三維金屬氧化物半導體場效電晶體(MOSFET)。應當理解，在其他實施例中，其他形式的裝置(例如，平面裝置、奈米線裝置)是合適的。良好的開放式聲明。
圖3顯示半導體或半導體上絕緣體(SOI)基板的一部分，例如，晶圓上的積體電路晶粒或晶片的一部 分的頂側透視圖。具體地，圖3顯示包含矽或SOI的基板310的結構300。覆蓋基板310是可選的緩衝層320。在一個實施例中，緩衝層310是矽鍺材料引入的，在一個實施例中，其藉由生長技術在基板310上。代表性地，緩衝層320(如果存在)具有大約幾百奈米(nm)等級的代表性厚度。
在圖3所示的實施例中，設置在基板310和可選的緩衝層320的表面上(如圖所示的上表面)是電晶體裝置，諸如N型電晶體裝置或P型電晶體裝置的一部分。在本實施例中，N型或P型電晶體裝置的共有部分是設置在緩衝層320的表面上的本體或鰭330。在一個實施例中，鰭330係由半導體材料或多於一種半導體材料，諸如矽、矽鍺或III-V族或IV-V族半導體材料所形成。在一個實施例中，鰭330的材料係根據用於形成三維積體電路裝置的傳統處理技術形成的。代表性地，半導體材料係在基板上磊晶地生長，接著形成為鰭330(例如，藉由掩模和蝕刻程序)。
在一個實施例中，鰭330具有大於高度尺寸H的長度尺寸L。代表性的長度範圍係在10奈米(nm)至1毫米(mm)的數量級，代表性的高度範圍係在5nm至200nm的數量級。鰭330也具有寬度W，其代表性地在4nm至10nm的數量級。如圖所示，鰭330是從基板310的表面延伸或在基板310的表面上(或可選地從緩衝層320或在緩衝層320上)延伸的三維體。如在圖3所示 的三維體為具有如圖所示的從緩衝層320的表面突出的相對側(第一和第二側面)的矩形體。應當理解，在處理這樣的物體時，可能無法利用可用的工具實現真正的矩形形狀，並且可能導致其他形狀。代表性的形狀包含但不限於梯形形狀(例如，基部寬於頂部)和拱形形狀。
在圖3中的結構的實施例中，設置在鰭330上的是閘級堆疊。在一個實施例中，閘極堆疊包含，例如，二氧化矽或介電常數大於二氧化矽的介電材料(高k介電材料)的閘極介電層。在一個實施例中，設置在閘極介電層上的是，例如，金屬的閘極325。閘極堆疊可以包含在其相對側上的介電材料的間隔物350。用於間隔物350的代表性材料是低k材料，諸如氮化矽(SiN)或氮化矽碳(SiCN)。圖3顯示可選的間隔物350相鄰於閘極堆疊的側壁且在鰭330上。在閘極堆疊的相對側形成在鰭330上或之中的是接面(源極340A和汲極340B)。
在一個實施例中，為了形成三維電晶體結構，閘極介電材料係在鰭330上形成，諸如藉由毯式沉積，接著沉積沉積犧牲或虛設閘極材料的方式。在該結構上方引入掩模材料，並將掩模材料圖案化以在指定的通道區域上保護閘極堆疊材料(具有犧牲或虛設閘極材料的閘極堆疊)。接著使用蝕刻程序來移除不想要的區域中的閘極堆疊材料，並在指定的通道區域上將閘極堆疊圖案化。接著形成間隔物350。形成間隔物350的一種技術是在結構上沉積膜、在期望的區域中保護該膜，接著蝕刻以將該 膜圖案化成期望的間隔物尺寸。
在鰭330和間隔物350上形成包含犧牲或虛設閘極材料的閘極堆疊之後，在鰭330上或鰭330中形成接面(源極和汲極)。源極和汲極形成在閘極堆疊(閘極介電質上的犧牲閘極電極)的相對側上的鰭330之中或之上。在圖3所示的實施例中，源極340A和汲極340B是由磊晶生長源極和汲極材料而形成作為鰭330的部份上的包層。源極340A和汲極340B的代表材料包含但不限於矽、矽鍺或III-V族或IV-V族化合物半導體材料。源極340A和汲極340B可以替代地藉由移除鰭材料的部分並且在移除鰭材料的指定接面區中磊晶生長源極和汲極材料來形成。
在形成源極340A和汲極340B之後，在一個實施例中，犧牲或虛設閘極被移除並用閘極電極材料代替。在一個實施例中，在移除犧牲或虛設閘極堆疊之前，介電材料被沉積在該結構上。在一個實施例中，介電材料是沉積為覆蓋層的二氧化矽或低k介電材料，接著研磨以暴露犧牲或虛設閘極325。接著藉由例如蝕刻程序移除犧牲或虛設閘極和閘極介電質。
在移除犧牲或虛設閘極和閘極介電質之後，在閘極電極區域中形成閘極堆疊。引入例如沉積在結構上的閘極堆疊，包含閘極介電質和閘極電極。在實施例中，閘極電極堆疊的閘極電極325由金屬閘極構成，並且閘極介電質層由具有大於二氧化矽(高K材料)的介電常數的 介電常數的材料構成。例如，在一個實施例中，閘極介電層(圖3中的閘極電極325之下)由諸如但不限於氧化鉿、氧氮化鉿、矽酸鉿、氧化鑭、氧化鋯、矽酸鋯、氧化鉭、鈦酸鍶鋇、鈦酸鋇、鈦酸鍶、氧化釔、氧化鋁、氧化鉛鈧鉭、鈮酸鉛鋅或其組合的材料構成。在另一實施例中，閘極介電層可以包含多於一種的介電材料，諸如二氧化矽和高K材料，或者兩種不同的高K材料，或者其他設置的介電材料。在一個實施例中，閘極電極325由金屬層構成，諸如但不限於金屬氮化物、金屬碳化物、金屬矽化物、金屬鋁化物、鉿、鋯、鈦、鉭、鋁、釕、鈀、鉑、鈷、鎳或導電金屬氧化物。在另一實施例中，閘極電極可以包含多於一層的合適金屬或其它導電材料。在形成閘極堆疊之後，額外的二氧化矽或低k介電材料的介電材料介電材料沉積在三維電晶體裝置上(例如，ILD0上)，以將裝置結構封裝或嵌入在介電材料中。圖3顯示封裝三維電晶體裝置(例如，作為ILD0)的介電材料355A。
圖3顯示形成到三維電晶體裝置結構的互連之後的結構。在此實施例中，第一互連層或金屬層作為分別到閘極電極325和汲極340B的電連接。可以採用類似的技術來形成到源極340A的互連。代表性地，為了形成到閘極電極325的電接觸，最初藉由例如具有對於閘極電極325和汲極340B的掩模中的開口的掩模程序，從介電材料355A的頂表面(如圖所示)到閘極電極形成開口。介電材料355A被蝕刻以暴露閘極電極和汲極，接著掩模 材料被移除。接下來，將例如鎢的接觸材料引入開口中，並且填充開口以形成到閘極電極325的接觸375A和到汲極340B的接觸375B。接著介電材料355A的表面(如圖所示的頂表面)可以用導電晶種材料對其晶種化，並且用掩模材料對其圖案化，以限定用於具有暴露接觸375A和接觸375B的開口的互連路徑的開口。接著藉由電鍍程序引入諸如銅的導電材料以形成連接到閘極電極325的接觸375A的互連370A和連接到汲極340B的接觸375B的互連370B。互連370A和互連370B是第一互連或金屬層或層的一部分。接著可以移除掩蔽材料和不需要的晶種材料。在形成作為初始金屬層的互連之後，例如二氧化矽或低k介電材料的介電材料355B可以沉積為互連上和周圍的ILD1層。接著可以根據傳統程序形成額外的互連層。圖1顯示由多層互聯組成的晶粒110的訊號佈線120。在圖3中的互連370A和互連370B是代表性的一種，例如，第一最接近裝置層的這種層。從互連觀察，最終或頂層包含接觸點(例如，接觸墊)。圖3顯示最終的介電層355D，其具有形成於其中和/或其上的接觸385。在一個實施例中，接觸385被連接到一或多個底層互連或佈線層並且用類似於互連370的方式來形成。用於進一步討論的目的，圖3的結構的裝置層由裝置層3000所識別且裝置層3000的第一側(相對於基板310的一側)或裝置上的一或多個互連層由互連3100所識別。
圖4顯示在倒置或翻轉用於將結構連接到載 體並以下面的載體結構400對準該倒置的結構之後圖3的結構的放大圖示的橫截面側視圖。在此實施例中，載體結構是包含例如是矽基板的基板410的TSV晶圓。在此實施例中，基板410包含僅是部分TSV的導電材料(例如，電鍍銅)的TSV 420，在此意義上，它們從基板410的表面415延伸穿過小於基板410的整個厚度部分(例如，穿過基板的一半)。基板410也可以包含例如在表面415上形成的電路裝置。
圖5顯示在載體結構400的接合之後圖4的部件。在一個實施例中，該結構被接合，例如，在結構300的表面上的介電材料和結構400的半導體材料之間具有粘合劑。圖5顯示TSV 420藉由結構300的接觸點385直接連接互連3100。在有基板410的表面415上的一或多個電路裝置的實施例中，這種裝置也可以藉由接觸點385連接到互連3100。
圖6顯示將基板310移除或薄化以暴露裝置層3000的第二側或背側(暴露圖3中的鰭330的背側或下側)之後圖5的結構。在一個實施例中，基板310可以藉由諸如機械研磨或蝕刻程序的薄化製程被移除。在本實施例中，基板310被完全移除，以暴露裝置層3000的第二側或背側。為了形成諸如圖2中的晶粒210的晶粒，基板310會薄化，但一部分將保持。基板310從結構的第二側或背側的薄化可任選地凹陷或薄化裝置層3000的電晶體裝置的鰭的部分(見圖3)。
圖7A-7B顯示了到電晶體裝置的第二側或背側的接觸的形成的實施例。具體識別的是在圖6中由嵌入參考7-7'識別的電晶體裝置。該電晶體裝置包含到在類似於參考圖3所描述的裝置的裝置層的第一側或裝置側上的閘極電極和汲極的接觸。使用圖3的電晶體裝置作為參考，圖7A顯示穿過圖3的結構的線A-A'的倒置橫截面，並且圖7B顯示穿過圖3的結構的線B-B'的倒置橫截面。圖7A-7B顯示在移除基板310的可選的將鰭330凹陷之後的結構。在一個實施例中，為了將鰭330凹陷，蝕刻製程可利用蝕刻劑選擇性地朝向將相對於介電材料355A的鰭材料移除。或者，掩蔽材料可被圖案化在具有暴露鰭330的開口的介電材料355A(暴露的背側表面)的表面上。鰭330的材料可藉由例如蝕刻製程被移除以使鰭330凹陷，接著移除掩蔽材料。
圖8A和圖8B分別顯示，在鰭330的背側上的介電材料的沉積和圖案化之後，圖7A和圖7B的結構。圖8A-8B顯示例如藉由覆蓋沉積程序沉積的二氧化矽或低K介電材料的介電材料381。一旦沉積，可以藉由例如在介電材料381的表面上形成掩模材料來圖案化介電材料381，在此實施例中，在鰭330的相對側上具有與例如源極區相對的開口或通孔。圖8A顯示穿過對應於該鰭的源極區(源極340A)的鰭330的背側上定向的介電材料381的開口382。在本實施例中，圖8B顯示的是開口(例如，開口382)具有尺寸比鰭330的寬度尺寸大的直徑。 以此方式，鰭330的背側以及鰭330的側壁被暴露。圖8B也顯示穿過結構進行蝕刻以暴露源極340A的背側。
圖9A和圖9B分別顯示圖8A和圖8B在用於背側接面形成的材料磊晶生長之後的結構。材料的範例是諸如矽鍺或III-V族或IV-V族半導體材料的半導體材料。圖8A顯示在與源極340A的背側對準的區域中的開口382中的磊晶生長材料385。圖9B顯示在鰭330的側壁上磊晶生長，並與先前形成在該結構的第一側或裝置側的源極340連接的材料385。
圖10A和圖10B分別顯示在以諸如鎢的導電接觸材料來填充介電材料381中的通孔開口之後圖9A和9B的結構。圖10A顯示到與源極340相關的磊晶材料385的接觸386。圖10B顯示到磊晶材料385的接觸金屬386。圖10A和10B也顯示從裝置層的下側的結構的背側或第二側到源極340A的(經由接觸材料)連接。互連現在可以藉由，例如，上面關於裝置側互連(參見圖3和所伴隨的文本)所描述的技術來形成接觸386。
形成背側接面(源極)接觸的上述描述是一個實施例。應當理解，存在相較於在鰭上磊晶生長材料的其它方法。其它實施例包含但不限於藉由例如在摻雜劑中驅動來從背側改變鰭的區域。在另一實施例中，鰭330的側壁可以暴露在源極區中，並且諸如鎢的接觸材料可以被引入到這種側壁上。其中接觸材料也形成在源極的裝置側上(例如，在形成到閘極電極325的接觸375A和到汲極 340B的接觸375B的時刻形成這樣的接觸)，接觸可以在背側處理操作中延伸以形成到源極的環繞接觸。最後，形成背側源極接觸的描述不僅僅限於源極接觸，類似技術可以用於在期望之處形成背側汲極接觸。
圖11A和圖11B分別顯示圖10A和圖10B的結構和顯示連接到接觸386到源極340的互連390，作為，例如，第一背側互連或金屬層的一部分。圖11A-11B也顯示在沉積二氧化矽的介電材料355C或互連或金屬層上的低k介電材料之後的結構。
已經描述的第二側或背側接觸到裝置層3000的裝置的形成與該接觸到第一背側互連或金屬層或層級的連接，圖12顯示在多個互連層以及用於將結構連接到裝置層3000的第二側或背側上的外部來源的接觸點的形成之後圖6的結構。這些層的互連可以藉由電鍍程序形成。在一個實施例中，諸如銅的導電材料的這種互連可以摻雜有摻雜劑以改善電遷移。如圖所示，每個互連層係藉由介電材料與相鄰層隔開。接觸點397例如是可操作以將結構連接到諸如封裝基板的基板的接觸墊或C4凸塊。
圖13顯示在薄化基板410之後圖12的結構。在一個實施例中，基板410是藉由機械研磨或蝕刻程序薄化以露出基板410的背側上的TSV 420，於是這樣的TSV可用於電性連接到另一個裝置或基板。此結果類似於上述圖1的結構。在另一個實施例中，一旦TSV 420被暴露，再分配層被引入以再分配到基板410的背側上的TSV 420的連接點。圖13顯示，例如，電鍍銅選擇性的連接到TSV 420的再分配層440以及，例如，設置在介電層430和435之間的二氧化矽或高k介電材料。在另一個實施例中，除了或作為替代的再分配層，諸如二極體、電容器和/或電感器的電路裝置可以形成在基板410上且藉由TSV 420連接到互連3100(需要的地方)。
圖14-18描述形成類似於圖1中的晶粒110的晶粒的方法的另一實施例。參考圖14，圖中顯示接合到載體基板裝置側下的裝置晶圓。圖14顯示包含在裝置層的第一側或裝置側上的半導體基板510、裝置層5000和互連5100的裝置結構500。互連5100包含具有金屬層之間的介電材料的一或多層金屬層。
在圖14中所示的實施例中，裝置結構500接合到載體基板610。載體基板610為，例如，諸如晶圓或晶圓的部分的半導體(例如，矽)基板。載體基板610可選擇性地包含連接到裝置結構500的表面上的一或多個電路裝置(如，二極體、電容器、電感器)。圖14顯示在用，例如，結構互連5100的表面上的介電材料和和基板610的半導體材料之間的粘合劑接合之後裝置結構500的部件和載體基板。在實施例中，其中一或多個電路裝置係存在載體基板610上，這樣的電路裝置可被連接到裝置結構5100的接觸點，其被連接到互連5100。
圖15顯示在移除或薄化基板510以暴露裝置層5000的第二側或背側(例如，暴露裝置層5000的電晶 體裝置的鰭的背側或下側)之後圖14的結構。在一個實施例中，基板510可以藉由諸如機械研磨或蝕刻處理的薄化程序被移除。在本實施例中，基板510被完全移除以暴露裝置層5000的第二側或背側。從結構的第二側或背側薄化基板510可任選地凹陷或薄化裝置層5000的電晶體裝置的鰭的部分(參照圖3)。
圖16顯示在形成用於將結構連接到裝置層5000的第二側或背側上的外部來源的多個互連層和接觸點之後圖15的結構。互連5200包含藉由，例如，上面參照圖7A-10B所描述的技術而形成到裝置層5000的一或多個裝置的接觸。互連5200也包含由如上所述的(例如，參照圖11A-11B)電鍍程序形成的，例如，銅金屬層或線。在一個實施例中，這樣的諸如銅的導電材料的金屬層或線可以用摻雜劑進行摻雜以改進電遷移。如圖所示，各個金屬層係由介電材料與鄰接層分隔。接觸點597例如是可操作以將結構連接到諸如封裝基板的基板的C4凸起。
圖17顯示基板610薄化之後圖16的結構。在一個實施例中，基板610是藉由機械研磨或蝕刻程序被薄化到所需的厚度。圖18顯示在形成穿過基板610到互連5100的接觸點的TSV之後圖17的結構。代表性地，TSV 620可以對於所需的TSV，藉由掩蔽具有在基板的掩模周圍區域的開口的基板610的背側(如圖所示的底部側)來形成。基板610接著蝕刻穿過基板到互連5100的接觸點。這是在沉積導電材料(例如，電鍍銅)之後以形 成穿過基板610的TSV 620。結果是類似如上所述圖1的結構。在另一個實施例中，一旦TSV 620被形成，再分配層被引入以再分配到基板610的背側上的TSV 620的連接點。圖18顯示，例如，電鍍銅選擇性地連接到TSV 620的選擇性再分配層640以及，例如，設置在介電層630和635之間的二氧化矽或高k介電材料。在另一個實施例中，除了或作為替代的再分配層，諸如二極體、電容器和/或電感器的電路裝置可以形成在基板610上連接到互連5100(需要的地方)。
在如上參照圖1-18描述的載體基板中形成的TSV不消耗任何裝置半導體層，而是直接落在互連3100(見圖13)或互連5100(見圖18)之上。此外，由於在TSV和裝置(例如，電晶體)之間沒有側向相互作用，在裝置層中配置的先前技術“避開區域(keep out zones)”可以被消除或最小化。因此，由TSV和與裝置半導體層相關的周邊裝置佔據的相對較大的半導體區域可以被保留用於更多功能裝置(例如，電晶體)。可替代地，TSV尺寸可以放大。在這種情況下，因為扇出可能不是必要的，TSV本身可以用作接合焊墊，從而消除了額外的再分佈層的需要。這允許多種封裝選項。圖19至21顯示這樣的選項的範例。
圖19顯示包含如上面參照圖1描述的被接合到封裝基板的部件之總體的橫截面側視圖。部件710包含在裝置層的第一側上的第一互連，其包含藉由焊料接合 725連接到封裝基板730的接觸墊735的接觸墊。部件710的裝置層的第二側上的第二互連係連接到延伸穿過載體基板的TSV 720。TSV 720係藉由焊料接合740連接到晶粒750的接觸點，例如，在晶粒堆疊配置中的處理器、記憶體裝置、無線電裝置、感測器裝置、功率管理裝置。
圖20顯示包含如上面參照圖1描述的被接合到封裝基板的部件之總體的另一實施例的橫截面側視圖。部件810包含在裝置層的第一側上的第一互連，其包含藉由焊料接合825連接到封裝基板830的接觸墊835的接觸墊。部件810的裝置層的第二側上的第二互連係連接到延伸穿過部件之載體基板的TSV 820。TSV 820係藉由直接金屬到金屬接合840連接到晶粒850的接觸點，例如，在晶粒堆疊配置中的處理器、記憶體裝置、無線電裝置、感測器裝置、功率管理裝置。
圖21顯示包含如上面參照圖1描述的被接合到封裝基板的部件之總體的進一步實施例的橫截面側視圖。部件910包含在裝置層的第一側上的第一互連，其包含藉由焊料接合925連接到封裝基板930的接觸墊935的接觸墊。部件910的裝置層的第二側上的第二互連係連接到延伸穿過部件之載體基板的TSV 920。TSV 920藉由佈線接合945連接到封裝基板的接觸墊935的其他部分以例如提供額外的輸入/輸出埠。
圖22顯示包括一或多個實施例的中介層1000。中介層1000是用於將第一基板1002橋接到第二基 板1004的居間基板。第一基板1002可以是，例如，積體電路晶粒。第二基板1004可以是，例如，記憶體模組、電腦主機板，或另一積體電路晶粒。通常，中介層1000的目的是散佈連接到更寬的間距和/或重新路由連接到不同的連接。例如，中介層1000可以將積體電路晶粒耦接到可以隨後被耦接到第二基板1004的球閘陣列(BGA)1006。在一些實施例中，第一和第二基板1002/1004被附接到中介層1000的相對側。在其它實施例中，第一和第二基板1002/1004被附接到中介層1000的相同側。在進一步的實施例中，三個或更多的基板係藉由中介層1000的方式被互連。
中介層1000可以由環氧樹脂、玻璃纖維增強環氧樹脂、陶瓷材料或聚合物材料，如聚酰亞胺形成。在進一步的實現中，中介層可以由替代的可以包括上述在半導體基板中使用的相同材料，如矽、鍺以及其它III-V族和IV族的材料的剛性或柔性材料來形成。
中介層可以包括金屬互連1008和通孔1010，其包含但不限於穿透矽通孔(TSV)1012。中介層1000可以進一步包括嵌入式裝置1014，其包括被動和主動裝置。這樣的裝置包括但不限於電容、解耦電容、電阻、電感、熔斷器、二極體、變壓器、感測器和靜電放電(ESD)裝置。更複雜的裝置，如射頻(RF)裝置、功率放大器、功率管理裝置、天線、陣列、感測器和MEMS裝置也可以在中介層1000上形成。
根據實施例，本文揭露的設備或程序可以用於製造中介層1000。
圖23顯示根據本發明的一種實施例的計算裝置1100。計算裝置1100可以包括多個元件。在一個實施例中，這些元件被附接到一或多個主機板。在替代的實施例中，這些元件被製造到單一系統單晶片(SoC)晶粒上，而不是主機板上。在計算裝置1100中的元件包括但不限於積體電路晶粒1102以及至少一個通訊晶片1108。在一些實現中，通訊晶片1108被製造成積體電路晶粒1102的一部分。積體電路晶粒1102可包括CPU 1104以及經常被用作快取記憶體的晶粒上記憶體1106，其可以藉由如嵌入式DRAM(eDRAM)或自旋轉移力矩記憶體(STTM或STTM-RAM)的技術來提供。
計算裝置1100可包括可能會或可能不會物理地和電性地耦接到主機板或在SoC晶粒內製造的其他元件。這些其它元件包括但不限於揮發性記憶體1110(例如，DRAM)、非揮發性記憶體1112(例如，ROM或快閃記憶體)、圖形處理單元1114(GPU)、數位訊號處理器1116、加密處理器1142(在硬體中的執行加密演算法的專用處理器)、晶片組1120、天線1122、顯示器或觸控螢幕顯示器1124、觸控螢幕控制器1126、電池1128或其它電源、功率放大器(未顯示)、全球定位系統(GPS)裝置1144、羅盤1130、運動協同處理器或感測器1132(其可包括加速計、陀螺儀和羅盤)、揚聲器 1134、相機1136、用戶輸入裝置1138(如鍵盤、滑鼠、手寫筆和觸控板)和大容量儲存裝置1140(如硬碟、光碟(CD)、數位多功能光碟(DVD)等)。
通訊晶片1108致使進行資料的傳輸往來計算裝置1100的無線通訊。用語“無線”及其衍生物可以用於描述電路、裝置、系統、方法、技術、通訊通道等，其可以經由非固態媒體藉由使用調變的電磁輻射進行資料通訊。該用語不暗示關聯的裝置不包含任何導線，儘管在一些情況中可能不包含。通訊晶片1108可實現任何數目的無線標準或協定，其包括但不限於Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽，其衍生物以及那些被指定為3G、4G、5G和之後的任何其它無線協定。計算裝置1100可以包括複數個通訊晶片1108。例如，第一通訊晶片1108可專用於短範圍無線通訊，如Wi-Fi和藍芽，以及第二通訊晶片1108可專用於長範圍無線通訊，如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO和其它。
計算裝置1100的處理器1104包含一或多個裝置，諸如根據實施例形成的電晶體或金屬互連，其包含到裝置的背側接觸和背側金屬層以及包含TSV的載體基板以連接到裝置側或背側金屬層。用語“處理器”可以指處理來自暫存器和/或記憶體的電子資料，以轉換該電子資 料成可儲存在暫存器和/或記憶體中的其他電子資料的任何裝置或裝置的一部分。
通訊晶片1108也可以包含一或多個裝置，諸如根據實施例形成的電晶體或金屬互連，其包含到裝置的背側接觸和背側金屬層以及包含TSV的載體基板以連接到裝置側或背側金屬層。
在進一步的實施例中，容納在計算裝置1100內的另一個元件可以包含一或多個裝置，諸如根據實現形成的電晶體或金屬互連，其包含到裝置的背側接觸和背側金屬層以及包含TSV的載體基板以連接到裝置側或背側金屬層。
在各種實施例中，計算裝置1100可以是膝上電腦、小筆電、筆記型電腦、超輕薄筆電、智慧手機、平板電腦、個人數位助理(PDA)、極致行動PC、行動電話、桌上電腦、伺服器、列表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器或者數位錄影機。在另外的實現中，計算裝置1100可以是處理資料的任何其它電子裝置。
範例
範例1是一種設備，包含：電路結構，其包含裝置層，該裝置層包含複數個電晶體裝置，該複數個電晶體裝置各包含第一側和相對的第二側；一或多個導電互連層，其在該裝置層的第一側上且耦接到該電晶體裝置中 的一些電晶體裝置；以及基板，其包含導電穿矽通孔，其耦接到在該結構的第一側上的該一或多個導電互連層，使得該一或多個互連層介於該穿矽通孔和該裝置層之間。
在範例2中，範例1的設備中的該一或多個導電互連層包含一或多個第一互連層，該設備進一步包含在耦接到該電晶體裝置中的一些電晶體裝置的該裝置層的第二側上的一或多個第二互連層。
在範例3中，範例2的設備進一步包含設置在該裝置層的該第二側上的接觸點，其可操作以耦接到外部來源並耦接到該至少第二互連層。
在範例4中，範例1至3中任一個中的設備的該穿矽通孔包含耦接到該一或多個導電互連層的第一側和可操作以耦接到外部來源的第二側。
在範例5中，範例4的設備的該穿矽通孔的該第二側限定接觸墊。
在範例6中，範例4的設備進一步包含設置在該穿矽通孔的該第二側上的接觸墊，其可操作以耦接到外部來源並耦接到該穿矽通孔。
範例7是一種系統，包含：封裝基板，其包含電源連接；以及晶粒，其耦接到該封裝基板，該晶粒包含：(i)裝置層，其包含複數個電晶體裝置，該複數個電晶體裝置各包含第一側和相對的第二側；(ii)一或多個導電互連層，其在該裝置層的第一側上且耦接到該電晶體裝置中的一些電晶體裝置；以及(iii)基板，其包含導 電穿矽通孔，其耦接到在該結構的第一側上的該一或多個導電互連層，使得該一或多個互連層介於該穿矽通孔和該裝置層之間。
在範例8中，範例7的系統中的該一或多個導電互連層包含一或多個第一互連層，該設備進一步包含在耦接到該電晶體裝置中的一些電晶體裝置的該裝置層的第二側上的一或多個第二互連層。
在範例9中，範例8的系統進一步包含設置在該裝置層的該第二側上的接觸點，其可操作以耦接到外部來源並耦接到該至少第二互連層。
在範例10中，範例7至9中任一個的系統的該穿矽通孔包含耦接到該一或多個導電互連層的第一側和可操作以耦接到外部來源的第二側。
在範例11中，範例10的系統的該穿矽通孔的該第二側限定接觸墊。
在範例12中，範例10的系統進一步包含設置在該穿矽通孔的該第二側上的接觸墊，其可操作以耦接到外部來源並耦接到該穿矽通孔。
範例13是一種方法，包含：在基板上形成複數個電晶體裝置，該複數個電晶體裝置限定包含第一側和相對的第二側的裝置層，其中該第二側被耦接到該基板；在該裝置層的第一側上形成一或多個互連層，該一或多個互連層耦接到該複數個裝置中的一些電晶體裝置；移除該基板的一部分；以及將穿矽通孔耦接到該一或多個互連 層，使得該一或多個互連層被設置在該裝置層和該穿矽通孔之間。
在範例14中，範例13的方法中的該穿矽通孔係經由基板設置，並將該穿矽通孔耦接到該一或多個互連層包含將包含該穿矽通孔的該基板耦接。
在範例15中，在將該穿矽通孔耦接到該一或多個互連層之前，範例13至14中任一個的方法包含將基板耦接到該一或多個互連層且將該穿矽通孔耦接包含經由該基板形成該穿矽通孔。
在範例16中，移除範例13至15中任一個的方法中的該基板的一部分包含移除該基板的整個部分。
在範例17中，範例13至16中任一個的方法中的該一或多個互連層包含一或多個第一互連層，該方法進一步包含：在該裝置層的該第二側上形成至少一或多個第二互連層，其中該一或多個第二互連層係耦接到該複數個電晶體裝置中的一些電晶體裝置。
在範例18中，範例17的方法進一步包含在該裝置層的該第二側上形成接觸點，其可操作以耦接到外部來源並耦接到該一或多個第二互連層。
在範例19中，範例13至18中任一個的方法中的該穿矽通孔包含耦接到該一或多個互連層的第一側和第二側，其中該穿矽通孔的該第二側限定可操作以耦接到外部來源的接觸墊。
在範例20中，範例13至19中任一個的方法 進一步包含在該穿矽通孔的該第二側上形成接觸墊，其可操作以耦接到外部來源並耦接到該穿矽通孔。
上述的說明實現，包括在摘要中所描述的，並非意在窮舉或限制發明為所揭露的精確形式。雖然本發明在此描述的具體實現和範例用於說明性目的，那些相關領域技術人員將理解各種等同修改是可能在本發明的範圍之內的。
可以根據上述詳細說明來完成這些修飾。在下面的申請專利範圍中使用的用語不應當被解釋為限制本發明在說明書和申請專利範圍中揭露的具體實現。相對的，根據申請專利範圍詮釋的既定原則解釋，發明的範圍完全由下面的申請專利範圍來確定。
100‧‧‧部件
110‧‧‧晶粒
115‧‧‧裝置層
120‧‧‧互連
130‧‧‧互連
135‧‧‧穿矽通孔(TSV)
140‧‧‧載體基板
150‧‧‧接觸點
190‧‧‧封裝基板
195‧‧‧基板
1150A‧‧‧第一側
1150B‧‧‧第二側

Claims (20)

  1. 一種設備，包含：電路結構，其包含裝置層，該裝置層包含複數個電晶體裝置，該複數個電晶體裝置各包含第一側和相對的第二側；一或多個導電互連層，其在該裝置層的第一側上且耦接到該等電晶體裝置中的一些電晶體裝置；以及基板，其包含導電穿矽通孔，其耦接到在該結構的第一側上的該一或多個導電互連層，使得該一或多個互連層介於該穿矽通孔和該裝置層之間。
  2. 如申請專利範圍第1項的設備，其中該一或多個導電互連層包含一或多個第一互連層，該設備進一步包含在耦接到該等電晶體裝置中的一些電晶體裝置的該裝置層的第二側上的一或多個第二互連層。
  3. 如申請專利範圍第2項的設備，進一步包含設置在該裝置層的該第二側上的接觸點，其可操作以耦接到外部來源並耦接到該至少第二互連層。
  4. 如申請專利範圍第1項的設備，其中該穿矽通孔包含耦接到該一或多個導電互連層的第一側和可操作以耦接到外部來源的第二側。
  5. 如申請專利範圍第4項的設備，其中該穿矽通孔的該第二側限定接觸墊。
  6. 如申請專利範圍第4項的設備，進一步包含設置在該穿矽通孔的該第二側上的接觸墊，其可操作以耦接到 外部來源並耦接到該穿矽通孔。
  7. 一種系統，包含：封裝基板，其包含電源連接；以及晶粒，其耦接到該封裝基板，該晶粒包含：(i)裝置層，其包含複數個電晶體裝置，該複數個電晶體裝置各包含第一側和相對的第二側；(ii)一或多個導電互連層，其在該裝置層的第一側上且耦接到該等電晶體裝置中的一些電晶體裝置；以及(iii)基板，其包含導電穿矽通孔，其耦接到在該結構的第一側上的該一或多個導電互連層，使得該一或多個互連層介於該穿矽通孔和該裝置層之間。
  8. 如申請專利範圍第7項的系統，其中該一或多個導電互連層包含一或多個第一互連層，該設備進一步包含在耦接到該等電晶體裝置中的一些電晶體裝置的該裝置層的第二側上的一或多個第二互連層。
  9. 如申請專利範圍第8項的系統，進一步包含設置在該裝置層的該第二側上的接觸點，其可操作以耦接到外部來源並耦接到該至少第二互連層。
  10. 如申請專利範圍第7項的系統，其中該穿矽通孔包含耦接到該一或多個導電互連層的第一側和可操作以耦接到外部來源的第二側。
  11. 如申請專利範圍第10項的系統，其中該穿矽通孔的該第二側限定接觸墊。
  12. 如申請專利範圍第10項的系統，進一步包含設 置在該穿矽通孔的該第二側上的接觸墊，其可操作以耦接到外部來源並耦接到該穿矽通孔。
  13. 一種方法，包含：在基板上形成複數個電晶體裝置，該複數個電晶體裝置限定包含第一側和相對的第二側的裝置層，其中該第二側係耦接到該基板；在該裝置層的第一側上形成一或多個互連層，該一或多個互連層耦接到該複數個裝置中的一些電晶體裝置；移除該基板的一部分；以及將穿矽通孔耦接到該一或多個互連層，使得該一或多個互連層被設置在該裝置層和該穿矽通孔之間。
  14. 如申請專利範圍第13項的方法，其中該穿矽通孔係經由基板設置，並將該穿矽通孔耦接到該一或多個互連層包含將包含該穿矽通孔的該基板耦接。
  15. 如申請專利範圍第13項的方法，其中在將該穿矽通孔耦接到該一或多個互連層之前，該方法包含將基板耦接到該一或多個互連層且將該穿矽通孔耦接包含經由該基板形成該穿矽通孔。
  16. 如申請專利範圍第13項的方法，其中移除該基板的一部分包含移除該基板的整個部分。
  17. 如申請專利範圍第13項的方法，其中該一或多個互連層包含一或多個第一互連層，該方法進一步包含：在該裝置層的該第二側上形成至少一或多個第二互連層，其中該一或多個第二互連層係耦接到該複數個電晶體 裝置中的一些電晶體裝置。
  18. 如申請專利範圍第17項的方法，進一步包含在該裝置層的該第二側上形成接觸點，其可操作以耦接到外部來源並耦接到該一或多個第二互連層。
  19. 如申請專利範圍第13項的方法，其中該穿矽通孔包含耦接到該一或多個互連層的第一側和第二側，其中該穿矽通孔的該第二側限定可操作以耦接到外部來源的接觸墊。
  20. 如申請專利範圍第13項的方法，進一步包含在該穿矽通孔的該第二側上形成接觸墊，其可操作以耦接到外部來源並耦接到該穿矽通孔。
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