CN108292626A - 在双侧互连器件上制作和使用穿硅过孔 - Google Patents

在双侧互连器件上制作和使用穿硅过孔 Download PDF

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Publication number
CN108292626A
CN108292626A CN201580084799.XA CN201580084799A CN108292626A CN 108292626 A CN108292626 A CN 108292626A CN 201580084799 A CN201580084799 A CN 201580084799A CN 108292626 A CN108292626 A CN 108292626A
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coupled
interconnection
substrate
silicon via
layer
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CN108292626B (zh
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B·K·米勒
P·莫罗
K·俊
P·B·菲舍尔
D·潘图索
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Intel Corp
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Intel Corp
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Abstract

一种装置包括：电路结构，所述电路结构包括器件层；在器件层的第一侧上并且耦合到晶体管器件中的多个晶体管器件的一个或多个导电互连级；以及衬底，所述衬底包括耦合到所述一个或多个导电互连级的导电穿硅过孔，使得所述一个或多个互连层位于所述穿硅过孔和所述器件层之间。一种方法，包括：在衬底上形成多个晶体管器件，所述多个晶体管器件限定器件层；在所述器件层的第一侧上形成一个或多个互连级；去除衬底的一部分；以及将穿硅过孔耦合到所述一个或多个互连级，使得所述一个或多个互连级位于所述器件层和所述穿硅过孔之间。

Description

在双侧互连器件上制作和使用穿硅过孔
技术领域
包括器件的半导体装置包括与器件背侧的电连接。
背景技术
在过去的几十年里，集成电路特征的扩展一直是不断增长的半导体行业的推动力量。缩放到越来越小的特征使得能够增加半导体芯片的有限空间中功能单元的密度。例如，缩小晶体管尺寸允许在芯片上并入更多数量的存储器件，从而为制造具有增加容量的产品提供支持。然而，驱动更多的容量并非没有问题。优化每个器件性能的必要性变得越来越重要。
附图说明
图1示出了包括连接到封装衬底的集成电路芯片或管芯的组件的实施例的截面示意性侧视图。
图2示出了包括连接到封装衬底的集成电路芯片或管芯的组件的另一实施例的截面示意性侧视图。
图3示出了半导体或绝缘体上半导体(SOI)衬底的一部分的顶侧透视图，该衬底例如是晶片上的集成电路管芯或芯片的一部分，并且示出了三维晶体管器件，在其上形成有与晶体管器件的栅极电极和漏极的互连。
图4示出了与载体衬底倒置并对齐的图3的器件衬底的截面侧视图。
图5示出了在将图3的器件衬底键合到载体衬底之后的图4的结构。
图6示出了在去除或减薄器件衬底以暴露晶体管的鳍状物的第二侧或背侧之后以及在鳍状物凹陷之后的图5的结构。
图7A-7B示出了在晶体管器件的鳍状物凹陷之后的图6的结构的截面侧视图。
图8A-8B示出了在具有到晶体管器件的源极的背侧的过孔或开口的鳍状物的背侧上的电介质材料的沉积和图案化之后的图7A-7B的结构。
图9A-9B示出了用于背侧结形成的材料的外延生长之后的图8A-8B的结构。
图10A-10B示出了在利用诸如钨的导电接触材料填充电介质材料中的过孔开口之后的图9A-9B的结构。
图11A-11B示出了图10A-10B的结构，并且示出了作为例如第一背侧互连或金属层的部分的连接到源极的接触点的互连。
图12示出了在形成用于将结构连接到器件层的第二管芯或背侧上的外部源的多个互连层和接触点之后的图6的结构。
图13示出了在载体衬底变薄以暴露穿硅过孔之后的图12的结构。
图14示出了根据形成组件的第二实施例的包括器件层的器件衬底，该器件层包括向下结合到载体衬底器件侧的多个器件。
图15示出了在去除或减薄器件衬底以暴露器件层的第二侧或背侧之后的图14的结构。
图16示出了在形成用于将结构连接到器件层的第二侧或背侧上的外部源的多个互连层和接触点之后的图15的结构。
图17示出了载体衬底变薄之后的图16的结构。
图18示出了在穿过载体衬底到器件层的第一侧上的互连的接触点形成TSV之后的图17的结构。
图19示出了包括诸如以上参考图1所描述的结合到封装衬底的组件的集合体的截面侧视图。
图20示出了包括诸如以上参考图1所描述的结合到封装衬底的组件的集合体的另一个实施例的截面侧视图。
图21示出了包括诸如以上参考图1所描述的结合到封装衬底的组件的集合体的另一个实施例的截面侧视图。
图22是实现一个或多个实施例的中介层。
图23示出了计算设备的实施例。
具体实施方式
未来的电路器件，例如中央处理单元器件，将需要集成在单个管芯或芯片中的高性能器件和低电容、低功率器件。这里描述的实施例涉及集成电路结构，该集成电路结构包括器件层中的平面或非平面半导体器件(例如，三维器件)，在器件层的每一侧具有一个或多个互连或布线层，并且一个或多个穿硅过孔(TSV)落在其中一个布线层上。在一个实施例中，一种装置包括电路结构，所述电路结构包括器件层，器件层包括多个晶体管器件，每个晶体管器件包括第一侧和相对的第二侧；在器件层的第一侧上并连接到晶体管器件中的多个晶体管器件的一个或多个导电互连级；以及包括导电TSV的衬底，所述导电TSV连接到所述结构的第一侧上的所述一个或多个导电互连级，使得所述一个或多个互连级位于所述TSV和所述器件层之间。在另一个实施例中，公开了一种系统，其包括封装衬底和与封装衬底连接的管芯，该封装衬底包括供电连接。在一个实施例中，管芯包括器件层和衬底，衬底包括连接到互连级的TSV，使得互连级在TSV和连接到器件层的第二侧(背侧或底侧)的器件层之间。还公开了形成电路结构的方法。
图1示出了包括连接到封装衬底的集成电路芯片或管芯的组件的一个实施例的截面示意性侧视图。组件100包括管芯110，其包括包括多个器件(例如，晶体管器件)的器件层或层115。器件层115包括代表层的第一侧的第一侧1150A以及与第一侧1150A相对的第二侧或背侧1150B。晶体管器件包括逻辑电路和可选的一个或多个功率晶体管。连接到第一侧1150A上的管芯110的器件层115是互连120，在一个实施例中，互连120包括但不限于从第一侧1150A连接到器件层115的器件的多个导电金属线。包括在互连中的是控制电路互连和/或电源互连(VDD，VDD门控和VSS)。各个行的金属线由电介质材料(例如层间电介质(ILD))分隔。在本实施例中，通过器件层115的第二侧1150B电连接到器件层115的器件的为互连130。在一个实施例中，互连130包括一行或多行金属化中的功率互连和/或控制电路互连，至少在某些情况下，金属化与器件层115的器件连接。单独的金属线行由电介质材料(例如层间电介质(ILD))分隔。图1还示出了设置在互连130下方的载体衬底140(如图所示)。在一个实施例中，如下面将要描述的，在逻辑电路的两侧上用金属化形成管芯110的工艺中，将载体衬底140结合到互连130(更具体地说，结合到电介质材料绝缘金属化)。贯通衬底140设置一个或多个穿硅过孔(TSV)135。图1示出了连接到器件层115的第二侧1150B上的互连130的TSV 135。TSV 135的相对侧可用于与衬底195(例如封装或其他器件)电连接或物理连接，诸如通过焊料连接或金属对金属(例如，铜对铜)连接。图1还示出了连接到接触点150(例如，焊料凸块)的互连120中的多个，其能够操作用于将管芯110连接到衬底190，例如封装190。图1进一步代表性地示出了通过封装衬底到管芯110的VDD和VSS连接。应当理解，接触点150不限于VDD和VSS连接，而是可以包括其他连接(例如，I/O连接)。
图2示出了包括连接到封装衬底的集成电路芯片或管芯的组件的另一实施例的截面示意性侧视图。组件200包括管芯210，管芯210包括包括多个器件(例如晶体管器件)的器件层或层215。器件层215包括代表层的第一侧的第一侧2150A以及与第一侧2150A相对的第二侧或背侧2150B。在该实施例中，器件层215的第二侧2150B连接到衬底225。衬底225例如是半导体材料，例如硅、锗或其他一种或多种材料，适于在其上面形成器件，在一个实施例中衬底被减薄。器件层215的晶体管器件包括逻辑电路和可选的一个或多个功率晶体管。其他类型的晶体管或器件也可以可选地被包括(例如，嵌入式存储器)。连接到第一侧2150A上的管芯210的器件层215是互连220，在一个实施例中，互连220包括但不限于从第一侧2150A连接到器件层215的器件的多个导电金属线或金属化。互连中包括控制电路互连和/或电源互连(VDD，VDD门控和VSS)。各行金属线由电介质材料(例如层间电介质(ILD))分隔。在本实施例中，通过器件层的第二侧2150B连接到器件层215的器件中的多个器件是包括一行或多行金属线的互连230。在一个实施例中，互连230包括电力互连和/或逻辑电路互连。互连230包括通过衬底225连接到TSV 245的电接触点，所述TSV 245连接到器件层215的器件(例如器件的背侧)。
如图所示，设置在器件层215的第二侧2150B上的互连230下面是载体衬底240。在一个实施例中，载体衬底240在器件层两侧上用金属化形成管芯210的过程中结合到互连230。通过载体衬底240设置一个或多个TSV235。TSV连接到器件层215的第二侧2150B上的互连230。TSV 235的相对侧可用于与衬底295(例如封装或器件)的电连接和物理连接。图2还示出了器件层215的第一侧2150A上的这种互连220中的多个被连接到能够操作用于将管芯210连接到封装290的接触点250(例如，焊料凸块)。图2进一步代表性地示出了穿过封装衬底290到管芯210的VDD和VSS接。
图3-13描述了形成与图1中的管芯110类似的管芯的方法或过程，包括在器件层的相对侧上的一个或多个互连，其中一个或多个TSV落在一个或多个互连中的一个上，使得一个或多个互连位于TSV和器件层之间。在一个实施例中，器件层中使用的器件是三维金属氧化物半导体场效应晶体管(MOSFET)。可以理解，在其他实施例中，其他形式的器件(例如，平面器件、纳米线器件)是合适的。良好开端式声明。
图3示出了半导体或绝缘体上半导体(SOI)衬底的一部分的顶侧透视图，该衬底例如是晶片上的集成电路管芯或芯片的一部分。具体而言，图3示出了包括硅或SOI的衬底310的结构300。覆盖衬底310是可选的缓冲层320。在一个实施例中，缓冲层310是在一个实施例中通过生长技术引入衬底310上的硅锗材料。代表性地，缓冲层320(如果存在)具有约几百纳米(nm)数量级的代表性厚度。
在图3所示的实施例中的衬底310和可选的缓冲层320的表面(如所看到的上表面)上设置的是诸如N型晶体管器件或P型晶体管器件之类的晶体管器件的一部分。在本实施例中，N型或P型晶体管器件共有的是设置在缓冲层320的表面上的主体或鳍状物330。在一个实施例中，鳍状物330由半导体材料或诸如硅、硅锗或III-V族或IV-V族半导体材料的多于一种半导体材料的叠层形成。在一个实施例中，鳍状物330的材料根据用于形成三维集成电路器件的常规处理技术形成。代表性地，在衬底上外延生长半导体材料，然后形成鳍状物330(例如，通过掩模和蚀刻工艺)。
在一个实施例中，鳍状物330具有大于高度尺寸H的长度尺寸L。代表性长度范围在10纳米(nm)至1毫米(mm)的量级上，并且典型高度范围在5nm至200nm的量级上。鳍状物330也具有代表性大约4-10nm的量级的宽度W。如图所示，鳍状物330是从衬底310的表面或在衬底310的表面上(或可选地从缓冲层320或在缓冲层320上)延伸的三维体。如图3所示的三维体是具有从所观察的缓冲层320的表面突出的相对侧(第一和第二侧)的矩形体。可以理解的是，在处理这样的主体时，真实的矩形形状可能无法用可用的工具实现，并且可能导致其他形状。代表性的形状包括但不限于梯形(例如，基部比顶部宽)和拱形。
在图3的结构的实施例中设置在鳍状物330上的是栅极叠层。在一个实施例中，栅极叠层包括例如二氧化硅或具有比二氧化硅大的电介质常数的电介质材料(高k电介质材料)的栅极电介质层。在一个实施例中，设置在栅极电介质层上的是例如金属的栅极325。栅极叠层可以包括在其相对侧上的电介质材料的间隔件350。用于间隔件350的代表性材料是诸如氮化硅(SiN)或硅碳氮(SiCN)的低k材料。图3示出了邻近栅极叠层的侧壁并且在鳍状物330上的可选的间隔件350。形成在栅极叠层的相对侧上的鳍状物330之上或之中的是结(源极340A和漏极340B)。
在一个实施例中，为了形成三维晶体管结构，在鳍状物330上形成栅极电介质材料，例如通过毯覆式沉积，接着毯式沉积牺牲或伪栅极材料。在结构上引入掩模材料并将其图案化以在指定的沟道区域上保护栅极叠层材料(具有“牺牲栅极材料或伪栅极材料”的栅极叠层)。然后使用蚀刻工艺去除不希望的区域中的栅极叠层材料并且在指定的沟道区域上图案化栅极叠层。然后形成间隔件350。一种形成间隔件350的技术是在结构上沉积膜，保护所需区域的膜，然后蚀刻以将膜图案化成期望的间隔件尺寸。
在鳍状物330和间隔件350上形成包括牺牲或伪栅极材料的栅极叠层之后，在鳍状物330上或鳍状物330中形成结(源极和漏极)。源极和漏极形成在鳍状物330中或鳍状物330上，位于栅极叠层的相对侧(栅极电介质上的牺牲栅极电极)。在图3所示的实施例中，源极340A和漏极340B通过在源极330的一部分上外延生长源极和漏极材料作为包层而形成。源极340A和漏极340B的代表性材料包括但不限于硅、硅锗或III-V族或IV-V族化合物半导体材料。可选地，源极340A和漏极340B可以通过在去除鳍状物材料的指定结区中去除部分鳍材料和外延生长的源和漏材料而形成。
在形成源极340A和漏极340B之后，在一个实施例中，去除牺牲栅极或伪栅极并用栅极电极材料代替。在一个实施例中，在去除牺牲或伪栅极叠层之前，将电介质材料沉积在结构上。在一个实施例中，电介质材料是二氧化硅或低k电介质材料，沉积为毯子，然后抛光以暴露牺牲或伪栅极325。然后通过例如蚀刻工艺去除牺牲或伪栅极和栅极电介质。
在去除牺牲或伪栅极和栅极电介质之后，在栅极电极区域中形成栅极叠层。引入栅极叠层，例如沉积在包括栅极电介质和栅极电极的结构上。在一个实施例中，栅极电极叠层的栅极电极325由金属栅极构成，并且栅极电介质层由电介质常数大于二氧化硅的电介质常数的材料(高K材料)构成。例如，在一个实施例中，栅极电介质层(图3中的栅极电极325下方)由诸如但不限于氧化铪、氮氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸钡锶、钛酸钡、钛酸锶、氧化钇、氧化铝、铅钪钽氧化物、铌酸铅锌或其组合的材料构成。在另一个实施例中，栅极电介质层可以包括多于一种电介质材料，例如二氧化硅和高K材料，或者两种不同的高K材料或电介质材料的其他布置。在一个实施例中，栅极电极325由金属层组成，例如但不限于金属氮化物、金属碳化物、金属硅化物、金属铝化物、铪、锆、钛、钽、铝、钌、钯、铂、钴、镍或导电金属氧化物。在另一个实施例中，栅极电极可以包括多于一层合适的金属或其他导电材料。在形成栅极叠层之后，在三维晶体管器件(例如ILD0)上沉积二氧化硅或低k电介质材料的附加电介质材料电介质材料，以将器件结构封装或嵌入电介质材料中。图3示出了封装三维晶体管器件(例如，作为ILD0)的电介质材料355A。
图3示出了形成三维晶体管器件结构的互连之后的结构。在该实施例中，分别对栅极电极325和漏极340B进行电连接作为第一互连层或金属层。可以采用类似的技术来形成到源极340A的互连。代表性地，为了形成与栅极电极325的电接触，首先通过例如掩模工艺使得在掩模中有通往栅极点积325和漏极340B的开口而从从电介质材料355A的顶表面(如所看到的)到栅极电极形成开口。蚀刻电介质材料355A以暴露栅极电极和漏极，然后去除掩模材料。接下来，例如钨的接触材料被引入到开口中并且开口被填充以形成到栅极电极325的接触点375A和到漏极340B的接触点375B。电介质材料355A的表面(如所看到的顶表面)然后可以用导电材料接种并用掩模材料图案化以限定用于互连路径的开口，开口露出接触点375A和接触点375B。然后通过电镀工艺引入诸如铜的导电材料，以形成连接到栅极电极325的接触点375A的互连370A和连接到漏极340B的接触点375B的互连370B。互连370A和互连370B是第一互连或金属层或级的一部分。然后可以去除掩模材料和不需要的种子材料。在将互连形成为初始金属级之后，例如硅氧化物或低k电介质材料的电介质材料355B可以作为ILD1层沉积在互连上和互连周围。然后可以根据常规工艺形成额外的互连层。图1示出了由多层互连构成的管芯110的信号布线120。图3中的互连370A和互连370B代表例如一个最靠近器件层的这样的层中的第一层。从互连观察，最终或顶层包括接触点(例如，接触焊盘)。图3示出了具有在其中和/或其上形成的接触点385的最终电介质层355D。在一个实施例中，接触点385连接到一个或多个底层互连或布线层并以类似于互连370的方式形成。为了进一步讨论，图3的结构的器件层由器件层3000标识，并且器件或器件层3000的第一侧(与衬底310相对的一侧)上的一个或多个互连级由互连3100标识。
图4示出了用于将结构连接到载体并将倒置结构与下面的载体结构400对齐的结构的倒置或翻转之后的图3的结构的扩展图的截面侧视图。在该实施例中，载体结构是包括衬底410的TSV晶片，衬底410例如是硅衬底。在该实施例中，衬底410包括仅为部分TSV的导电材料(例如，电镀铜)的TSV 420，部分的意思是从衬底410的表面415延伸穿过小于衬底410的整个厚度部分(例如，穿过基材半路)。衬底410还可以包括例如在表面415上形成的电路器件。
图5示出了在载体结构400的结合之后的图4的组件。在一个实施例中，结构例如利用结构300的表面上的电介质材料和结构400的半导体材料之间的粘合剂结合。图5示出了通过结构300的接触点385直接连接互连3100的TSV 420。在衬底410的表面415上存在一个或多个电路器件的实施例中，这些器件也可以通过接触点385连接到互连3100。
图6示出了在去除或减薄衬底310以暴露器件层3000的第二侧或背侧(以暴露图3中的鳍状物330的背侧或底侧)之后的图5的结构。在一个实施例中，衬底310可通过减薄工艺(例如机械研磨或蚀刻工艺)移除。在该实施例中，衬底310被完全去除以暴露器件层3000的第二侧或背侧。为了形成诸如图2中的管芯210的管芯，衬底310将变薄，但一部分将保留。从结构的第二侧或背侧减薄衬底310可以可选地凹陷或减薄器件层3000的晶体管器件的鳍状物的一部分(参见图3)。
图7A-7B示出了形成到晶体管器件的第二侧或背侧的接触点的实施例。具体标识为图6中由插图参考7-7'标识的晶体管器件。该晶体管器件包括与器件层的第一侧或器件侧上的栅极电极和漏极的接触点，类似于参照图3描述的器件。使用图3的晶体管器件作为参考，图7A示出了图3的结构的线A-A'的倒置截面，图7B示出了穿过图3的结构的线B-B'的倒置截面。图7A-7B示出了去除衬底310和鳍状物330的可选凹陷之后的结构。在一个实施例中，为了使鳍状物330凹陷，可以利用蚀刻工艺，其中选择性地朝向相对于电介质材料355A去除鳍状物材料应用蚀刻剂。可替代地，掩模材料可以在具有暴露鳍状物330的开口的电介质材料355A表面(暴露的背侧表面)上被图案化。鳍状物330的材料可通过例如蚀刻工艺被去除以使鳍状物330凹入，然后去除掩模材料。
图8A和图8B分别示出了在鳍状物330的背侧上沉积和图案化电介质材料之后的图7A和图7B的结构。图8A-8B示出了例如二氧化硅或者通过例如毯式沉积工艺沉积的低K电介质材料的电介质材料381。一旦沉积，可通过例如在电介质材料381的表面上形成掩模材料来图案化电介质材料381，在该实施例中，在鳍状物330的相对侧上具有例如与源区相对的开口或过孔。图8A示出了穿过电介质材料381的开口382，该电介质材料381定位在鳍状物330的背侧上，对应于鳍状物的源极区(源极340A)。图8B示出了在该实施例中，开口(例如开口382)具有的直径的尺寸大于鳍状物330的宽度尺寸。以这种方式，鳍状物330的背侧以及鳍状物330的侧壁暴露。图8B还显示了蚀刻继续穿过该结构以暴露源极340A的背侧。
图9A和图9B分别示出了用于背侧结形成的材料的外延生长之后的图8A和图8B的结构。材料的一个例子是诸如硅锗或III-V族或IV-V族半导体材料的半导体材料。图8A示出了在与源极340A的背侧对齐的区域中的开口382中的外延生长材料385。图9B示出了在鳍状物330的侧壁上外延生长并且与先前形成在结构的第一侧或器件侧上的源极340连接的材料385。
图10A和图10B分别示出了在利用诸如钨的导电接触材料填充电介质材料381中的过孔开口之后的图9A和9B的结构。图10A示出了与源极340相关联的外延材料385的接触点386。图10B示出了与外延材料385的接触金属386。图10A和10B还示出了从结构的背侧或第二侧或器件层的底侧到源极340A(经由接触材料)的连接。现在可以通过例如上面关于器件侧互连(参见图3和所附文本)描述的技术来形成到接触点386的互连。
上述形成背侧结(源极)接触点的描述是一个实施例。可以理解的是，存在其他方法而不是在鳍状物上外延生长材料。其他实施例包括但不限于通过例如驱动掺杂剂来从背侧改变鳍状物的区域。在另一个实施例中，鳍状物330的侧壁可以暴露在源极区中，并且可以在这样的侧壁上引入诸如钨的接触材料。在也在源极的器件侧上形成接触材料(例如，在形成与栅极电极325的接触点375A和与漏极340B的接触点375B时形成这种接触点)的情况下，接触点可以在背侧处理操作中延伸以形成与源极的环绕式接触。最后，形成背侧源极接触点的描述不仅限于源极接触点相似的技术，可用于在需要时形成背侧漏极接触点。
图11A和图11B分别示出了图10A和图10B的结构，并且示出了作为例如第一背侧互连或金属层的一部分连接到与源极340的接触点386的互连390。图11A-11B还示出了在互连或金属层上沉积二氧化硅或低k电介质材料的电介质材料355C之后的结构。
已经描述了形成与器件层3000的器件的第二侧或背侧接触点的形成以及与第一背侧互连或金属层或级的接触点的连接，图12示出了在形成用于将结构连接到器件层3000的第二侧或背侧上的外部源的多个互连层以及接触点之后的图6的结构。这些层的互连可以通过电镀工艺形成。在一个实施例中，诸如铜之类的导电材料的这种互连可以掺杂有掺杂剂以改善电迁移。如图所示，每个互连级通过电介质材料与邻接级分隔开。接触点397例如是能操作用于将结构连接到诸如封装衬底的衬底的接触块或C4凸块。
图13示出了在衬底410变薄之后的图12的结构。在一个实施例中，衬底410通过机械研磨或蚀刻工艺变薄以暴露衬底410背侧上的TSV 420，使得这些TSV可用于电连接到另一个器件或衬底。结果是与上述图1类似的结构。在另一个实施例中，一旦TSV 420暴露，引入再分布层以将连接点重新分布到衬底410的背侧上的TSV4 20。图13示出了例如电镀铜的再分布层440，其可选地连接到TSV 420并设置在例如二氧化硅或高k电介质材料的电介质层430和435之间。在另一个实施例中，除了再分布层之外或者作为再分布层的替代，诸如二极管、电容器和/或电感器的电路器件可以形成在衬底410上并且在需要时通过TSV 420连接到互连3100。
图14-18描述了形成与图1中的管芯110类似的管芯的方法的另一个实施例。参考图14，该图显示了向下与载体衬底器件侧结合的器件晶片。图14示出了在器件层的第一侧或器件侧上的包括半导体衬底510、器件层5000和互连5100的器件结构500。互连5100包括金属层之间具有电介质材料的一层或多层金属层。
在图14所示的实施例中，器件结构500被结合到载体衬底610。载体衬底610例如是半导体(例如硅)衬底，诸如晶片或晶片的一部分。载体衬底610可以可选地包括在连接到器件结构500的表面上的一个或多个电路器件(例如，二极管、电容器、电感器)。图14示出了在例如与粘合剂粘合之后的器件结构500和载体衬底组装在结构互连5100的表面上的电介质材料与衬底610的半导体材料之间。在一个或多个电路器件存在于载体衬底610上的实施例中，这样的电路器件可以连接到器件结构5100的接触点，接触点连接到互连5100。
图15示出在去除或减薄衬底510以暴露器件层5000的第二侧或背侧(例如，以暴露器件层5000的晶体管器件的鳍状物的背侧或底侧)之后的图14的结构。在一个实施例中，衬底510可以通过减薄工艺(例如机械研磨或蚀刻工艺)来去除。在该实施例中，衬底510被完全去除以暴露器件层5000的第二侧或背侧。衬底510从结构的第二侧或背侧变薄可以可选地凹陷或减薄器件层5000的晶体管器件的鳍状物的一部分(见图3)。
图16示出在形成用于将结构连接到器件层5000的第二侧或背侧上的外部源的多个互连层和接触点之后的图15的结构。互连5200包括例如，通过上面参照图7A-10B描述的技术形成到器件层5000的一个或多个器件的接触点。互连5200还包括例如通过如上所述的电镀工艺(例如，参考图11A-11B)形成的铜的金属层或线。在一个实施例中，诸如铜的导电材料的这种金属层或线可以掺杂有掺杂剂以改善电迁移。如图所示，每个金属层通过电介质材料与邻接的层分开。接触点597例如是C4凸块，其能够操作用于将该结构连接到诸如封装衬底的衬底。
图17示出了在衬底610变薄之后的图16的结构。在一个实施例中，通过机械研磨或蚀刻工艺将衬底610变薄到期望的厚度。图18示出了通过衬底610到互连点5100的接触点形成TSV之后的图17的结构。代表性地，TSV 620可以通过利用用于期望的TSV的衬底的区域周围的掩模中的开口掩蔽衬底610的背侧(如所看到的底面)来形成。然后衬底610被蚀刻穿过衬底到互连5100的接触点。接着沉积导电材料(例如，电镀铜)以形成穿过衬底610的TSV620。结果得到类似于上述图1的结构。在另一个实施例中，一旦形成TSV 620，引入再分布层以将连接点重新分布到衬底610的背侧上的TSV 620。图18示出了可选的再分布层640，例如电镀铜，可选地连接到TSV 620和设置在例如二氧化硅或高k电介质材料的电介质层630和635之间。在另一个实施例中，除了再分布层之外或者作为再分布层的替代方案，诸如二极管、电容器和/或电感器的电路器件可以形成在衬底610上并且在需要时连接到互连5100。
如上参考图1-18所述在载体衬底中形成的TSV不占用任何器件半导体层，而是直接落在互连3100(参见图13)或互连5100(参见图18)上。此外，由于TSV与器件(例如晶体管)之间不存在横向相互作用，因此可以消除或最小化现有技术中置于器件层中的“禁止区域”。因此，对于更多功能器件(例如，晶体管)，可以节省否则由TSV和与器件半导体层相关联的外围设备占据的相对较大的半导体区域。可替代地，可以扩大TSV尺寸。在这种情况下，TSV本身可以用作键合焊盘，因为可能不需要扇出，从而不需要额外的再分布层。这允许多种封装选项。图19-21展示了这些选项的示例。
图19示出了包括诸如以上参考图1所描述的结合到封装衬底的组件的集合体的截面侧视图。组件710包括器件层的第一侧上的第一互连，第一互连包括通过焊料结合部725连接到封装衬底730的接触焊盘735的接触焊盘。组件710的器件层的第二侧上的第二互连连接到TSV 720，TSV 720延伸贯通载体衬底。TSV 720通过焊料结合部740连接到管芯750的接触点，管芯750例如是管芯叠层布置中的处理器、存储器设备、无线电设备、传感器设备、功率管理装置。
图20示出了包括诸如以上参照图1描述的、结合到封装衬底的组件的集合体的另一个实施例的截面侧视图。组件810包括器件层的第一侧上的第一互连，包括通过焊料结合部825连接到封装衬底830的接触焊盘835的接触焊盘。组件810的器件层的第二侧上的第二互连连接到延伸贯通组件的载体衬底的TSV 820。TSV 820通过直接金属到金属结合840(例如，铜到铜结合)连接到管芯850的接触点，例如管芯叠层布置中的处理器、存储器设备、无线电设备、传感器设备、功率管理装置。
图21示出了包括诸如上面参照图1所描述的、结合到封装衬底的组件的集合体的另一个实施例的截面侧视图。组件910包括器件层的第一侧上的第一互连，第一互连包括通过焊料结合部925连接到封装衬底930的接触焊盘935的接触焊盘。组件910的器件层的第二侧上的第二互连连接到TSV 920，TSV 920延伸贯通组件的载体衬底。TSV 920通过线结合945连接到封装衬底的其他接触焊盘935，以例如提供额外的输入/输出端口。
图22图示了包括一个或多个实施例的中介层1000。中介层1000是用于将第一衬底1002桥接到第二衬底1004的中间衬底。第一衬底1002可以是例如集成电路管芯。第二衬底1004可以是例如存储器模块、计算机主板或另一个集成电路管芯。通常，中介层1000的用途是将连接扩展到更宽的间距或将连接重新路由到不同的连接。例如，中介层1000可以将集成电路管芯耦合到随后可以耦合到第二衬底1004的球栅阵列(BGA)1006。在一些实施例中，第一和第二衬底1002/1004被附接到中介层1000的相对侧。在其它实施例中，第一和第二衬底1002/1004被附接到中介层1000的同一侧。在另外的实施例中，三个或更多个衬底通过中介层1000互连。
中介层1000可以由环氧树脂、玻璃纤维增强环氧树脂、陶瓷材料或诸如聚酰亚胺的聚合物材料形成。在进一步的实施方式中，中介层可以由交替的刚性或柔性材料形成，所述交替的刚性或柔性材料可以包括用于半导体衬底中的上述相同材料，例如硅、锗和其他III-V族和IV族材料。
中介层可以包括金属互连1008和过孔1010，包括但不限于穿硅过孔(TSV)1012。中介层1000还可以包括嵌入式器件1014，嵌入式器件1014包括无源器件和有源器件。这些器件包括但不限于电容器、去耦电容器、电阻器、电感器、熔丝、二极管、变压器、传感器和静电放电(ESD)器件。也可以在中介层1000上形成更复杂的器件，例如射频(RF)器件、功率放大器、功率管理器件、天线、阵列、传感器和MEMS器件。
根据实施例，本文公开的装置或过程可以用于制造中介层1000。
图23示出了根据一个实施例的计算设备1100。计算设备1100可以包括多个部件。在一个实施例中，这些部件被连接到一个或多个主板。在替代实施例中，这些部件被制造到单个片上系统(SoC)管芯而不是主板上。计算设备1100中的部件包括但不限于集成电路管芯1102和至少一个通信芯片1108。在一些实施方式中，通信芯片1108被制造为集成电路管芯1102的一部分。集成电路管芯1102可以包括CPU 1104以及通常用作高速缓存存储器的管芯上存储器1106，其可以通过诸如嵌入式DRAM(eDRAM)或自旋转移力矩存储器(STTM或STTM-RAM)来提供。
计算设备1100可以包括可以或者可以不物理地和电地耦合到主板或者在SoC管芯内制造的其他部件。这些其他部件包括但不限于易失性存储器1110(例如DRAM)、非易失性存储器1112(例如ROM或闪存)、图形处理单元1114(GPU)、数字信号处理器1116、密码处理器1142(在硬件内执行密码算法的专用处理器)、芯片组1120、天线1122、显示器或触摸屏显示器1124、触摸屏控制器1126、电池1128或其它电源、功率放大器(未示出)、全球定位系统(GPS)设备1144、罗盘1130、运动协处理器或传感器1132(其可以包括加速度计、陀螺仪和罗盘)、扬声器1 134、相机1136、用户输入设备1138(诸如键盘、鼠标、触控笔和触摸板)以及大容量存储设备1140(诸如硬盘驱动器、光盘(CD)、数字多功能盘(DVD)等等)。
通信芯片1108使得用于向计算设备1100以及从计算设备1100传送数据的无线通信成为可能。术语“无线”及其派生词可用于描述电路、设备、系统、方法、技术、通信信道等，可以通过使用调制的电磁辐射通过非固体介质来传送数据。该术语并不意味着相关设备不包含任何电线，尽管在一些实施例中它们可能不包含电线。通信芯片1108可以实现多种无线标准或协议中的任何一种，包括但不限于Wi-Fi(IEEE802.11系列)、WiMAX(IEEE 802.16系列)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙及其衍生物以及被指定为3G、4G、5G及更高的任何其他无线协议。计算设备1100可以包括多个通信芯片1108。例如，第一通信芯片1108可以专用于较短距离的无线通信，诸如Wi-Fi和蓝牙，并且第二通信芯片1108可以专用于较长距离的无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE，Ev-DO、5G等。
计算设备1100的处理器1104包括根据实施例形成的一个或多个器件，诸如晶体管或金属互连，器件包括到器件的背侧接触点和背侧金属化以及包括TSV以连接到器件侧或背侧金属化的载体衬底。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将该电子数据转换为可以存储在寄存器和/或存储器中的其它电子数据的任何设备或设备的一部分。
通信芯片1108还可以包括根据实施例形成的一个或多个器件，诸如晶体管或金属互连，所述实施例包括到器件的背侧接触点和背侧金属化以及包括TSV以连接到器件侧或背侧金属化的载体衬底。
在进一步的实施例中，容纳在计算设备1100内的另一部件可以包括根据实施方式形成的一个或多个器件，诸如晶体管或金属互连，器件包括到器件的背侧接触点和背侧金属化以及包括TSV以连接到器件侧或背侧金属化的载体衬底。
在各种实施例中，计算设备1100可以是膝上型计算机、上网本计算机、笔记本计算机、超级计算机、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器或数字录像机。在进一步的实施方式中，计算设备1100可以是处理数据的任何其他电子设备。示例
示例1是一种装置，包括：电路结构，该电路结构包括器件层，器件层包括多个晶体管器件，每个晶体管器件包括第一侧和相对的第二侧；在器件层的第一侧上并且耦合到晶体管器件中的多个晶体管器件的一个或多个导电互连级；以及衬底，所述衬底包括耦合到所述结构的第一侧上的所述一个或多个导电互连级的导电穿硅过孔，使得所述一个或多个互连层介于所述穿硅过孔和所述器件层之间。
在示例2中，示例1的装置的一个或多个导电互连级包括一个或多个第一互连级，该装置还包括在器件层的第二侧上的、耦合到晶体管器件的一个或多个第二互连级。
在示例3中，示例2的装置还包括设置在器件层的第二侧上的接触点，该接触点能够操作用于耦合到外部源并耦合到至少第二互连层。
在示例4中，示例1-3中任一示例的装置的穿硅过孔包括耦合到一个或多个导电互连级的第一侧和能够操作用于耦合到外部源的第二侧。
在示例5中，示例4的装置的穿硅过孔的第二侧限定接触焊盘。
在示例6中，示例4的装置还包括设置在穿硅过孔的第二侧上的接触焊盘，接触焊盘能够操作用于耦合到外部源并耦合到穿硅过孔。
示例7是一种系统包括：具有供电连接的封装衬底；以及耦合到所述封装衬底的管芯，所述管芯包括：(i)器件层，其包括多个晶体管器件，每个晶体管器件包括第一侧和相对的第二侧；(ii)所述器件层的第一侧上并且耦合到所述晶体管器件中的多个晶体管器件的一个或多个导电互连级；以及(iii)衬底，所述衬底包括耦合到所述结构的第一侧上的所述一个或多个导电互连级的导电穿硅过孔，使得所述一个或多个互连级位于所述穿硅过孔和所述器件层之间。
在示例8中，示例7的系统的一个或多个导电互连级包括一个或多个第一互连级，该装置还包括在器件层的第二侧上的、耦合到晶体管器件的一个或多个第二互连级。
在示例9中，示例8的系统还包括设置在器件层的第二侧上的接触点，该接触点能够操作用于耦合到外部源并耦合到至少第二互连层。
在示例10中，示例7-9中的任一个的系统的穿硅过孔包括耦合到一个或多个导电互连级的第一侧和能够操作用于耦合到外部源的第二侧。
在示例11中，示例10的系统的穿硅过孔的第二侧限定接触焊盘。
在示例12中，示例10的系统还包括设置在穿硅过孔的第二侧上的接触焊盘，接触焊盘能够操作用于耦合到外部源并且耦合到穿硅过孔。
示例13是一种方法，包括：在衬底上形成多个晶体管器件，所述多个晶体管器件限定器件层，所述器件层包括第一侧和相对的第二侧，其中所述第二侧耦合到所述衬底；在所述器件层的第一侧上形成一个或多个互连级，所述一个或多个互连级耦合到所述多个器件中的多个器件；去除衬底的一部分；以及将穿硅过孔耦合到所述一个或多个互连级，使得所述一个或多个互连级设置在所述器件层和所述穿硅过孔之间。
在示例14中，示例13的方法的穿硅过孔设置为穿过衬底，并且将穿硅过孔耦合至一个或多个互连层包括耦合包括穿硅过孔的衬底。
在示例15中，在将穿硅过孔耦合到一个或多个互连级之前，示例13-14中的任一个的方法包括将衬底耦合到一个或多个互连级并且耦合穿硅过孔包括形成贯穿衬底的穿硅过孔。
在示例16中，示例13-15中任一示例的方法的去除衬底的一部分包括去除衬底的整个部分。
在示例17中，示例13-16中的任一示例的方法的一个或多个互连级包括一个或多个第一互连级，该方法还包括在器件层的第二侧上形成至少一个或多个第二互连级，其中所述一个或多个第二互连级耦合到所述多个晶体管器件中的多个晶体管器件。
在示例18中，示例17的方法还包括在器件层的第二侧上形成接触点，该接触点能够操作用于耦合到外部源并耦合到该一个或多个第二互连级。
在示例19中，示例13-18中的任何一个的方法的穿硅过孔包括第二侧和耦合到一个或多个互连级的第一侧，其中穿硅过孔的第二侧限定接触焊盘，接触焊盘能够操作用于耦合到外部源。
在示例20中，示例13-19中的任何示例的方法还包括在穿硅过孔的第二侧上形成接触焊盘，该接触焊盘能够操作用于耦合到外部源并耦合到穿硅过孔。
包括在摘要中描述的内容的所示实施方式的以上描述并非旨在穷举或将本发明限制于所公开的精确形式。尽管本文中出于说明性目的描述了本发明的具体实施方式和示例，但是正如相关领域的技术人员将认识到的，在本发明的范围内可能有各种等同修改。
根据上面的具体实施方式可以做出这些修改。所附权利要求中使用的术语不应被解释为将本发明限制于说明书和权利要求书中所公开的具体实施方式。相反，本发明的范围完全由所附的权利要求确定，这些权利要求要根据既定的权利要求解释的原则来进行解释。

Claims (20)

1.一种装置，包括：
电路结构，其包括器件层，所述器件层包括多个晶体管器件，每个晶体管器件包括第一侧和相对的第二侧；
一个或多个导电互连级，其位于所述器件层的第一侧上并且耦合到所述晶体管器件中的多个晶体管器件；以及
衬底，其包括耦合到所述结构的第一侧上的所述一个或多个导电互连级的导电穿硅过孔，使得所述一个或多个互连级位于所述穿硅过孔和所述器件层之间。
2.根据权利要求1所述的装置，其中，所述一个或多个导电互连级包括一个或多个第一互连级，所述装置还包括耦合到所述晶体管器件中的多个晶体管器件的、位于所述器件层的第二侧上的一个或多个第二互连级。
3.根据权利要求2所述的装置，还包括设置在所述器件层的所述第二侧上的接触点，所述接触点能够操作用于耦合到外部源并且耦合到至少所述第二互连层。
4.根据权利要求1所述的装置，其中，所述穿硅过孔包括耦合到所述一个或多个导电互连级的第一侧和能够操作用于耦合到外部源的第二侧。
5.根据权利要求4所述的装置，其中，所述穿硅过孔的所述第二侧限定接触焊盘。
6.根据权利要求4所述的装置，还包括设置在所述穿硅过孔的所述第二侧上的接触焊盘，所述接触焊盘能够操作用于耦合到外部源并且耦合到所述穿硅过孔。
7.一种系统，包括：
包括供电连接的封装衬底；以及
耦合到所述封装衬底的管芯，所述管芯包括：
(i)器件层，其包括多个晶体管器件，每个晶体管器件包括第一侧和相对的第二侧；
(ii)一个或多个导电互连级，其位于所述器件层的第一侧上并且耦合到所述晶体管器件中的多个晶体管器件；以及
(iii)衬底，所述衬底包括耦合到所述结构的第一侧上的所述一个或多个导电互连级的导电穿硅过孔，使得所述一个或多个互连级位于所述穿硅过孔和所述器件层之间。
8.根据权利要求7所述的系统，其中，所述一个或多个导电互连级包括一个或多个第一互连级，所述装置还包括耦合到所述晶体管器件中的多个晶体管器件的、位于所述器件层的第二侧上的一个或多个第二互连级。
9.根据权利要求8所述的系统，还包括设置在所述器件层的所述第二侧上的接触点，所述接触点能够操作用于耦合到外部源并且耦合到至少所述第二互连层。
10.根据权利要求7所述的系统，其中，所述穿硅过孔包括耦合到所述一个或多个导电互连级的第一侧和能够操作用于耦合到外部源的第二侧。
11.根据权利要求10所述的系统，其中，所述穿硅过孔的所述第二侧限定接触焊盘。
12.根据权利要求10所述的系统，还包括设置在所述穿硅过孔的所述第二侧上的接触焊盘，所述接触焊盘能够操作用于耦合到外部源并且耦合到所述穿硅过孔。
13.一种方法，包括：
在衬底上形成多个晶体管器件，所述多个晶体管器件限定器件层，所述器件层包括第一侧和相对的第二侧，其中，所述第二侧耦合到所述衬底；
在所述器件层的第一侧上形成一个或多个互连级，所述一个或多个互连级耦合到所述多个器件中的多个器件；
去除所述衬底的一部分；以及
将穿硅过孔耦合到所述一个或多个互连级，使得所述一个或多个互连级设置在所述器件层和所述穿硅过孔之间。
14.根据权利要求13所述的方法，其中，所述穿硅过孔被设置成穿过衬底，并且将所述穿硅过孔耦合到所述一个或多个互连级包括：耦合包括所述穿硅过孔的所述衬底。
15.根据权利要求13所述的方法，其中，在将所述穿硅过孔耦合到所述一个或多个互连级之前，所述方法包括将衬底耦合到所述一个或多个互连级，并且耦合所述穿硅过孔包括穿过所述衬底形成所述穿硅过孔。
16.根据权利要求13所述的方法，其中，去除所述衬底的一部分包括去除所述衬底的整个部分。
17.根据权利要求13所述的方法，其中，所述一个或多个互连级包括一个或多个第一互连级，所述方法进一步包括：
在所述器件层的所述第二侧上形成至少一个或多个第二互连级，其中，所述一个或多个第二互连级耦合到所述多个晶体管器件中的多个晶体管器件。
18.根据权利要求17所述的方法，还包括在所述器件层的所述第二侧上形成接触点，所述接触点能够操作用于耦合到外部源并且耦合到所述一个或多个第二互连级。
19.根据权利要求13所述的方法，其中，所述穿硅过孔包括第二侧和耦合到所述一个或多个互连级的第一侧，其中，所述穿硅过孔的所述第二侧限定能够操作用于耦合到外部源的接触焊盘。
20.根据权利要求13所述的方法，还包括在所述穿硅过孔的所述第二侧上形成接触焊盘，所述接触焊盘能够操作用于耦合到外部源并且耦合到所述穿硅过孔。
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