CN107690704A - 具有GAAS作为牺牲层的Ge纳米线晶体管 - Google Patents

具有GAAS作为牺牲层的Ge纳米线晶体管 Download PDF

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Publication number
CN107690704A
CN107690704A CN201580080411.9A CN201580080411A CN107690704A CN 107690704 A CN107690704 A CN 107690704A CN 201580080411 A CN201580080411 A CN 201580080411A CN 107690704 A CN107690704 A CN 107690704A
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Prior art keywords
nano wire
channel region
gate stack
multiple nano
gate
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Inventor
W·拉赫马迪
M·V·梅茨
V·H·勒
J·T·卡瓦列罗斯
S·K·加德纳
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Intel Corp
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Intel Corp
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Publication of CN107690704A publication Critical patent/CN107690704A/zh
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
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    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种装置，包括三维半导体主体，三维半导体主体包括沟道区和布置在沟道区的相对侧上的结区，三维半导体主体包括多个纳米线，纳米线包括布置在结区中由第二材料分离的相应的平面中的锗材料，其中第二材料的晶格常数类似于锗材料的晶格常数；以及布置在沟道区上的栅极叠层，栅极叠层包括布置在栅极电介质上的栅极电极。一种方法，包括：在衬底上的分离平面中形成多个纳米线，多个纳米线中的每个包括锗材料并通过牺牲材料与相邻纳米线分离；将栅极叠层布置在指定沟道区中的多个纳米线上，栅极叠层包括电介质材料和栅极电极。

Description

具有GAAS作为牺牲层的Ge纳米线晶体管
技术领域
包括非平面半导体器件的半导体器件，所述非平面半导体器件具有带有低带隙包覆层的沟道区。
背景技术
过去几十年来，在集成电路中的特征的缩放是不断成长的半导体工业背后的驱动力。缩小到越来越小的特征使在半导体芯片的有限基板面上的功能单元的增大的密度成为可能。例如，缩小晶体管尺寸允许在芯片上结合增大数量的存储器设备，有助于具有增大的容量的产品的制造。然而，对越来越大的容量的驱动不是没有问题。优化每个器件的性能的必要性变得越来越明显。
由于低有效质量连同减小的杂质散射，由III-V族化合物半导体材料系统形成的半导体器件提供在晶体管沟道中的异常高的载流子迁移率。III族和V族指在元素周期表的第13-15族(以前的III-V族)中的半导体材料的元素的位置。这样的器件提供高驱动电流性能，并看起来对于未来的低功率高速逻辑应用是有前途的。
附图说明
图1示出半导体衬底的一部分、例如晶片的一部分的顶侧透视图，晶片具有在其上形成的牺牲鳍状物和相邻于牺牲鳍状物的电介质材料。
图2示出在移除牺牲鳍状物以在电介质材料中形成沟槽之后的图1的结构。
图3示出在根据高宽比捕获(ART)方法对纳米线和牺牲材料的交替层进行外延生长之后的图2的结构。
图4示出在电介质材料的凹进之后的图3的结构。
图5示出在将纳米线的源极和漏极实现在牺牲材料上的情况下，在结构的指定沟道区中的纳米线上引入间隔体和牺牲或虚设栅极电极并且相邻于间隔体引入电介质材料之后的图4的结构。
图6示出在将源极和漏极实现为纳米线并且移除指定结区中的牺牲材料的情况下，在结构的指定沟道区中的纳米线上引入间隔体和牺牲或虚设栅极电极并且相邻于间隔体引入电介质材料之后的图4的结构。
图7示出在将源极和漏极实现为纳米线并且其形成有包覆材料的情况下，在结构的指定沟道区中的纳米线上引入间隔体和牺牲或虚设栅极电极并且相邻于间隔体引入电介质材料之后的图4的结构。
图8示出在将源极和漏极实现为代替指定结区中的纳米线和牺牲材料的生长或沉积的材料的情况下，在结构的指定沟道区中的纳米线上引入间隔体和牺牲或虚设栅极电极并且相邻于间隔体引入电介质材料之后的图4的结构。
图9示出在牺牲栅极电极的移除之后的图5的结构，留下相邻于结区的间隔体。
图10示出在沟道区中的牺牲层材料的移除之后的图9的结构。
图11示出在沟道区上的栅极叠层的引入之后的图10的结构。
图12示出在CMOS实施方式中包括衬底上的NMOS器件和PMOS器件的结构的实施例的顶前透视图。
图13是实现一个或多个实施例的插入机构。
图14示出计算设备的实施例。
具体实施方式
本文所述的一个或多个实施例涉及包括布置在沟道区的相对侧上的沟道区和结区的非平面半导体器件(三维器件)。沟道区包括多个纳米线或纳米带，其包括锗材料。在一个这样的实施例中，在栅极环绕配置中，器件的栅极叠层围绕沟道区。
在晶体管沟道中集成不同外延材料(例如III-V族化合物材料或锗(Ge))所要面对的主要问题之一是在那些材料和硅之间的晶格失配和抑制在外延过程期间的缺陷形成的能力。在一个实施例中，包括锗材料的纳米线或纳米带在具有类似于锗的晶格结构的材料上外延地形成。这样的材料的例子是III-V族化合物材料，例如砷化镓。
图1-7描述形成半导体器件的过程。在一个实施例中，器件是三维金属氧化物半导体场效应晶体管(MOSFET)，且是隔离器件或是在多个嵌套式器件中的一个器件。如将认识到的，对于一般集成电路，N和P沟道晶体管都可被制造在单个衬底上以形成互补金属氧化物半导体(CMOS)集成电路。此外，可制造额外的互连，以便将这样的器件集成到集成电路内。
图1示出半导体衬底的一部分，例如晶片的一部分的顶侧透视图。衬底110在一个实施例中是硅。在另一实施例中，衬底110是在绝缘体衬底上的硅。在一个实施例中，在衬底110的表面(如所观察到的上表面)是通过外延生长技术引入的硅锗的可选缓冲层。衬底110在某些实例中可因此被理解为包括缓冲层。在衬底110上面，图1示出具有期望纳米线或期望纳米带纳米线三维电路器件的期望长度L、高度H和宽度W尺寸的牺牲鳍状物120。在一个实施例中，牺牲鳍状物120是单晶硅材料，例如衬底110的材料。在一个实施例中，通过将衬底110蚀刻到等于牺牲鳍状物的期望高度H的深度来形成牺牲鳍状物120。在牺牲鳍状物120的形成之后，在图1所示的实施例中，在鳍状物周围(例如在牺牲鳍状物120的相对侧上)引入电介质材料130。在一个实施例中，电介质材料130是氧化物材料。
图2示出在移除牺牲鳍状物120以在电介质材料130中形成沟槽125之后的图1的结构。可通过选择性蚀刻过程来移除牺牲鳍状物120。
图3示出在根据高宽比捕获(ART)方法对纳米线和牺牲材料的交替层进行外延生长之后的图2的结构。图3示出分别在牺牲层140A、140B和140C上外延生长的锗材料的纳米线150A、150B和150C。如在本文使用的词“纳米线”不限于任何特定的形状(例如圆柱形、矩形等)，且因此包括各种横截面形状的纳米带和纳米结构。在一个实施例中，牺牲层140A-C每个都是具有与锗的晶格常数类似的晶格常数的材料。在一个实施例中，牺牲层140A-C每个都是III-V族化合物结构，例如在沟槽125中外延生长的砷化镓(GaAs)。如图3所示，外延生长首先以牺牲层140A开始进行，后面是纳米线150A，后面是牺牲层140B、纳米线150B、牺牲层140C和纳米线150C。因此，牺牲层和纳米线层交替，其中一个牺牲层上一个纳米线。如图3所示，牺牲层140A-C和纳米线150A-C的交替层填充沟槽125。虽然图3和图4示出三个纳米线，但是结构不限于三个纳米线并可包含少于或多于三个纳米线。
图4示出在电介质材料130的凹进之后的图3的结构。在一个实施例中，二氧化硅的电介质材料130被选择性地蚀刻，以便移除电介质材料而不移除纳米线和牺牲材料的层。如所示，凹进继续进行到暴露每个纳米线150A-C的水平。
图5示出在结构的指定沟道区中的纳米线上引入间隔体和牺牲或虚设栅极电极之后的图4的结构。图5示出指定沟道区155，包括间隔体160和沉积在间隔体160之间的牺牲材料165。在一个实施例中，为了形成图5的结构，栅极电介质材料(例如二氧化硅)作为均厚层沉积在图4的结构上，后面是牺牲或虚设栅极材料(例如多晶硅)也作为均厚层沉积在栅极电介质材料上。牺牲或虚设栅极材料和栅极电介质材料然后被图案化为在指定沟道区155中的牺牲或虚设栅极165和栅极电介质。间隔体材料膜(例如具有比二氧化硅的介电常数小的介电常数的电介质材料(低k电介质)，例如氮化硅(SiN)或硅碳氮(SiCN))然后被沉积和蚀刻以形成间隔体160。然后，源极和漏极在指定结区180A和180B中形成。
存在实现源极和漏极的不同的可能性。在一个实施例中，可以使用在指定结区180A和180B中的纳米线150A-150C，就如同其间具有牺牲材料140A-C。典型地，纳米线150A-C可在指定结区180A和180B中被暴露，并被掺杂有适当的掺杂剂，后面是电介质材料170的均厚沉积以形成ILD0。这种实施方式在图5中示出。
在图6所示的另一实施例中，源极和漏极的实施方式涉及在指定结区180A和180B中的牺牲材料140A-C的移除和纳米线150A-C被掺杂。典型地，纳米线150A-C和牺牲材料140A-C最初将被暴露，然后接下来将是相对于纳米线150A-C选择性地移除牺牲材料140A-C的蚀刻过程。对于砷化镓的牺牲材料，可通过基于盐酸的蚀刻相对于锗纳米线来选择性地移除这样的材料。然后可掺杂纳米线150A-C，后面是电介质材料170的均厚沉积。
在图7所示的另一实施例中，源极和漏极的实施方式涉及在指定结区180A和180B中的牺牲材料140A-C的移除和在纳米线150A-C上的包覆材料的引入。典型地，纳米线150A-C和牺牲材料140A-C将被暴露，后面是如在图6的实施方式中所述的牺牲材料的选择性移除。然后将通过外延过程在每个纳米线150A-C周围引入包覆材料152，例如掺杂硅锗或掺杂锗。后面将是电介质材料170的均厚沉积。
在图8所示的再一实施例中，源极和漏极的实施方式涉及纳米线150A-C的移除和牺牲材料150A-C的移除以及用源极和漏极材料对所移除的材料的替换。典型地，电介质材料可在指定结区180A和180B中形成。然后，掩蔽和蚀刻过程可用于移除纳米线150A-C和牺牲材料140A-C，后面是外延过程以引入源极和漏极材料，例如掺杂硅锗或掺杂锗或掺杂硅锗和掺杂锗的组合。图8示出在指定结区中代替纳米线150A-C和牺牲材料140A-C而形成的源极156和漏极158。
图5-8中的每个实施方式示出：例如二氧化硅或低k电介质材料的电介质材料170沉积在相邻于间隔体160的指定结区180A和180B上，且电介质材料被抛光以暴露牺牲或虚设栅极165。
使用图5所示的源极和漏极的实施方式，图9示出在牺牲栅极电极的移除之后的图5的结构，留下分别相邻于结区180A和180B的间隔体160，并界定栅极电极区或沟道区155。在一个实施例中，通过选择性蚀刻过程来移除例如多晶硅树脂的虚设栅极。
图10示出在沟道区155中的牺牲层材料的移除之后的图9的结构。在一个实施例中，对于砷化镓的牺牲层材料，可通过基于盐酸的蚀刻而相对于锗纳米线来选择性地移除这样的材料。在结区180A和结区180B中，牺牲层140A-140C的材料——如果仍然存在——被电介质材料170保护而免受蚀刻过程。图10典型地示出在结区180A中的电介质材料170被移除以示出在结区中的牺牲层140A-140C的材料的保留和在沟道区155中的这样的材料的移除。在一些实施例中，在牺牲材料被从沟道区蚀刻出来之后，牺牲材料的部分或结构可仍然保留在间隔体160内。
图11示出在沟道区155上的栅极叠层的引入之后的图10的结构。栅极叠层在一个实施例中包括栅极电介质190和栅极电极195。在一个实施例中，栅极电介质190是二氧化硅或低k电介质材料，且栅极电极195是金属材料。图11示出环绕栅极配置，其中电介质层190分别围绕纳米线150A、150B和纳米线150C中的每个，且栅极电极195围绕每个栅极电介质。高k材料的栅极电介质可由原子层沉积过程引入，且栅极金属可由物理沉积过程引入。在栅极叠层的形成之后，可产生与结区180A和180B的接触，以及与栅极电极195的接触以形成用于器件100的电连接。在一个实施例中，包括锗纳米线的三维纳米线结构限定适合于PMOS器件的锗金属氧化物半导体场效应晶体管(MOSFET)。这样的器件可连同NMOS器件一起合并在CMOS逻辑应用中。MOSFET提供最小短沟道效应，因为器件的栅极长度(Lg)按比例缩小。上面所述的器件结构使作为PMOS的锗与例如作为NMOS的硅或III-V族的集成成为可能，以在晶片(例如硅树脂晶片)上形成CMOS而不需要基于晶片的厚缓冲层。此外，可通过增加在每个器件上的锗纳米线的数量或通过垂直地增加电线的厚度(例如纳米线的高度尺寸)来按比例增加器件驱动电流而不牺牲布局密度。
图12示出包括非平面金属氧化物半导体场效应晶体管(MOSFET)的硅或SOI衬底的一部分的实施例。结构200例如是集成电路或芯片的一部分。特别地，图12示出在CMOS的衬底上集成的两个多栅极器件。应认识到，衬底可包含多得多的这种器件以及不同的器件(例如平面器件)。参考图12，结构200包括硅或SOI的衬底200。在硅衬底210上面的是缓冲层220。在一个实施例中，缓冲层220是硅锗缓冲器，例如Si0.3Ge0.7材料，其在一个实施例中被通过生长技术引入到衬底210上。缓冲层220具有几百纳米(nm)的典型厚度。
在一个实施例中，布置在缓冲层220的表面上的(如所观察的)是n型晶体管器件230和p型晶体管器件240。N型晶体管器件230包括布置在缓冲层220的表面125上的鳍状物2310。鳍状物2310的典型材料是III-V族化合物半导体材料，例如砷化铟镓(InGaAs)材料。在一个实施例中，鳍状物2310具有大于高度尺寸的长度尺寸L。典型的长度范围是大约(onthe order of)10nm到1毫米(mm)，而典型的高度范围是大约5nm到200nm。器件230的n型晶体管的鳍状物2310是从缓冲层220的表面延伸的三维主体。三维主体在图12中被示为矩形主体，但应认识到，在这样的主体的处理中，真正的矩形形式可能是使用可用的工具作业不可实现的，且会产生其它形状。典型形状包括但不限于梯形形状(例如基底比顶部宽)和弓形形状。
在鳍状物2310上面的是典型地由高K材料——例如但不限于氧化铝(Al2O3)或氧化铪(HfO2)——构成的具有大约3nm的典型厚度的栅极电介质层2330。
在栅极电介质层2330上面的是栅极电极2320。栅极电极2320是例如金属材料，例如但不限于金属氮化物、金属碳化物、金属硅化物、铪、锆、钛、钽、铝、钌、钯、铂、钴或镍。
栅极电极2320用布置在栅极之下的侧面中的沟道区分离器件的源极和漏极区。沟道区布置在栅极之下的鳍状物2310中。以这种方式，不是如同平面晶体管操作一样电流在栅极之下的平面中流动，而是电流如所示的那样在鳍状物的顶侧和相对的侧壁上流动。
图12还示出p型晶体管器件240，其例如是在缓冲层220的表面上形成的三维器件。P型晶体管器件240包括具有矩形形状的所示鳍状物2410。在一个实施例中，p型鳍状物2410是在如上面关于图1-11所述的器件的结区中的锗纳米线和牺牲材料的交替层和在沟道区中的锗的纳米线的复合结构。在栅极环绕配置中围绕沟道区中的纳米线的是典型地由高K材料构成的栅极电介质层2430(例如但不限于具有大约3nm的典型厚度的Al2O3或HfO2)，以及例如上面所述的材料的金属栅极的栅极电极2420。
为了指示CMOS配置，将器件230和器件240的栅极和漏极示为被连接。
图13示出包括一个或多个实施例的插入机构300。插入机构300是用于将第一衬底302桥接到第二衬底304的中间衬底。第一衬底302可以是例如集成电路管芯。第二衬底304可以是例如存储器模块、计算机母板或另一集成电路管芯。通常，插入机构300的目的是将连接扩展到较宽的间距或将连接重新布线到不同的连接。例如，插入机构300可将集成电路管芯耦合到球栅阵列(BGA)306，其可随后耦合到第二衬底304。在一些实施例中，第一和第二衬底302/304附接到插入机构300的相对侧。在其它实施例中，第一和第二衬底302/304附接到插入机构300的同一侧。在另外的实施例中，三个或更多个衬底借助于插入机构300来互连。
插入机构300可由环氧树脂、纤维玻璃加强的环氧树脂、陶瓷材料或聚合物材料(例如聚酰亚胺)形成。在另外的实施方式中，插入机构可由交替的刚性或柔性材料形成，这些材料可包括上面所述的用于在半导体衬底中使用的相同的材料，例如硅、锗和其它III-V族和IV族材料。
插入机构可包括金属互连308和过孔310，包括但不限于穿硅过孔(TSV)312。插入机构300还可包括嵌入式器件314，包括无源和有源器件两者。这样的器件包括但不限于电容器、去耦电容器、电阻器、电感器、熔丝、二极管、变压器、传感器和静电放电(ESD)器件。更复杂的器件——例如射频(RF)器件、功率放大器、功率管理器件、天线、阵列、传感器和MEMS器件——也可在插入机构300上形成。
根据实施例，可在插入机构300的制造中使用本文公开的装置或过程。
图14示出根据一个实施例的计算设备400。计算设备400可包括多个部件。在一个实施例中，这些部件附接到一个或多个母板。在备选的实施例中，这些部件被制造到单个片上系统(SOC)管芯而不是母板上。在计算设备400中的部件包括但不限于集成电路管芯402和至少一个通信芯片408。在一些实施方式中，通信芯片408被制造为集成电路管芯402的部分。集成电路管芯402可包括CPU 404以及常常作为高速缓存存储器来使用的管芯上存储器406，其可由例如嵌入式DRAM(eDRAM)或自旋转移扭矩存储器(STTM或STTM-RAM)的技术提供。
计算设备400可包括可以或可以不物理地和电气地耦合到母板或被制造在SoC管芯内的其它部件。这些其它部件包括但不限于易失性存储器410(例如DRAM)、非易失性存储器412(例如ROM或闪存)、图形处理器单元414(GPU)、数字信号处理器416、密码处理器442(在硬件内执行密码算法的专用处理器)、芯片组420、天线422、显示器或触摸屏显示器424、触摸屏控制器426、电池428或其它电源、功率放大器(未示出)、全球定位系统(GPS)设备444、罗盘430、运动协处理器或传感器432(其可包括加速度计、陀螺仪和罗盘)、扬声器434、照相机436、用户输入设备438(例如键盘、鼠标、手写笔和触控板)和大容量存储设备440(例如硬盘驱动器、紧致盘(CD)、数字通用盘(DVD)等)。
通信芯片408实现用于数据往返计算设备400的传送的无线通信。术语“无线”及其派生词可用于描述可通过使用经由非固体介质的经调制电磁辐射来传递数据的电路、设备、系统、方法、技术、通信信道等。该术语并不暗示相关的设备不包含任何电线，虽然在一些实施例中它们可以不包含电线。通信芯片408可实现多种无线标准或协议中的任一个，包括但不限于Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物以及被指定为3G、4G、5G和更高代的任何其它无线协议。计算设备400可包括多个通信芯片408。例如，第一通信芯片408可专用于较短距离无线通信，例如Wi-Fi和蓝牙，而第二通信芯片408可专用于较长距离无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算设备400的处理器404包括根据上面所述的实施例形成的一个或多个器件，例如三维晶体管。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将该电子数据转换成可存储在寄存器和/或存储器中的其它电子数据的任何设备或设备的部分。
通信芯片408也可包括根据上面所述的实施例形成的一个或多个器件，例如晶体管或金属互连。
在另外的实施例中，容纳在计算设备400内的另一部件可包含根据上面所述的实施方式形成的一个或多个器件，例如三维晶体管或金属互连。
在各种实施例中，计算设备400可以是膝上型计算机、上网本计算机、笔记本计算机、超级本计算机、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、桌上型计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器或数字视频记录器。在另外的实施方式中，计算设备400可以是处理数据的任何其它电子设备。
例子
下面的例子涉及实施例。
例子1是一种装置，包括三维半导体主体，三维半导体主体包括沟道区和布置在沟道区的相对侧上的结区，三维半导体主体包括多个纳米线，纳米线包括在结区中由第二材料分离的相应的平面中布置的锗材料，其中第二材料的晶格常数类似于锗材料的晶格常数；以及布置在沟道区上的栅极叠层，栅极叠层包括布置在栅极电介质上的栅极电极。
在例子2中，例子1所述的第二材料包括III族和V族化合物材料。
在例子3中，例子1或例子2所述的第二材料包括砷化镓。
在例子4中，例子1-3所述的栅极叠层围绕在沟道区中的多个纳米线中的每个。
例子5是一种装置，其包括布置在衬底上的堆叠布置中的多个纳米线，每个纳米线包括锗材料；围绕多个纳米线中的每个的栅极叠层，栅极叠层包括栅极电介质和栅极电极；在栅极叠层的相对侧上的一对间隔体；被限制到间隔体内的区域和在纳米线之间的多个III-V族材料结构；以及源极区和漏极区，每个区被限定在栅极叠层的相对侧上。
在例子6中，多个纳米线和多个III-V族材料结构延伸到源极和漏极区内，并且其中例子5所述的III-V族材料包括与锗材料的晶格常数类似的晶格常数。
在例子7中，例子5或例子6所述的第二材料包括III族和V族化合物材料。
在例子8中，例子5或例子6所述的牺牲材料包括砷化镓。
例子9是一种方法，包括：在衬底上的分离平面中形成多个纳米线，多个纳米线中的每个包括锗材料并通过牺牲材料而与相邻纳米线分离；将栅极叠层布置在指定沟道区中的多个纳米线上，栅极叠层包括电介质材料和栅极电极。
在例子10中，例子9所述的牺牲材料包括与多个纳米线的锗材料的晶格常数类似的晶格常数。
在例子11中，例子9或例子10所述的牺牲材料包括砷化镓。
在例子12中，例子9所述的形成多个纳米线包括使多个纳米线中的每个在牺牲材料的相应层上外延地生长。
在例子13中，在形成多个纳米线之前，例子12所述的方法包括在半导体衬底上的电介质材料中形成沟槽，并且形成多个纳米线包括在沟槽中形成多个纳米线。
在例子14中，在形成多个纳米线之后，例子13所述的方法包括移除电介质材料。
在例子15中，在移除电介质材料之后，例子14所述的方法包括在指定沟道区中的多个纳米线上形成牺牲栅极；以及在为结区指定的区域中的多个纳米线上形成电介质材料。
在例子16中，例子15所述的方法还包括移除牺牲栅极材料。
在例子17中，例子16所述的方法还包括移除在指定沟道区中的牺牲材料。
在例子18中，例子17所述的形成栅极叠层包括在多个纳米线中的每个周围形成栅极叠层。
在例子19中，例子18所述的栅极电极包括金属材料。
在例子20中，例子9或例子10所述的指定沟道区没有牺牲材料。
所示实施方式的上面的描述——包括在说明书摘要中所述的内容——并非旨在是无遗漏的或将本发明限制到所公开的精确形式。虽然在本文中为了例证性目的描述了本发明的具体实施方式和例子，但是各种等效修改在本发明范围内都是可能的，如相关领域中的技术人员将认识到的。
可以按照上面的详细描述对本发明进行这些修改。在下面的权利要求中使用的术语不应被解释为将本发明限制到在说明书和权利要求中公开的具体实施方式。相反，本发明的范围应完全由下面的权利要求确定，所述权利要求应根据权利要求解读的已确立的原则来解释。

Claims (20)

1.一种装置，包括：
三维半导体主体，其包括沟道区和布置在所述沟道区的相对侧上的结区，所述三维半导体主体包括：
多个纳米线，其包括在所述结区中由第二材料分离的锗材料，其中所述第二材料的晶格常数类似于所述锗材料的晶格常数；以及
栅极叠层，其布置在所述沟道区上，所述栅极叠层包括布置在所述栅极电介质上的栅极电极。
2.如权利要求1所述的装置，其中所述第二材料包括III族和V族化合物材料。
3.如权利要求1所述的装置，其中所述第二材料包括砷化镓。
4.如权利要求1所述的装置，其中所述栅极叠层围绕在所述沟道区中的所述多个纳米线中的每个纳米线。
5.一种装置，包括：
布置在衬底上的堆叠布置中的多个纳米线，每个纳米线包括锗材料；
围绕所述多个纳米线中的每个纳米线的栅极叠层，所述栅极叠层包括栅极电介质和栅极电极；
在所述栅极叠层的相对侧上的一对间隔体；
被限制到所述间隔体内的区域并且在所述纳米线之间的多个III-V族材料结构；以及
源极区和漏极区，所述源极区和所述漏极区中的每一个被限定在所述栅极叠层的相对侧上。
6.如权利要求5所述的装置，其中所述多个纳米线和所述多个III-V族材料结构延伸到所述源极区和所述漏极区内，并且其中所述III-V族材料包括与所述锗材料的晶格常数类似的晶格常数。
7.如权利要求5所述的装置，其中所述第二材料包括III族和V族化合物材料。
8.如权利要求5所述的装置，其中所述牺牲材料包括砷化镓。
9.一种方法，包括：
在衬底上的分离平面中形成多个纳米线，所述多个纳米线中的每个纳米线包括锗材料并通过牺牲材料而与相邻的纳米线分离；
将栅极叠层布置在指定沟道区中的所述多个纳米线上，所述栅极叠层包括电介质材料和栅极电极。
10.如权利要求9所述的方法，其中所述牺牲材料包括与所述多个纳米线的锗材料的晶格常数类似的晶格常数。
11.如权利要求10所述的方法，其中所述牺牲材料包括砷化镓。
12.如权利要求9所述的方法，其中形成所述多个纳米线包括使所述多个纳米线中的每个纳米线在所述牺牲材料的相应层上外延地生长。
13.如权利要求12所述的方法，其中在形成所述多个纳米线之前，所述方法包括：
在半导体衬底上的电介质材料中形成沟槽，并且形成所述多个纳米线包括在所述沟槽中形成所述多个纳米线。
14.如权利要求13所述的方法，其中在形成所述多个纳米线之后，所述方法包括移除所述电介质材料。
15.如权利要求14所述的方法，其中在移除所述电介质材料之后，所述方法包括：
在所述指定沟道区中的所述多个纳米线上形成牺牲栅极；以及
在为结区指定的区域中的所述多个纳米线上形成电介质材料。
16.如权利要求15所述的方法，还包括移除所述牺牲栅极材料。
17.如权利要求16所述的方法，还包括移除在所述指定沟道区中的所述牺牲材料。
18.如权利要求17所述的方法，其中形成所述栅极叠层包括在所述多个纳米线中的每个纳米线周围形成所述栅极叠层。
19.如权利要求18所述的方法，其中所述栅极电极包括金属材料。
20.如权利要求9所述的方法，其中所述指定沟道区没有所述牺牲材料。
CN201580080411.9A 2015-06-27 2015-06-27 具有GAAS作为牺牲层的Ge纳米线晶体管 Pending CN107690704A (zh)

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US10249740B2 (en) 2019-04-02
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US20190189770A1 (en) 2019-06-20
US20180138289A1 (en) 2018-05-17
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