TWI697962B - 具有砷化鎵作為犧牲層的鍺奈米線電晶體 - Google Patents

具有砷化鎵作為犧牲層的鍺奈米線電晶體 Download PDF

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TWI697962B
TWI697962B TW105116139A TW105116139A TWI697962B TW I697962 B TWI697962 B TW I697962B TW 105116139 A TW105116139 A TW 105116139A TW 105116139 A TW105116139 A TW 105116139A TW I697962 B TWI697962 B TW I697962B
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nanowires
sacrificial
gate
gate stack
channel region
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TW105116139A
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TW201709345A (zh
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威利 瑞奇曼第
馬修 梅茲
凡 雷
傑克 卡瓦萊羅斯
薩納斯 珈納
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美商英特爾股份有限公司
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    • B—PERFORMING OPERATIONS; TRANSPORTING
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Abstract

一種裝置，其包含三維半導體本體，其包含通道區域和設置在該通道區域的相對側的接面區域，該三維半導體本體包含複數條奈米線，其包含設置在由第二材料在該接面區域分開的各自平面的鍺材料，其中該第二材料的晶格常數係類似於該鍺材料的晶格常數；以及閘極堆疊，其設置在該通道區域上，該閘極堆疊包含設置在閘極介電質上的閘極電極。一種方法，其包含在基板上單獨的平面中形成複數條奈米線，該複數條奈米線中的每一條包含鍺材料並且藉由犧牲材料與相鄰的奈米線分開；在特定通道區域中的該複數條奈米線上設置閘極堆疊，該閘極堆疊包含介電材料和閘極電極。

Description

具有砷化鎵作為犧牲層的鍺奈米線電晶體
包含具有低帶隙包覆層的通道區域的非平面半導體裝置的半導體裝置。
在過去的幾十年中，積體電路中的特性縮放一直是不斷增長的半導體產業背後的驅動力。縮放到越來越小的特性使得能夠在半導體晶圓的有限面積上增加功能單元的密度。例如，縮小電晶體尺寸使得晶片上的記憶體裝置的增加數量的成立，使得製造的產品具有增加的容量。驅動了更大的容量，但也不是沒有問題。最佳化每個裝置的性能的必要性變得日益顯著。
由於隨著降低的雜質散射的低有效質量，由III-V族化合物半導體材料系統形成的半導體裝置在電晶體通道中提供格外高的載子遷移率。III族和V族是指在元素週期表的第13-15組的半導體材料的元件的位置(以前的III-V族)。這樣的裝置提供高驅動電流的性能，並且呈現用於未來的低功率、高速邏輯應用的希望。
100‧‧‧裝置
110‧‧‧基板
120‧‧‧犧牲鰭
125‧‧‧溝槽
130‧‧‧介電材料
140A‧‧‧犧牲層
140B‧‧‧犧牲層
140C‧‧‧犧牲層
150A‧‧‧奈米線
150B‧‧‧奈米線
150C‧‧‧奈米線
152‧‧‧覆蓋材料
155‧‧‧通道區域
156‧‧‧源極
158‧‧‧汲極
160‧‧‧犧牲材料
165‧‧‧犧牲材料
170‧‧‧介電材料
180A‧‧‧接面區域
180B‧‧‧接面區域
190‧‧‧閘極介電質
195‧‧‧閘極電極
200‧‧‧結構
210‧‧‧基板
220‧‧‧緩衝層
300‧‧‧中介層
302‧‧‧第一基板
304‧‧‧第二基板
306‧‧‧球閘陣列(BGA)
308‧‧‧金屬互連
310‧‧‧通孔
312‧‧‧穿透矽通孔(TSV)
314‧‧‧嵌入式裝置
400‧‧‧計算裝置
402‧‧‧積體電路晶粒
404‧‧‧處理器
406‧‧‧晶粒上記憶體
408‧‧‧通訊晶片
410‧‧‧揮發性記憶體
412‧‧‧非揮發性記憶體
414‧‧‧圖形處理單元
416‧‧‧數位訊號處理器
420‧‧‧晶片組
422‧‧‧天線
424‧‧‧觸控螢幕顯示器
426‧‧‧觸控螢幕控制器
428‧‧‧電池
430‧‧‧羅盤
432‧‧‧運動協同處理器或感測器
434‧‧‧揚聲器
436‧‧‧相機
438‧‧‧用戶輸入裝置
440‧‧‧大容量儲存裝置
442‧‧‧加密處理器
444‧‧‧全球定位系統裝置
圖1顯示半導體基板的一部分，如具有形成在其上的犧牲鰭和鄰近該犧牲鰭的介電材料的晶圓的一部分的上視圖。
圖2顯示在移除犧牲鰭以在介電材料中形成溝槽之後圖1的結構。
圖3顯示在根據高寬比捕獲(ART)方法來磊晶生長奈米線和犧牲材料的交替層之後圖2的結構。
圖4顯示在介電材料的凹陷之後圖3的結構。
圖5顯示在結構的特定通道區域中的奈米線上的間隔物和犧牲或偽閘極電極和鄰近於以在犧牲材料上的奈米線的源極和汲極的實現的間隔物的介電材料的引入之後圖4的結構。
圖6顯示當在特定接面區域中的奈米線和犧牲材料被移去，在結構的特定通道區域中的奈米線上的間隔物和犧牲或偽閘極電極和鄰近於以源極和汲極的實現的間隔物的介電材料的引入之後圖4的結構。
圖7顯示當奈米線具有形成在其上的包覆材料，在結構的特定通道區域中的奈米線上的間隔物和犧牲或偽閘極電極和鄰近於以源極和汲極的實現的間隔物的介電材料的引入之後圖4的結構。
圖8顯示當在特定接面區域中取代奈米線和 犧牲材料的生長或沉積材料，在結構的特定通道區域中的奈米線上的間隔物和犧牲或偽閘極電極和鄰近於以源極和汲極的實現的間隔物的介電材料的引入之後圖4的結構。
圖9顯示在移除犧牲閘極電極留下相鄰於接面區域的間隔物之後圖5的結構。
圖10顯示在通道區域中的犧牲層材料去除之後圖9的結構。
圖11顯示在通道區域上的閘極堆疊的引入之後圖10的結構。
圖12顯示包含在CMOS實現中的基板上NMOS裝置和PMOS裝置的結構的實施例的上前視圖。
圖13是實現一或多個實施例的中介層。
圖14顯示計算裝置的實施例。
【發明內容及實施方式】
本文所描述的一或多個實施例關於非平面半導體裝置(三維裝置)，包含設置在通道區域的相對側上的通道區域和接面區域。通道區域包含含有鍺材料的多條奈米線或奈米帶。在一個這樣的實施例中，該裝置的閘極堆疊圍繞在閘極全圍繞配置中的通道區域。
在電晶體通道中不同磊晶材料(如III-V族複合材料或鍺(Ge))的整合面臨的主要問題之一是這些材料和矽之間的晶格失配，以及在磊晶過程中抑制缺陷形成的能力。在一個實施例中，包含鍺材料的奈米線或奈米帶 係磊晶地形成在具有類似於鍺的晶格結構的材料上。這種材料的例子為III-V族複合材料，例如砷化鎵。
圖1~7描述一種形成半導體裝置的程序。在一個實施例中，該裝置是一種三維金屬氧化物半導體場效電晶體(MOSFET)，並且是獨立的裝置或者是在複數個嵌套裝置中的一個裝置。如將被理解的是，對於典型的積體電路，N和P通道電晶體兩者可在單一基板上被製造以形成互補金屬氧化物半導體(CMOS)積體電路。此外，額外的互連可以被製造以將這樣的裝置整合成積體電路。
圖1顯示半導體基板，如晶圓的一部分的一部分的上視圖。在一個實施例中，基板110為矽。在另一個實施例中，基板110為絕緣體上矽基板。在一個實施例中，在基板110的表面(如圖所示的較上方表面)上的是藉由磊晶生長技術引入矽鍺的可選緩衝層。在某些情況下，基板110因此可以理解為包含緩衝層。覆蓋基板110，圖1顯示具有所需的長度L、高度H和寬度W、所需奈米線或所需奈米帶奈米線的三維電路裝置的尺寸的犧牲鰭120。在一個實施例中，犧牲鰭120是單晶矽材料，如基板110的材料。在一個實施例中，犧牲鰭120係藉由將基板110蝕刻到等於犧牲鰭的希望高度H的深度來形成。在形成犧牲鰭120之後，在圖1中所示的實施例中，介電材料130圍繞著鰭(例如，在犧牲鰭120的相對側)被引入。在一個實施例中，介電材料130為氧化物材料。
圖2顯示在移除犧牲鰭120以在介電材料130 中形成溝槽125之後圖1的結構。犧牲鰭120可藉由選擇性蝕刻程序被移除。
圖3顯示在根據高寬比捕獲(ART)方法來磊晶生長奈米線和犧牲材料的交替層之後圖2的結構。圖3顯示分別磊晶生長在犧牲層140A、140B和140C上的鍺材料的奈米線150A、150B和150C。這裡所用的用語奈米線不局限於任何特定的形狀(例如，圓柱形、矩形等)，並因此包含奈米帶和各種橫截面形狀的奈米結構。在一個實施例中，犧牲層140A~C中的每一個為具有類似於鍺的晶格常數的晶格常數的材料。在一個實施例中，犧牲層140A~C中的每一個為III-V族化合物的結構，如在溝槽125中磊晶生長的砷化鎵(GaAs)。如圖3所示，磊晶生長，首先於犧牲層140A，接著奈米線150A，接著犧牲層140B、奈米線150B、犧牲層140C和奈米線150C進行。由此，犧牲層和與每一奈米線交替的奈米線層形成在犧牲層上。如在圖3中所示，犧牲層140A~C和奈米線150A~C的交替層填充溝槽125。雖然圖3和4顯示三條奈米線，該結構並不限於三條奈米線並且可以包含少於或多於三條奈米線。
圖4顯示在介電材料130的凹陷之後圖3的結構。在一個實施例中，二氧化矽的介電材料130被選擇性地蝕刻，以移除該介電材料，並且不移除奈米線和犧牲材料層。如圖所示，凹陷繼續到暴露奈米線150A~C中的每一個的程度。
圖5顯示在該結構的特定通道區域中的奈米線上間隔物和犧牲或偽閘極電極引入之後圖4的結構。圖5顯示特定通道區域155，其包括間隔物160和沉積在間隔物160之間的犧牲材料165。在一個實施例中，用以形成圖5的結構，閘極介電材料(例如，二氧化矽)係沉積作為在圖4的結構上的覆面，隨後沉積犧牲或偽閘極材料(例如，多晶矽)也作為在閘極介電材料上的覆面。該犧牲或偽閘極材料和閘極介電材料接著在特定的通道區域155被圖案化成犧牲或偽閘極165和閘極介電質。隔離物材料膜(例如，具有小於二氧化矽(低k介電質)的介電常數的介電常數的介電材料，如氮化矽(SiN)或矽、氮化碳(SiCN))接著被沉積並蝕刻以形成間隔物160。接著，源極和汲極被形成在特定接面區域180A和180B中。
對於源極和汲極實現有不同的可能性。在一個實施例中，在特定接面區域180A和180B中的奈米線150A~150C可以被使用作為與犧牲材料140A~C交錯。代表性地，奈米線150A~C可以在特定接面區域180A和180B中被暴露並以合適的摻雜物來摻雜，隨後覆面沉積介電材料170以形成ILD0。此實現在圖5中顯示。
在另一實施例中，在圖6中顯示，源極和汲極實現關於在特定接面區域180A和180B和摻雜的奈米線150A~C中的犧牲材料140A~C的移除。代表性地，奈米線150A~C和犧牲材料140A~C首先被曝露，接著 蝕刻程序將跟隨選擇性相對於奈米線150A~C的去除犧牲材料140A~C。對於砷化鎵的犧牲材料，這種材料可被選擇性地藉由鹽酸酸系蝕刻相對於鍺奈米線被移除。奈米線150A~C可以接著被摻雜，接著沉積介電材料170。
在進一步的實施例中，在圖7中顯示，源極和汲極實現關於在特定接面區域180A和180B中去除犧牲材料140A~C並且在奈米線150A~C上引入包覆材料。代表性地，奈米線150A~C和犧牲材料140A~C將被暴露，隨後如圖6的實現中描述的，犧牲材料選擇性地移除。覆蓋材料152，諸如摻雜的矽鍺或摻雜的鍺將隨後藉由圍繞奈米線150A~C中的每一個的磊晶程序的方式被引入。介電材料170的覆面沉積將會跟隨。
在圖8中顯示的更進一步實施例中，源極和汲極實現關於奈米線150A~C的去除和犧牲材料140A~C的去除和以源極和汲極材料置換去除的材料。代表性地，介電材料可在特定接面區域180A和180B中被形成。接著，掩模和蝕刻程序可被用於去除奈米線150A~C和犧牲材料140A~C，隨後磊晶程序引入源極和汲極材料，如摻雜的矽鍺或摻雜的鍺或摻雜的矽鍺和摻雜的鍺的組合。圖8顯示替代奈米線150A~C和犧牲材料140A~C形成在特定接面區域中的源極156和汲極158。
圖5~8的實現中的每一個顯示介電材料170，例如，二氧化矽或低k介電材料係沉積在相鄰於間隔物160的特定接面區域180A和180B，並且介電材料被 打磨以暴露犧牲或偽閘極165。
使用在圖5所示的源極和汲極實現，圖9顯示在移除犧牲閘極電極165之後圖5的結構，分別留下相鄰於接面區域180A和接面180B的間隔物160，並且定義閘極電極區域或通道區域155。在一個實施例中，例如，多晶矽的偽閘極，係藉由選擇性蝕刻程序被移除。
圖10顯示在通道區域155中的犧牲層材料去除之後圖9的結構。在一個實施例中，對於砷化鎵的犧牲層材料，這種材料可被選擇性地藉由鹽酸酸系蝕刻相對於鍺奈米線被移除。在接面區域180A和接合區域180B中，犧牲層140A~140C的材料，如果仍然存在，是由介電材料170免受任何蝕刻程序。圖10代表性地顯示在接面區域180A被移除的介電材料170以說明保留接面區域中的犧牲層140A~140C的材料，並且在通道區域155中移除這種材料。在一些實施例中，犧牲材料的部分或結構仍可以在犧牲材料被從通道區域蝕刻出來之後保留在間隔物160內。
圖11顯示在通道區域155上的閘極堆疊的引入之後圖10的結構。在一個實施例中，閘極堆疊包含閘極介電質190和閘極電極195。在一個實施例中，閘極介電質190為二氧化矽或低K介電材料，並且閘極電極195為金屬材料。圖11顯示分別圍繞奈米線150A、150B和奈米線150C中的每一個的介電層190的全圍繞閘極配置，並且閘極電極195圍繞閘極介電質中的每一個。高k 材料的閘極介電質可藉由原子層沉積程序被引入，並且閘極金屬可以藉由物理沉積程序被引入。在閘極堆疊形成之後，可以形成到接面區域180A和180B，以及到閘極電極195的接點以形成用於裝置100的電連接。在一個實施例中，包含鍺奈米線的三維奈米線結構定義適合用於PMOS裝置的鍺金屬氧化物半導體場效電晶體(MOSFET)。這種裝置可與NMOS裝置一起結合於CMOS邏輯應用。當裝置的閘極長度(Lg)被向下縮放，該MOSFET提供最小短通道效應。上述的裝置結構使得作為PMOS的鍺與，例如，作為NMOS的矽或III-V族的整合以形成晶圓(例如，矽晶圓)上的CMOS，而不需要基於晶圓的厚緩衝層。此外，裝置的驅動電流可向上縮放而不需要藉由增加每一裝置上的鍺奈米線數目或藉由垂直地增加線的厚度(例如，奈米線的高度尺寸)來犧牲佈局密度。
圖12顯示包含非平面金屬氧化物半導體場效電晶體(MOSFET)的矽或SOI基板的一部分的實施例。例如，結構200是積體電路或晶片的一部分。具體地，圖12顯示整合在用於CMOS的基板上的兩個多閘極裝置。可以理解的是，基板可以包含許多這樣的裝置以及不同的裝置(例如，平面的裝置)。參見圖12，結構200包含矽或SOI的基板210。覆蓋矽基板210的是緩衝層220。在一個實施例中，緩衝層220為矽鍺緩衝器，諸如被引入的Si0.3Ge0.7材料，在一個實施例中，藉由生長技術在基板210上。緩衝層220具有幾百奈米(nm)的代表性厚 度。
在一個實施例中，設置在緩衝層220的表面上(如圖所示)的是n型電晶體裝置230和p型電晶體裝置240。N型電晶體裝置230包含被設置在緩衝層220的表面125的鰭2310。一種用於鰭2310的表示材料為III-V族化合物半導體材料，如砷化銦鎵(InGaAs)材料。在一個實施例中，鰭2310具有大於高度尺寸的長度尺寸L。代表性長度範圍是在10奈米到1毫米(mm)的數量級，並且代表性高度範圍是在5奈米到200奈米的數量級。裝置230的n型電晶體的鰭2310是從緩衝層220的表面延伸的三維體。在圖12中顯示的三維體為矩形體，但可以理解的，在這些本體的處理中，真正的矩形形狀可能不是可以用工具來完成，並且可能會導致其它形狀。代表性的形狀包含但不限於梯形形狀(例如，基部寬於頂部和拱形狀)。
覆蓋鰭2310的是代表性地由具有3奈米數量級的代表性厚度的高K材料，如，但不限於氧化鋁(Al2O3)或氧化鉿(HfO2)構成的閘極介質層2330。
覆蓋閘極介電層2330的是閘極電極2320。閘極電極2320為，例如，金屬材料，如，但不限於金屬氮化物、金屬碳化物、金屬矽化物、鉿、鋯、鈦、鉭、鋁、釕、鈀、鉑、鈷或鎳。
閘極電極2320將具有設置在該閘極下方的通道區域的裝置的源極和汲極區域分開。通道區域係設置在 閘極下方的鰭2310中。以這種方式，電流不是如同平面電晶體操作，流動在閘極下方的平面，電流是如圖示在鰭的頂側和相對側壁上流動。
圖12也顯示，例如，形成在緩衝層220的表面上的三維裝置的p型電晶體裝置240。p型電晶體裝置240包含顯示具有矩形形狀的鰭2410。在一個實施例中，p型鰭2410為如在上面參考圖1~11描述的裝置的接面區域中的鍺奈米線和犧牲材料的交替層的複合結構，和通道區域中的鍺奈米線。圍繞在閘極全圍繞配置中的通道區域中的奈米線的是具有3奈米數量級的代表性厚度的代表性高K材料，如，但不限於Al2O3或HfO2的閘極介電層2430，以及，例如，上述材料的金屬閘極的閘極電極2420。
為了表示CMOS配置，裝置230和裝置240的閘極和汲極顯示為被連接。
圖13顯示包括一或多個實施例的中介層300。中介層300是用於將第一基板302橋接到第二基板304的居間基板。第一基板302可以是，例如，積體電路晶粒。第二基板304可以是，例如，記憶體模組、電腦主機板，或另一積體電路晶片。通常，中介層300的目的是散佈連接到更寬的間距或重新路由到不同連接的連接。例如，中介層300可以將積體電路晶粒耦接到可以隨後被耦接到第二基板304的球閘陣列(BGA)306。在一些實施例中，第一和第二基板302/304被附接到中介層300的相 對側。在其它實施例中，第一和第二基板302/304被附接到中介層300的相同側。在進一步的實施例中，三個或更多的基板是藉由中介層300的方式被互連。
中介層300可以由環氧樹脂、玻璃纖維增強環氧樹脂、陶瓷材料或聚合物材料，如聚酰亞胺形成。在進一步的實現中，中介層可以由替代的可以包括上述在半導體基板中使用的相同材料，如矽、鍺以及其它III-V族和IV族的材料的剛性或柔性材料來形成。
中介層可以包括金屬互連308和通孔310，其包含但不限於穿透矽通孔(TSV)312。中介層300可以進一步包括嵌入式裝置314，其包括被動和主動裝置。這樣的裝置包括但不限於電容、解耦電容、電阻、電感、熔斷器、二極體、變壓器、感測器和靜電放電(ESD)裝置。更複雜的裝置，如射頻(RF)裝置、功率放大器、功率管理裝置、天線、陣列、感測器和MEMS裝置也可以在中介層300上形成。
根據實施例，本文揭露的裝置或程序可能使用在中介層300的製造中。
圖14顯示根據本發明的一種實施例的計算裝置400。計算裝置400可以包括多個元件。在一個實施例中，這些元件被附接到一或多個主機板。在替代的實施例中，這些元件被製造到單一系統單晶片(SoC)晶粒上，而不是主機板。在計算裝置400中的元件包括但不限於積體電路晶粒402以及至少一個通訊晶片408。在一些實現 中，通訊晶片408被製造成積體電路晶粒402的一部分。積體電路晶粒402可包括CPU 404以及晶粒上記憶體406，經常被用作快取記憶體，其可以藉由如嵌入式DRAM(eDRAM)或自旋轉移力矩記憶體(STTM或STTM-RAM)的技術來提供。
計算裝置400可包括可能會或可能不會物理地和電性地耦接到主機板或在SoC晶粒內製造的其他元件。這些其它元件包括但不限於揮發性記憶體410(例如，DRAM)、非揮發性記憶體412(例如，ROM或快閃記憶體)、圖形處理單元414(GPU)、數位訊號處理器416、加密處理器442(在硬體中的執行加密演算法的專用處理器)、晶片組420、天線422、顯示器或觸控螢幕顯示器424、觸控螢幕控制器426、電池428或其它電源、功率放大器(未顯示)、全球設置系統(GPS)裝置444、羅盤430、運動協同處理器或感測器432(其可包括加速計、陀螺儀和羅盤)、揚聲器434、相機436、用戶輸入裝置438(如鍵盤、滑鼠、手寫筆和觸控板)和大容量儲存裝置440(如硬碟、光碟(CD)、數位多功能光碟(DVD)等)。
通訊晶片408致使進行資料的轉移到和來自計算裝置400的無線通訊。用語“無線”及其衍生物可以用於描述電路、裝置、系統、方法、技術、通訊通道等，其可以經由非固體介質藉由使用調變的電磁輻射進行資料通訊。該用語不暗示關聯的裝置不包含任何導線，儘管在一 些情況中可能不包含。通訊晶片408可實現任何數目的無線標準或協定，其包括但不限於Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽，其衍生物以及那些被特定為3G、4G、5G和之後的任何其它無線協定。計算裝置400可以包括複數個通訊晶片408。例如，第一通訊晶片408可專用於短範圍無線通訊，如Wi-Fi和藍芽，以及第二通訊晶片408可專用於長範圍無線通訊，如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO和其它。
計算裝置400的處理器404包括一或多個裝置，諸如根據上述實施例形成的三維電晶體。用語“處理器”可以指處理來自暫存器和/或記憶體的電子資料，以轉換該電子資料成可儲存在暫存器和/或記憶體中的其他電子資料的任何裝置或裝置的一部分。
通訊晶片408也可以包含一或多個裝置，諸如根據上述實施例形成的電晶體或金屬互連。
在進一步的實施例中，容納在該計算裝置400內的另一組件可以包含一或多個裝置，諸如根據上述實現形成的三維電晶體或金屬互連。
在各種實施例中，計算裝置400可以是膝上電腦、小筆電、筆記型電腦、超輕薄筆電、智慧手機、平板電腦、個人數位助理(PDA)、極致行動PC、行動電 話、桌上電腦、伺服器、列表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器或者數位錄影機。在另外的實現中，計算裝置400可以是處理資料的任何其它電子裝置。
範例
下面的範例關於實施例。
範例1一種裝置，其包含三維半導體本體，其包含通道區域和設置在該通道區域的相對側的接面區域，該三維半導體本體包含：複數條奈米線，其包含設置在由第二材料在該接面區域分開的各自平面的鍺材料，其中該第二材料的晶格常數係類似於該鍺材料的晶格常數；以及閘極堆疊，其設置在該通道區域上，該閘極堆疊包含設置在閘極介電質上的閘極電極。
在範例2中，範例1的該第二材料包含III族和V族複合材料。
在範例3中，範例1或範例2的該第二材料包含砷化鎵。
在範例4中，範例1~3的該閘極堆疊包圍在該通道區域中的該複數條奈米線中的每一條。
範例5是一種裝置，其包含以堆疊排列配置在基板上的複數條奈米線，每條奈米線包含鍺材料；閘極堆疊，其圍繞該複數條奈米線中的每一條，該閘極堆疊包含閘極介電質和閘極電極；一對間隔件，其在該閘極堆疊 的相對側上；複數個III-V族材料結構，其侷限於該等間隔件之內的區域並且介於該等奈米線之間；以及源極區域和汲極區域，其各定義在該閘極堆疊的相對側上。
在範例6中，該複數條奈米線和該複數個III-V族材料結構延伸至該源極和汲極區域，並且其中範例5的該III-V族材料包含類似於該鍺材料的晶格常數之晶格常數。
在範例7中，範例5或範例6的該第二材料包含III族和V族複合材料。
在範例8中，範例5或範例6的該犧牲材料包含砷化鎵。
範例9是一種方法，其包含在基板上單獨的平面中形成複數條奈米線，該複數條奈米線中的每一條包含鍺材料並且藉由犧牲材料與相鄰的奈米線分開；在特定通道區域中的該複數條奈米線上設置閘極堆疊，該閘極堆疊包含介電材料和閘極電極。
在範例10中，範例9的該犧牲材料包含類似於該複數條奈米線的該鍺材料的晶格常數之晶格常數。
在範例11中，範例9或範例10的該犧牲材料包含砷化鎵。
在範例12中，形成範例9的該複數條奈米線包含將該複數條奈米線中的每一條磊晶地生長在該犧牲材料的相應層上。
在範例13中，在形成該複數條奈米線之前， 範例12的該方法包含以介電材料在半導體基板上形成溝槽以及形成該複數條奈米線包含在該溝槽中形成該複數條奈米線。
在範例14中，在形成該複數條奈米線之後，範例13的該方法包含移除該介電材料。
在範例15中，在移除該介電材料之後，範例14的該方法包含在該特定通道區域中的該複數條奈米線上設置犧牲閘極；以及在特定為接面區域的區域中的該複數條奈米線上形成介電材料。
在範例16中，範例15的該方法進一步包含移除該犧牲閘極材料。
在範例17中，範例16的該方法進一步包含移除在該特定的通道區域中該犧牲材料。
在範例18中，形成範例17的該閘極堆疊包含圍繞該複數條奈米線中的每一條來形成該閘極堆疊。
在範例19中，範例18的該閘極電極包含金屬材料。
在範例20中，範例9或範例10的該特定的通道區域係不含該犧牲材料。
以上所示實現的說明，包括在摘要中所描述的，並非意在窮舉或限制發明為所揭露的精確形式。雖然本發明在此描述的範例的具體實現和範例用於說明性目的，那些相關領域技術人員將理解各種等同修改是可能在本發明的範圍之內。
可以根據上述詳細說明修飾本發明的實施例。在下面的申請專利範圍中使用的用語不應當被解釋為限制本發明在說明書和申請專利範圍中揭露的具體實現。相對的，根據申請專利範圍詮釋的既定原則解釋，發明的範圍完全由下面的申請專利範圍來確定。
100‧‧‧裝置
110‧‧‧基板
120‧‧‧犧牲鰭
130‧‧‧介電材料

Claims (18)

  1. 一種半導體裝置，其包含：三維半導體本體，其包含通道區域和設置在該通道區域的相對側的接面區域，該三維半導體本體包含：複數條奈米線，其包含設置在由第二材料在該接面區域分開的各自平面的鍺材料，其中該第二材料的晶格常數係類似於該鍺材料的晶格常數；以及閘極堆疊，其設置在該通道區域上，該閘極堆疊包含設置在閘極介電質上的閘極電極。
  2. 如申請專利範圍第1項的半導體裝置，其中該第二材料包含III族和V族複合材料。
  3. 如申請專利範圍第1項的半導體裝置，其中該第二材料包含砷化鎵。
  4. 如申請專利範圍第1項的半導體裝置，其中該閘極堆疊包圍在該通道區域中的該複數條奈米線中的每一條。
  5. 一種半導體裝置，其包含：鰭，其包含以堆疊排列配置在基板上的複數條奈米線，每條奈米線包含鍺材料；閘極堆疊，其設置在該鰭的通道區域並且圍繞該複數條奈米線中的每一條，該閘極堆疊包含閘極介電質和閘極電極；以及源極區域和汲極區域，其各定義在該通道區域的相對側上的該鰭中，其中該等奈米線係排列在藉由犧牲材料在 該源極區域和該汲極區域分開的各自平面中，該犧牲材料包含類似於該鍺材料的晶格常數之晶格常數。
  6. 如申請專利範圍第5項的半導體裝置，其中該犧牲材料包含III族和V族複合材料。
  7. 如申請專利範圍第5項的半導體裝置，其中該犧牲材料包含砷化鎵。
  8. 一種半導體裝置的製造方法，其包含：在基板上單獨的平面中形成複數條奈米線，該複數條奈米線中的每一條包含鍺材料並且藉由犧牲材料與相鄰的奈米線分開；在特定通道區域中的該複數條奈米線上設置閘極堆疊，該閘極堆疊包含介電材料和閘極電極，其中該犧牲材料包含類似於該複數條奈米線的該鍺材料的晶格常數之晶格常數。
  9. 如申請專利範圍第8項的方法，其中該犧牲材料包含砷化鎵。
  10. 如申請專利範圍第8項的方法，其中形成該複數條奈米線包含將該複數條奈米線中的每一條磊晶地生長在該犧牲材料的相應層上。
  11. 如申請專利範圍第10項的方法，其中在形成該複數條奈米線之前，該方法包含：以介電材料在半導體基板上形成溝槽以及形成該複數條奈米線包含在該溝槽中形成該複數條奈米線。
  12. 如申請專利範圍第11項的方法，其中在形成該 複數條奈米線之後，該方法包含移除該介電材料。
  13. 如申請專利範圍第12項的方法，其中在移除該介電材料之後，該方法包含：在該特定通道區域中的該複數條奈米線上設置犧牲閘極；以及在特定為接面區域的區域中的該複數條奈米線上形成介電材料。
  14. 如請專利範圍第13項的方法，其進一步包含移除該犧牲閘極材料。
  15. 如請專利範圍第14項的方法，進一步包含移除在該特定的通道區域中該犧牲材料。
  16. 如申請專利範圍第15項的方法，其中形成該閘極堆疊包含圍繞該複數條奈米線中的每一條來形成該閘極堆疊。
  17. 如申請專利範圍第16項的方法，其中該閘極電極包含金屬材料。
  18. 如申請專利範圍第8項的方法，其中該特定的通道區域係不含該犧牲材料。
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