TW201721163A - 識別製程拐點之技術 - Google Patents
識別製程拐點之技術 Download PDFInfo
- Publication number
- TW201721163A TW201721163A TW105129442A TW105129442A TW201721163A TW 201721163 A TW201721163 A TW 201721163A TW 105129442 A TW105129442 A TW 105129442A TW 105129442 A TW105129442 A TW 105129442A TW 201721163 A TW201721163 A TW 201721163A
- Authority
- TW
- Taiwan
- Prior art keywords
- output frequency
- integrated circuit
- inflection point
- aro1
- aro2
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 205
- 230000008569 process Effects 0.000 title claims abstract description 163
- 238000004519 manufacturing process Methods 0.000 claims description 34
- 230000008859 change Effects 0.000 claims description 16
- 239000013078 crystal Substances 0.000 claims description 16
- 238000004891 communication Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 2
- 101100491995 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) aro-1 gene Proteins 0.000 claims 6
- 101100216944 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) aro-2 gene Proteins 0.000 claims 4
- 230000007257 malfunction Effects 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 20
- 230000006870 function Effects 0.000 description 10
- 230000008901 benefit Effects 0.000 description 8
- 230000005669 field effect Effects 0.000 description 8
- 238000003860 storage Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 230000000644 propagated effect Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
- G01R31/3004—Current or voltage test
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562232486P | 2015-09-25 | 2015-09-25 | |
| US15/015,547 US10191106B2 (en) | 2015-09-25 | 2016-02-04 | Techniques to identify a process corner |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201721163A true TW201721163A (zh) | 2017-06-16 |
Family
ID=56990952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW105129442A TW201721163A (zh) | 2015-09-25 | 2016-09-10 | 識別製程拐點之技術 |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US10191106B2 (enExample) |
| EP (1) | EP3353561B1 (enExample) |
| JP (1) | JP2019500575A (enExample) |
| KR (1) | KR20180056761A (enExample) |
| CN (1) | CN108027402B (enExample) |
| BR (1) | BR112018006092A2 (enExample) |
| CA (1) | CA2997532A1 (enExample) |
| TW (1) | TW201721163A (enExample) |
| WO (1) | WO2017053006A1 (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10394982B2 (en) | 2014-02-26 | 2019-08-27 | International Business Machines Corporation | Partial parameters and projection thereof included within statistical timing analysis |
| CN114639610B (zh) * | 2020-12-15 | 2024-06-07 | 长鑫存储技术有限公司 | 工艺角检测电路与工艺角检测方法 |
| CN114138726B (zh) * | 2021-11-12 | 2025-09-09 | 国微集团(深圳)有限公司 | 一种针对存在相邻边均相互垂直的多边形的gdsii版图数据的处理方法 |
| CN114414999A (zh) * | 2022-02-28 | 2022-04-29 | 北京智芯微电子科技有限公司 | 一种芯片工艺角检测电路、方法和芯片 |
| TWI829433B (zh) | 2022-11-16 | 2024-01-11 | 創意電子股份有限公司 | 晶片特性量測方法、測試裝置以及非暫態電腦可讀取媒體 |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0653843A3 (en) * | 1993-11-17 | 1996-05-01 | Hewlett Packard Co | CMOS circuits with adaptive voltage threshold. |
| US5486786A (en) | 1994-08-09 | 1996-01-23 | Lsi Logic Corporation | Process monitor for CMOS integrated circuits |
| US5631596A (en) | 1994-08-09 | 1997-05-20 | Lsi Logic Corporation | Process monitor for CMOS integrated circuits |
| US6850075B1 (en) * | 2000-12-22 | 2005-02-01 | Cypress Semiconductor Corp. | SRAM self-timed write stress test mode |
| US7126365B2 (en) * | 2002-04-16 | 2006-10-24 | Transmeta Corporation | System and method for measuring negative bias thermal instability with a ring oscillator |
| US6894528B2 (en) * | 2002-09-17 | 2005-05-17 | Sun Microsystems, Inc. | Process monitor based keeper scheme for dynamic circuits |
| JP2006041951A (ja) * | 2004-07-27 | 2006-02-09 | Fujitsu Ltd | プロセスばらつき検知装置およびプロセスばらつき検知方法 |
| US7330080B1 (en) | 2004-11-04 | 2008-02-12 | Transmeta Corporation | Ring based impedance control of an output driver |
| US7627839B1 (en) | 2005-11-14 | 2009-12-01 | National Semiconductor Corporation | Process corner indicator and estimation circuit |
| US20090027131A1 (en) * | 2007-07-25 | 2009-01-29 | Shingo Suzuki | Ring oscillators for cmos transistor beta ratio monitoring |
| JP5452983B2 (ja) * | 2009-06-03 | 2014-03-26 | 株式会社メガチップス | プロセスモニタ回路およびプロセス特性の判定方法 |
| WO2011027553A1 (ja) | 2009-09-07 | 2011-03-10 | 日本電気株式会社 | 経年劣化診断装置、経年劣化診断方法 |
| JP5529555B2 (ja) | 2010-01-20 | 2014-06-25 | ルネサスエレクトロニクス株式会社 | 半導体集積回路、動作電圧制御方法 |
| TWI422847B (zh) * | 2010-09-01 | 2014-01-11 | Univ Nat Chiao Tung | 全晶片上寬工作電壓溫度製程電壓的感測系統 |
| US8441310B2 (en) * | 2010-12-07 | 2013-05-14 | Broadcom Corporation | Power control based on dual loop with multiple process detection circuits |
| JP5226094B2 (ja) * | 2011-02-23 | 2013-07-03 | 株式会社半導体理工学研究センター | 半導体記憶装置 |
| US8954764B2 (en) | 2012-03-05 | 2015-02-10 | Csr Technology Inc. | Method and apparatus for dynamic power management |
| US8801281B1 (en) | 2012-05-24 | 2014-08-12 | Pixelworks, Inc. | On-chip temperature detection using an oscillator |
| KR20140023726A (ko) * | 2012-08-17 | 2014-02-27 | 에스케이하이닉스 주식회사 | 반도체 장치, 반도체 시스템 및 그의 모니터링 방법 |
| US9112484B1 (en) * | 2012-12-20 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit process and bias monitors and related methods |
| US8976574B2 (en) * | 2013-03-13 | 2015-03-10 | Qualcomm Incorporated | Process corner sensor for bit-cells |
| JP2017079336A (ja) * | 2014-01-31 | 2017-04-27 | 国立大学法人東北大学 | サイドチャネル攻撃の検知装置、サイドチャネル攻撃の検知装置によるサイドチャネル攻撃の検知方法 |
| CN104101827B (zh) * | 2014-06-25 | 2016-08-31 | 东南大学 | 一种基于自定时振荡环的工艺角检测电路 |
| KR102298158B1 (ko) * | 2014-08-25 | 2021-09-03 | 삼성전자주식회사 | 반도체 장치와 이를 포함하는 위상 동기 회로 |
-
2016
- 2016-02-04 US US15/015,547 patent/US10191106B2/en active Active
- 2016-08-26 CA CA2997532A patent/CA2997532A1/en not_active Abandoned
- 2016-08-26 JP JP2018515037A patent/JP2019500575A/ja not_active Ceased
- 2016-08-26 WO PCT/US2016/049028 patent/WO2017053006A1/en not_active Ceased
- 2016-08-26 EP EP16770592.0A patent/EP3353561B1/en active Active
- 2016-08-26 CN CN201680055568.0A patent/CN108027402B/zh active Active
- 2016-08-26 KR KR1020187011636A patent/KR20180056761A/ko not_active Withdrawn
- 2016-08-26 BR BR112018006092-5A patent/BR112018006092A2/pt not_active IP Right Cessation
- 2016-09-10 TW TW105129442A patent/TW201721163A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| CN108027402A (zh) | 2018-05-11 |
| CN108027402B (zh) | 2020-06-16 |
| BR112018006092A2 (pt) | 2018-10-16 |
| WO2017053006A1 (en) | 2017-03-30 |
| US20170089974A1 (en) | 2017-03-30 |
| JP2019500575A (ja) | 2019-01-10 |
| US10191106B2 (en) | 2019-01-29 |
| EP3353561B1 (en) | 2019-09-18 |
| EP3353561A1 (en) | 2018-08-01 |
| KR20180056761A (ko) | 2018-05-29 |
| CA2997532A1 (en) | 2017-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8575993B2 (en) | Integrated circuit with pre-heating for reduced subthreshold leakage | |
| CN108027402B (zh) | 识别工艺拐点的技术 | |
| US8456247B2 (en) | Monitoring negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI) | |
| JP2010087275A (ja) | 半導体集積回路および電子機器 | |
| US10262985B2 (en) | Circuits and methods for lowering leakage in ultra-low-power MOS integrated circuits | |
| KR102413192B1 (ko) | Nbti 또는 pbit를 모니터링하는 테스트 회로 | |
| CN107210297A (zh) | 中心偏离栅极切割 | |
| Kerber et al. | Assessing device reliability margin in scaled CMOS technologies using ring oscillator circuits | |
| CN109001582B (zh) | 泄漏电流测量电路、集成电路及其系统 | |
| Rzepa et al. | Reliability and variability-aware DTCO flow: Demonstration of projections to n3 FinFET and nanosheet technologies | |
| CN101795126B (zh) | 用于表征工艺变化的系统和方法 | |
| US9319034B2 (en) | Slew based process and bias monitors and related methods | |
| US20120146672A1 (en) | Performance monitor with memory ring oscillator | |
| US8413094B2 (en) | Structure, design structure and process for increasing magnitude of device threshold voltage for low power applications | |
| CN105027214A (zh) | 用于调节存储器阵列的工作电压的系统和方法 | |
| US9514999B2 (en) | Systems and methods for semiconductor line scribe line centering | |
| US9171125B2 (en) | Limiting skew between different device types to meet performance requirements of an integrated circuit | |
| US9262569B2 (en) | Balancing sensitivities with respect to timing closure for integrated circuits | |
| Islam et al. | Reconfigurable delay cell for area-efficient implementation of on-chip MOSFET monitor schemes | |
| TW202014718A (zh) | 用於閘極漏電偵測之感測器 | |
| TWI520488B (zh) | 脈衝式閂鎖裝置及其脈衝式閂鎖器的脈衝信號的產生方法 | |
| Yasufuku et al. | Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS | |
| Lou et al. | Analysis of layout arrangement for CMOS oscillators to reduce overall variation on silicon | |
| CN104967446B (zh) | 一种环形振荡器 | |
| US11165416B2 (en) | Duty cycle and skew measurement and correction for differential and single-ended clock signals |