TW201709268A - 元件層製造方法、分離裝置、捲繞有層積體之卷體、層積體、以及分離方法 - Google Patents

元件層製造方法、分離裝置、捲繞有層積體之卷體、層積體、以及分離方法 Download PDF

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Publication number
TW201709268A
TW201709268A TW105111100A TW105111100A TW201709268A TW 201709268 A TW201709268 A TW 201709268A TW 105111100 A TW105111100 A TW 105111100A TW 105111100 A TW105111100 A TW 105111100A TW 201709268 A TW201709268 A TW 201709268A
Authority
TW
Taiwan
Prior art keywords
layer
laminate
peeling
support substrate
base material
Prior art date
Application number
TW105111100A
Other languages
English (en)
Chinese (zh)
Inventor
Takayoshi Nirengi
Naoki Oota
Original Assignee
Dainippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dainippon Printing Co Ltd filed Critical Dainippon Printing Co Ltd
Publication of TW201709268A publication Critical patent/TW201709268A/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Laminated Bodies (AREA)
TW105111100A 2015-04-28 2016-04-08 元件層製造方法、分離裝置、捲繞有層積體之卷體、層積體、以及分離方法 TW201709268A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015091830 2015-04-28
JP2015156221 2015-08-06

Publications (1)

Publication Number Publication Date
TW201709268A true TW201709268A (zh) 2017-03-01

Family

ID=57199236

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105111100A TW201709268A (zh) 2015-04-28 2016-04-08 元件層製造方法、分離裝置、捲繞有層積體之卷體、層積體、以及分離方法

Country Status (3)

Country Link
JP (1) JP2017034225A (ja)
TW (1) TW201709268A (ja)
WO (1) WO2016175014A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7275683B2 (ja) * 2018-03-15 2023-05-18 大日本印刷株式会社 配線基板、及び配線基板の製造方法
JP7362378B2 (ja) * 2019-09-12 2023-10-17 株式会社東芝 キャリア及び半導体装置の製造方法
JP7521258B2 (ja) 2020-05-26 2024-07-24 Toppanホールディングス株式会社 基板ユニット、基板ユニットの製造方法及び半導体装置の製造方法
CN118380337B (zh) * 2024-06-25 2024-09-06 日月新半导体(威海)有限公司 一种半导体晶片的封装结构及其形成方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5473413B2 (ja) * 2008-06-20 2014-04-16 株式会社半導体エネルギー研究所 配線基板の作製方法、アンテナの作製方法及び半導体装置の作製方法
JP2012018952A (ja) * 2010-07-06 2012-01-26 Furukawa Electric Co Ltd:The プリント配線基板、半導体装置、プリント配線基板の製造方法及び半導体装置の製造方法
JP5882266B2 (ja) * 2013-08-20 2016-03-09 藤森工業株式会社 表面保護フィルム、及びそれが貼合された光学部品
JP6201610B2 (ja) * 2013-10-08 2017-09-27 富士通株式会社 電子装置の製造方法及び回路基板

Also Published As

Publication number Publication date
JP2017034225A (ja) 2017-02-09
WO2016175014A1 (ja) 2016-11-03

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