TW201705423A - 承載體、封裝基板、電子封裝件及其製法 - Google Patents

承載體、封裝基板、電子封裝件及其製法 Download PDF

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Publication number
TW201705423A
TW201705423A TW104124868A TW104124868A TW201705423A TW 201705423 A TW201705423 A TW 201705423A TW 104124868 A TW104124868 A TW 104124868A TW 104124868 A TW104124868 A TW 104124868A TW 201705423 A TW201705423 A TW 201705423A
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layer
circuit
carrier
electronic package
electronic
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TW104124868A
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TWI550814B (zh
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程呂義
呂長倫
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矽品精密工業股份有限公司
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Priority to TW104124868A priority Critical patent/TWI550814B/zh
Priority to CN201510532879.9A priority patent/CN106409802A/zh
Priority to US14/982,142 priority patent/US9818635B2/en
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Publication of TWI550814B publication Critical patent/TWI550814B/zh
Publication of TW201705423A publication Critical patent/TW201705423A/zh
Priority to US15/729,842 priority patent/US10211082B2/en

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Abstract

一種電子封裝件，係包括：具有相對之第一表面及第二表面之線路結構、設於該第一表面上之分隔層、設於該分隔層上之金屬層、設於該金屬層上之電子元件、以及包覆該電子元件之封裝層，其中，該第一表面具有第一線路層，該第二表面具有第二線路層，且該第一線路層之最小線路寬度係小於該第二線路層之最小線路寬度。藉由直接將高I/O功能之電子元件接置於該線路結構上，因而不需使用一含核心層之封裝基板，故可減少該電子封裝件之厚度。本發明復提供承載體、封裝基板、及該電子封裝件之製法。

Description

承載體、封裝基板、電子封裝件及其製法
本發明係有關一種電子封裝件，尤指一種具輕薄短小化之電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1圖係為習知3D晶片堆疊之半導體封裝件1之剖面示意圖。如第1圖所示，提供一矽中介板(Through Silicon interposer，簡稱TSI)10，該矽中介板10具有相對之置晶側10a與轉接側10b、及連通該置晶側10a與轉接側10b之複數導電矽穿孔(Through-silicon via，簡稱TSV)100，且該轉接側10b上具有複數線路重佈層(Redistribution layer，簡稱RDL)101。並將間距較小之半導體晶片19之電極墊190係藉由複數銲錫凸塊102電性結合至該置晶側10a上，再以底膠192包覆該些銲錫凸塊102，且形成封裝膠體18於該矽中介板10上，以覆蓋該半導體晶片19。接著，於該線路重佈層101上藉由複數如凸塊之導電元件103電性結合間距較大之封裝基板17之銲墊170，並以底膠172包覆該些導電元件103。
製作該半導體封裝件1時，係先將該半導體晶片19置放於該矽中介板10上，再將該矽中介板10以該些導電元件103接置於該封裝基板17上，之後形成該封裝膠體18。
惟，習知半導體封裝件1之製法中，使用該矽中介板10作為該半導體晶片19與該封裝基板17之間訊號傳遞的介質，因需具備一定深寬比之控制(即該導電矽穿孔100之深寬比為100um/10um)，才能製作出適用的矽中介板10，因而往往需耗費大量製程時間及化學藥劑之成本，進而提高製程難度及製作成本。
再者，該封裝基板17具有含玻纖材料之核心層，致使該封裝基板17厚度相當厚，因而不利於產品之輕薄短小化。
又，當該半導體晶片19具有細線寬線距的高I/O數時，則需加大該矽中介板10之面積，因而相對應之封裝基板17的面積亦需加大，故不利於產品之輕薄短小化。
另外，習知半導體封裝件1之製法中，係於該封裝膠 體18覆蓋該半導體晶片19後，再進行電性測試，如此，若該線路重佈層101發生問題，則無法重工，將造成昂貴晶片之損失。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：線路結構，係具有相對之第一表面及第二表面，且該第一表面具有第一線路層，該第二表面具有第二線路層，其中，該第一線路層之最小線路寬度係小於該第二線路層之最小線路寬度；分隔層，係形成於該線路結構之第一表面上；金屬層，係形成於該分隔層上且電性連接該第一線路層；電子元件，係設於該線路結構之之第一表面上且電性連接該金屬層；以及封裝層，係形成於該線路結構上，以包覆該電子元件。
本發明亦提供一種承載體，係包括：承載件；分隔層，係結合於該承載件上；以及線路結構，係具有相對之第一表面及第二表面，且該第一表面結合於該分隔層上，而該第一表面具有第一線路層，該第二表面具有第二線路層，其中，該第一線路層之最小線路寬度係小於該第二線路層之最小線路寬度。
本發明又提供一種封裝基板，係包括：線路結構，係具有相對之第一表面及第二表面，且該第一表面具有第一線路層，該第二表面具有第二線路層，其中，該第一線路 層之最小線路寬度係小於該第二線路層之最小線路寬度；分隔層，係形成於該線路結構之第一表面上；以及金屬層，係形成於該分隔層上且電性連接該第一線路層。
本發明復提供一種電子封裝件之製法，係包括：提供一具有相對之第一表面及第二表面之線路結構，且該線路結構之第一表面上形成有分隔層，而該第一表面具有第一線路層，該第二表面具有第二線路層，其中，該第一線路層之最小線路寬度係小於該第二線路層之最小線路寬度；形成金屬層於該分隔層上，且該金屬層電性連接該第一線路層；設置電子元件於該線路結構之第一表面上，且該電子元件電性連接該金屬層；以及形成封裝層於該線路結構之第一表面上，以包覆該電子元件。
前述之製法中，該分隔層形成於該線路結構上的製程係包括：提供一具有該分隔層之承載件；形成該線路結構於該分隔層上；以及移除該承載件，使該分隔層形成於該線路結構上。例如，該承載件係為矽晶圓材質，且該分隔層作為蝕刻停止層，並以研磨及蝕刻方式移除該承載件；或者，該承載件係為玻璃材質，係以加熱方式或照光方式，使該分隔層失去部分黏性，以移除該承載件。
前述之製法中，復包括於設置該電子元件之前，對該金屬層與該線路結構進行電性測試。又包括於進行電性測試之前，形成導電層於該金屬層上。
前述之電子封裝件及其製法中，復包括形成複數導電元件於該線路結構之第二表面上。
前述之承載體、封裝基板、電子封裝件及其製法中，該分隔層係熱化二氧化矽層或黏著層
前述之承載體、封裝基板、電子封裝件及其製法中，該金屬層係為圖案化線路層。
前述之承載體、封裝基板、電子封裝件及其製法中，於形成該金屬層前，先形成至少一輔助層於該分隔層上，使該金屬層復形成於該輔助層上。
由上可知，本發明之承載體、封裝基板、電子封裝件及其製法，主要藉由直接將高I/O功能之電子元件接置於該線路結構上，因而不需使用一含核心層之封裝基板，故可減少該電子封裝件之厚度。
再者，藉由該第一線路層對應具有細線寬線距的高I/O數之電子元件，因而無需增加該線路結構的面積，故有利於產品之輕薄短小化。
又，相較於習知技術，本發明之製法無需製作TSV，故可降低製作成本。
另外，本發明之製法係先進行該線路結構之電性測試，再接置電子元件，故可降低電子元件之損失。
1‧‧‧半導體封裝件
10‧‧‧矽中介板
10a‧‧‧置晶側
10b‧‧‧轉接側
100‧‧‧導電矽穿孔
101‧‧‧線路重佈層
102,230‧‧‧銲錫凸塊
103,25‧‧‧導電元件
17‧‧‧封裝基板
170‧‧‧銲墊
172‧‧‧底膠
18‧‧‧封裝膠體
19‧‧‧半導體晶片
190‧‧‧電極墊
2‧‧‧電子封裝件
2a‧‧‧承載體
2b‧‧‧封裝基板
20‧‧‧承載件
200‧‧‧分隔層
200’,200”‧‧‧輔助層
21‧‧‧線路結構
21’‧‧‧第一線路部
21”‧‧‧第二線路部
21a‧‧‧第一表面
21b‧‧‧第二表面
210‧‧‧介電層
210’,300‧‧‧絕緣層
211‧‧‧內部線路層
211’‧‧‧第一線路層
211”‧‧‧第二線路層
212‧‧‧凸塊底下金屬層
22,22’‧‧‧金屬層
220,220’‧‧‧導電層
23‧‧‧電子元件
24‧‧‧封裝層
30‧‧‧承載板
31‧‧‧導電層
第1圖係為習知半導體封裝件之剖面示意圖；以及第2A至2G圖係為本發明之電子封裝件之製法的剖面示意圖；其中，第2E’圖係為第2E圖之另一態樣，第2G’及2G”圖係為第2G圖之另一態樣之局部放大圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示，形成一分隔層200於一承載件20上。
於本實施例中，該承載件20係為半導體板體，例如虛設矽晶圓(dummy Si wafer)、玻璃或高分子板材，且該分隔層200係例如熱化二氧化矽層(thermal SiO2 layer)或黏著層(較佳為有機黏著層)。
如第2B圖所示，形成一線路結構21於該承載件20之分隔層200上。
於本實施例中，該線路結構21係具有相對之第一表面 21a與第二表面21b，並以該第一表面21a結合於該分隔層200上，且該線路結構21係具有複數介電層210、內部線路層211、形成於該第一表面21a之介電層210上之第一線路層211’、及形成於該第二表面21b之介電層210上之第二線路層211”，其中，該第一線路層211’之最小線路寬度小於該第二線路層211”之最小線路寬度，且該第二線路層211”形成有凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)212。
再者，該線路結構21可由線路重佈層(Redistribution layer，簡稱RDL)製程完成。
又，由於線路之線寬越小時，需先於該承載件20之表面先形成細線寬之線路層(如0.7um)，再形成中線寬之線路層(如5um)，再形成寬線寬之線路層(10um)，之後再做更寬的線路層，以此類推。此乃由於細線路層及其上之介電層平整度較平，如此往上作寬線路時，可符合上層線路層平整度要求；反之，先於該承載件20之表面依序往上形成寬、中、細之線路層，則由於底部之寬線路層平整度不夠平整，則往上無法依序製作出中、細之線路層，而產生線路層之可靠度問題。
因此，較佳地，當線路的線寬(L)太小時(如小於或等於1um以下時)，可先於晶圓製程完成第一線路部21’之佈線(含絕緣層210’)，再送至後端封裝製程進行第二線路部21”之佈線，使該線路結構21包含相疊之第一線路部21’與第二線路部21”，且該第一線路部21’係結合該分隔 層200。
然而，本發明之第一線路部21’係可包括但不限於一定要用晶圓製程完成(如大於或等於1um以上時)。例如，由於晶圓製程之線路層用之介電層需以化學氣相沉積(Chemical vapor deposition，簡稱CVD)形成氮化矽或氧化矽，其成本較高，故可採用一般非晶圓製程方式形成線路，即採用成本較低之高分子介電層，如聚醯亞胺(Polyimide，簡稱PI)、聚對二唑苯(Polybenzoxazole，簡稱PBO)以塗佈方式形成於線路之間進行絕緣。
另外，該承載件20、分隔層200與線路結構21係作為一承載體2a。
如第2C圖所示，設置一承載板30於該線路結構21之第二表面21b上。
於本實施例中，該承載板30係藉由一絕緣層300(如黏膠)結合於該線路結構21上，且該絕緣層300包覆部分該承載體2a之寬線路側之表面。
如第2D圖所示，移除該承載件20，使該分隔層200保留於該線路結構21上。
於本實施例中，當該承載件20係為矽晶圓材質時，先研磨移除該承載件20之大部分材質，再利用蝕刻方式清除剩餘該承載件20之材質，以保留該分隔層200，其中該分隔層200係作為蝕刻停止層。當該承載件20係為玻璃材質時，係以加熱方式或照光方式(如UV光)，使該分隔層200失去部分黏性，以移除該承載件20而保留該分隔層 200，其中該分隔層200係作為黏著層使用。
如第2E圖所示，以電鍍方式形成一金屬層22於該分隔層200上，且該金屬層22電性連接該線路結構21之第一線路層211’，再對該金屬層22與該線路結構21進行電性測試。其中該電性測試係為選擇性步驟。
於本實施例中，該金屬層22係以電鍍方式製作，故會先形成導電層(圖略)於該分隔層200上，且該金屬層22係為圖案化線路層，其包含電性接觸墊(pad)與導電跡線(trace)。然而，有關線路製程之方式繁多，如RDL製程，故於此不再贅述。
再者，先進行線路測試，待確認線路結構21與金屬層22正常後，再接置良好裸晶粒(Known Good Die，簡稱KGD)，即後述之電子元件23，以防止最終封裝件因線路結構21與金屬層22製作瑕疵，發生良率不佳之問題。
又，電測方式(如第2E’圖所示)，可例如於進行電性測試之前，可先形成一導電層31於部分該金屬層22上，以構成迴路(部分該金屬層22沒有接觸該導電層31，若全部該金屬層22接觸該導電層31，會發生短路)，待電性測試結束後，再移除該導電層31。
另外，該金屬層22、分隔層200與線路結構21係作為一封裝基板2b。
如第2F圖所示，設置複數電子元件23於該線路結構21之第一表面21a上方。接著，形成一封裝層24於該分隔層200與該線路結構21之第一表面21a上方，以包覆該 電子元件23。
於本實施例中，該電子元件23係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
再者，該電子元件23係以覆晶方式電性連接該線路結構21。具體地，該電子元件23藉由複數銲錫凸塊230電性結合至該金屬層22上。或者，該電子元件23亦可以打線方式電性連接該金屬層22。
又，形成該封裝層24之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材。
如第2G圖所示，移除該承載板30及該絕緣層300，以外露該線路結構21之第二表面21b。接著，形成複數導電元件25於該線路結構21之第二表面21b上之凸塊底下金屬層212上。
於本實施例中，該導電元件25係為銲球、金屬凸塊或金屬針等，其結合於該凸塊底下金屬層212上並電性連接該第二線路層211”。
再者，該線路結構21之第二表面21b與該第二線路層211”作為植球側，使該電子封裝件2可直接電性連接至電路板(圖略)，而無需再藉由額外之封裝基板，故可降低製作成本，且可降低終端產品之整體厚度。
又，製作該金屬層22所用之導電層與該分隔層200之結合性較差，故於形成該金屬層22前，如第2G’圖所示， 可先形成一輔助層200’於該分隔層200上，再形成該導電層220於該輔助層200’上，之後形成該金屬層22於該輔助層200’與該分隔層200上。
另外，如第2G”圖所示，可進行多層佈設，即形成另一輔助層200”係形成於該輔助層200’上，以藉由該些導電層220,220’電鍍形成複數金屬層22,22’於該些輔助層200’,200”與該分隔層200上，且最外側之金屬層22’用以電性連接該電子元件23。具體地，該另一輔助層200”係如聚醯亞胺(PI)、聚對二唑苯(PBO)、SiO2或SiNX材。
本發明之製法中，藉由直接將高I/O功能之電子元件23接置於該線路結構21之第一線路層211’上，因而不需使用一含核心層之封裝基板，故可減少該電子封裝件2之厚度。
再者，藉由該第一線路層211’對應具有細線寬的高I/O數之電子元件23，因而無需增加該線路結構21的面積，故有利於產品之輕薄短小化。
又，相較於習知技術，本發明之製法無需製作TSV，故可降低製作成本。
另外，製作該線路結構21後，可先進行電性測試，以確認該線路結構21內之線路製作良好，再接置昂貴之功能晶片(電子元件23)，如此可降低損失。
本發明提供一種電子封裝件2，係包括：一線路結構21、一分隔層200、一金屬層22、複數電子元件23、以及一封裝層24。
所述之線路結構21係具有相對之第一表面21a及第二表面21b，且該第一表面21a具有第一線路層211’，該第二表面21b具有第二線路層211”，其中，該第一線路層211’之最小線路寬度係小於該第二線路層211”之最小線路寬度。
所述之分隔層200係形成於該線路結構21之第一表面21a上。
所述之金屬層22係形成於該分隔層200上且電性連接該第一線路層211’。
所述之電子元件23係設於該分隔層200上且電性連接該金屬層22。
所述之封裝層24係形成於該分隔層200上，以包覆該電子元件23。
另外，該電子封裝件2復包括複數導電元件25，係形成於該線路結構21之第二表面21b上。
本發明亦可提供一種承載體2a，係包括：一承載件20、一結合於該承載件20上之分隔層200、以及結合於該分隔層200上之線路結構21，該線路結構21係具有相對之第一表面21a及第二表面21b，並以該第一表面21a結合於該分隔層200上，而該第一表面21a具有第一線路層211’，該第二表面21b具有第二線路層211”，其中，該第一線路層211’之最小線路寬度係小於該第二線路層211”之最小線路寬度。
本發明另可提供一種封裝基板2b，係包括：一具有相 對之第一表面21a及第二表面21b之線路結構21、形成於該第一表面21a上之分隔層200、以及形成於該分隔層200上且電性連接該線路結構21之金屬層22，該第一表面21a具有第一線路層211’，該第二表面21b具有第二線路層211”，其中，該第一線路層211’之最小線路寬度係小於該第二線路層211”之最小線路寬度。
於上述中，該分隔層200係熱化二氧化矽層或黏著層。
於上述中，該金屬層22係為圖案化線路層。
於上述中，復包括形成於該分隔層200上之至少一輔助層200’,200”，使該金屬層22,22’復形成於該輔助層200’,200”上。
綜上所述，本發明之承載體、封裝基板、電子封裝件及其製法，係藉由直接將高I/O功能之電子元件接置於該線路結構上，因而不需使用一含核心層之封裝基板，故可減少該電子封裝件之厚度。
再者，藉由該第一線路層對應結合具有細線寬線距的高I/O數之電子元件，因而無需增加該線路結構的面積，故有利於產品之輕薄短小化。
又，本發明之製法無需製作TSV，故可降低製作成本。
另外，製作該線路結構後，先進行電性測試，再接置電子元件，以降低材料損失。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
200‧‧‧分隔層
21‧‧‧線路結構
21’‧‧‧第一線路部
21”‧‧‧第二線路部
21a‧‧‧第一表面
21b‧‧‧第二表面
211’‧‧‧第一線路層
211”‧‧‧第二線路層
212‧‧‧凸塊底下金屬層
22‧‧‧金屬層
23‧‧‧電子元件
24‧‧‧封裝層
25‧‧‧導電元件

Claims (21)

  1. 一種電子封裝件，係包括：線路結構，係具有相對之第一表面及第二表面，且該第一表面具有第一線路層，該第二表面具有第二線路層，其中，該第一線路層之最小線路寬度係小於該第二線路層之最小線路寬度；分隔層，係形成於該線路結構之第一表面上；金屬層，係形成於該分隔層上且電性連接該第一線路層；電子元件，係設於該線路結構之第一表面上且電性連接該金屬層；以及封裝層，係形成於該線路結構上，以包覆該電子元件。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該分隔層係熱化二氧化矽層或黏著層。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該金屬層係為圖案化線路層。
  4. 如申請專利範圍第1項所述之電子封裝件，復包括形成於該分隔層上之至少一輔助層，使該金屬層復形成於該輔助層上。
  5. 如申請專利範圍第1項所述之電子封裝件，復包括複數導電元件，係形成於該線路結構之第二表面上。
  6. 一種承載體，係包括：承載件； 分隔層，係結合於該承載件上；以及線路結構，係具有相對之第一表面及第二表面，且該第一表面結合於該分隔層上，而該第一表面具有第一線路層，該第二表面具有第二線路層，其中，該第一線路層之最小線路寬度係小於該第二線路層之最小線路寬度。
  7. 如申請專利範圍第6項所述之承載體，其中，該分隔層係熱化二氧化矽層或黏著層。
  8. 一種封裝基板，係包括：線路結構，係具有相對之第一表面及第二表面，且該第一表面具有第一線路層，該第二表面具有第二線路層，其中，該第一線路層之最小線路寬度係小於該第二線路層之最小線路寬度；分隔層，係形成於該線路結構之第一表面上；以及金屬層，係形成於該分隔層上且電性連接該第一線路層。
  9. 如申請專利範圍第8項所述之封裝基板，其中，該分隔層係熱化二氧化矽層或黏著層。
  10. 如申請專利範圍第8項所述之封裝基板，其中，該金屬層係為圖案化線路層。
  11. 如申請專利範圍第8項所述之封裝基板，復包括形成於該分隔層上之至少一輔助層，使該金屬層復形成於該輔助層上。
  12. 一種電子封裝件之製法，係包括：提供一具有相對之第一表面及第二表面之線路結構，且於該線路結構之第一表面上形成有分隔層，而該第一表面具有第一線路層，該第二表面具有第二線路層，其中，該第一線路層之最小線路寬度係小於該第二線路層之最小線路寬度；形成金屬層於該分隔層上，且令該金屬層電性連接該第一線路層；設置電子元件於該線路結構之第一表面上，且令該電子元件電性連接該金屬層；以及形成封裝層於該線路結構之第一表面上，以包覆該電子元件。
  13. 如申請專利範圍第12項所述之電子封裝件之製法，其中，該分隔層係熱化二氧化矽層或黏著層。
  14. 如申請專利範圍第12項所述之電子封裝件之製法，其中，該金屬層係為圖案化線路層。
  15. 如申請專利範圍第12項所述之電子封裝件之製法，其中，該分隔層形成於該線路結構上的製程係包括：提供一具有該分隔層之承載件；形成該線路結構於該分隔層上；以及移除該承載件，以令該分隔層形成於該線路結構上。
  16. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該承載件係為矽晶圓材質，且該分隔層作為蝕刻停止層，並以研磨及蝕刻方式移除該承載件。
  17. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該承載件係為玻璃材質，係以加熱方式或照光方式，使該分隔層失去部分黏性，以移除該承載件。
  18. 如申請專利範圍第12項所述之電子封裝件之製法，其中，於形成該金屬層前，先形成至少一輔助層於該分隔層上，使該金屬層復形成於該輔助層上。
  19. 如申請專利範圍第12項所述之電子封裝件之製法，復包括於設置該電子元件之前，對該金屬層與該線路結構進行電性測試。
  20. 如申請專利範圍第19項所述之電子封裝件之製法，復包括於進行電性測試之前，形成導電層於該金屬層上。
  21. 如申請專利範圍第12項所述之電子封裝件之製法，復包括形成複數導電元件於該線路結構之第二表面上。
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