TW201633497A - 低成本封裝體翹曲解決方案 - Google Patents

低成本封裝體翹曲解決方案 Download PDF

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Publication number
TW201633497A
TW201633497A TW104136699A TW104136699A TW201633497A TW 201633497 A TW201633497 A TW 201633497A TW 104136699 A TW104136699 A TW 104136699A TW 104136699 A TW104136699 A TW 104136699A TW 201633497 A TW201633497 A TW 201633497A
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substrate
die
layer
device die
reinforcement layer
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TW104136699A
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English (en)
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TWI620303B (zh
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歐姆卡Ｇ 卡哈迪
尼亭Ａ 戴斯潘迪
德班拉 麥可
巴森Ｍ 奇亞戴
富田佳宏
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英特爾公司
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Abstract

本發明之實施例包括裝置封裝體及形成此等封裝體之方法。在一實施例中，形成一裝置封裝體之該方法可包含在一基板之上形成一強化層。可經由該強化層形成一或多個開口。在一實施例中，可將一裝置晶粒置放至該等開口中之一者中。可藉由回焊定位於該裝置晶粒與該基板之間的一或多個焊料凸塊而將該裝置晶粒接合至該基板。本發明之實施例可包括一模製強化層。替代實施例包括用一黏著層黏著至該基板之該表面的一強化層。

Description

低成本封裝體翹曲解決方案 發明領域
實施例大體上係關於半導體裝置。更具體而言，實施例係關於用於封裝半導體晶粒之方法及裝置。
發明背景
具有焊線之載帶球柵陣列(ball grid array；BGA)或四方扁平無引線(QFN)型封裝體為用於產生低成本電子封裝體之主要解決方案。圖1提供利用焊線之例示性載帶BGA封裝體100的說明。如所說明，封裝體基板110為薄載帶基板。可在載帶基板之表面之上形成導電跡線124。舉例而言，導電跡線可為銅跡線。導電跡線124可由一阻焊劑層112覆蓋。阻焊劑開口128可形成於導電跡線124之數個部分之上以提供開口，在該開口處可接合導線144。導線144可將導電跡線124連接至形成於裝置晶粒130之頂表面上的焊線襯墊146。導線144將晶粒120中之積體電路(未展示)電氣地耦接至封裝體基板110之背面上的焊料凸塊138。導電跡線124可由導電通孔126電氣地耦接至焊料凸塊138。可由晶粒附接膏劑149將裝置晶粒130附接至阻焊層112。整個封裝 體可由囊封層140(諸如，環氧樹脂囊封)覆蓋。
然而，焊線封裝體之使用具有顯著缺點。舉例而言，將導線連接至裝置晶粒130之頂表面導致大於電子封裝體的封裝體厚度，該等電子封裝體利用替代互連技術，諸如，倒裝晶片或受控塌陷晶片連接(controlled collapsed chip connection；C4)技術。另外，用焊線法封裝之裝置晶粒需要額外處理操作以形成焊線襯墊146。
不管與焊線法相關聯之侷限性，由於多個原因，形成於薄且可撓之基板上之裝置封裝體尚未能夠利用倒裝晶片接合。首先，由於載帶基板為薄且可撓的，所以將需要特殊基板處置系統以處理載帶基板。容納基板需要之額外裝備及處理操作導致封裝體之總體成本的增加。另外，倒裝晶片接合可包括質量回焊操作。在質量回焊期間溫度之升高導致載帶基板永久地變形。另外，歸因於熱壓接合(thermal compression bonding；TCB)之高成本，以TCB替代質量回焊製程在經濟上可能並非為可行的。因此，利用TCB而非質量回焊之倒裝晶片接合可能並非為用於在載帶基板上產生低成本電子封裝體之在經濟上可行的製程。
依據本發明之一實施例，係特地提出一種用於形成一裝置封裝體之方法，其包含：在一基板之上形成一強化層，其中一或多個開口通過該強化層被形成；將一裝置晶粒置放至該等開口中之一者中；藉由回焊定位於該裝置晶粒與該基板之間的一或多個焊料凸塊將該裝置晶粒接合 至該基板。
100‧‧‧帶球柵陣列封裝體
110‧‧‧封裝體基板
112、212、312‧‧‧阻焊層
120‧‧‧晶粒
124、224、324‧‧‧導電跡線
126、226、326‧‧‧導電通孔
128、228、328‧‧‧阻焊劑開口
130、230、330、630‧‧‧裝置晶粒
138、234、334、656‧‧‧焊料凸塊
140‧‧‧囊封層
144‧‧‧導線
146‧‧‧焊線襯墊
149‧‧‧晶粒附著膏劑
200、201、202‧‧‧帶倒裝晶片球柵陣列裝置封裝體
210、310‧‧‧載帶基板
220、320、620‧‧‧強化層
221‧‧‧黏著層
223、323‧‧‧邊緣
225、325‧‧‧側壁
229、329、629‧‧‧開口
232、332‧‧‧支柱
236、336‧‧‧底部填充材料
238‧‧‧第二級互連焊球
261、361‧‧‧第一側/第一表面
262‧‧‧第二側
327‧‧‧受控塌陷晶片連接區域/阻焊劑開口區域
338‧‧‧第二級焊料凸塊/第二級互連焊球
350‧‧‧模具
352‧‧‧凹部
354‧‧‧順應層
362、662‧‧‧第二表面
370‧‧‧單體化線
500‧‧‧計算裝置
502‧‧‧板
504‧‧‧處理器
506‧‧‧通訊晶片
610‧‧‧基板
631‧‧‧第二晶粒
636‧‧‧底部填充層
637‧‧‧焊劑材料
655‧‧‧局部記憶體互連件襯墊
G、G1、G2‧‧‧間隙
H‧‧‧高度
T、TR‧‧‧厚度
W‧‧‧寬度
圖1為利用焊線之帶球柵陣列封裝體的橫截面說明。
圖2A至圖2C為根據本發明之實施例的帶倒裝晶片球柵陣列(FCBGA)封裝體的橫截面說明。
圖3A至圖3I為根據本發明之實施例的用於形成帶FCBGA封裝體之製程的橫截面說明。
圖4A為根據本發明之實施例的圖3A中所說明之處理操作的示意性平面圖。
圖4B為根據本發明之實施例的圖3D中所說明之處理操作的示意性平面圖。
圖4C為根據本發明之實施例的圖3E中所說明之處理操作的示意性平面圖。
圖5為根據本發明之實施例的利用半導體封裝體之電腦系統之示意性方塊圖的說明。
圖6A至圖6B為根據本發明之實施例的用於形成包含第二晶粒之FCBGA封裝體之製程的橫截面說明。
較佳實施例之詳細說明
本發明之實施例提供具有對裝置封裝體之經改良翹曲控制的設備及形成此等裝置之方法。在以下描述中，闡述大量特定細節(諸如，特定材料及處理操作)以便提供對本發明之實施例的透徹理解。對於熟習此項技術者將 顯而易見的是，本發明之實施例可在無此等特定細節之情況下加以實踐。在其他情況下，並不詳細描述諸如半導體晶粒之積體電路的熟知特徵以便不會不必要地混淆本發明之實施例。此外，應理解，圖式中展示之各種實施例為例示性表示且不必按比例繪製。
本發明之實施例包括具有由倒裝晶片球柵陣列(FCBGA)接合製程耦接至薄基板之裝置晶粒的裝置封裝體。FCBGA處理之使用通常包括質量回焊操作之使用以便回焊焊料凸塊。如上文所描述，諸如載帶基板之薄聚合物基板在用於焊料凸塊之質量回焊所需要之熱量存在的情況下易受變形影響。因此，本發明之實施例包括在質量回焊操作之前在載帶基板之上形成之強化層。強化層增加基板之硬度且減少由回焊製程導致的載帶基板之翹曲。此外，由於強化層向其他可撓性基板提供剛度，因此本發明之實施例降低處置薄且可撓基板的難度。較硬基板允許在無通常對於此等薄且可撓性基板需要的專用基板處置裝備情況下處置並處理基板。因此，用於形成於厚且剛性之多層基板上之FCBGA封裝體中之處理裝備亦可用於製造可撓性帶FCBGA封裝體。
現參看圖2A，展示根據本發明之實施例的帶FCBGA封裝體200的橫截面說明。本發明之實施例包括載帶基板210，該載帶基板為聚合物基板。藉助於實例，載帶基板210可為聚醯胺或聚醯亞胺材料。載帶基板210可具有一厚度T。藉助於實例，厚度T可小於大約100μm。在一實施 例中，厚度T可為大約75μm或以下。在一實施例中，載帶基板210可為單層載帶基板。額外實施例亦可包括多層載帶基板，諸如包括層合在一起的兩個或兩個以上薄且可撓性層的基板。
可通過載帶基板210形成一或多個導電通孔226。導電通孔226在載帶基板210之第一側261與第二側262之間提供電連接。在一實施例中，導電通孔226可用焊接材料填充。額外實施例包括導電通孔226，該導電通孔為經電鍍通孔，諸如，電鍍銅通孔。通孔226可提供至形成於載帶基板210之第二側262上之第二級互連(second level interconnect；SLI)焊球238的電連接。焊球238可為通常用於電裝置封裝體中之焊接接合的任何焊料，諸如，鉛錫焊料或無鉛焊料。
如所說明，可在載帶基板210之第一側261之上形成導電跡線224。根據一實施例，導電跡線224可為金屬材料，諸如，銅或類似者。導電跡線224提供自經回焊焊料凸塊234至通孔226的電路徑。因此，裝置晶粒230中之積體電路(未展示)可電氣地耦接至載帶基板210之第二側262。在一實施例中，經回焊焊料凸塊234可為受控塌陷晶片連接(C4)凸塊。在一實施例中，可在載帶基板210之第一側261之數個部分之上及導電跡線224之數個部分之上形成阻焊層212。藉助於實例，阻焊層212可為此項技術中已知之任何阻焊劑材料，諸如，聚合材料或環氧樹脂材料)。可將阻焊劑開口228圖案化至阻焊層212中以暴露定位焊料凸塊234 所在的導電跡線224之部分。
根據一實施例，經回焊焊料凸塊234中之每一者可由支柱232電氣地耦接至裝置晶粒230。每一支柱232可提供至形成於裝置晶粒230上或裝置晶粒230中之積體電路(未展示)的電連接。在一實施例中，支柱為金屬材料，諸如，銅、金、鋁或其合金。額外實施例包括支柱，該等支柱包括一或多個層之堆疊。舉例而言，支柱232可包括障壁層、有機表面保護(OSP)層、金屬層或其任何組合。
與僅利用焊料凸塊234之封裝體相比，使用倒裝晶片封裝體中之支柱232提供額外益處。舉例而言，支柱232允許增加之支座高度。此外，支柱232允許接點之間的間距之減小。儘管圖2A中所說明之裝置封裝體200包括支柱232，但實施例並不限於此等組配。舉例而言，可視情況省略支柱232，且經回焊焊料凸塊234可直接耦接至裝置晶粒230。
根據一實施例，可將底部填充材料236沈積在裝置晶粒230下方且在經回焊焊料凸塊234與支柱232之間。在一實施例中，底部填充材料236可為環氧樹脂底部填充材料。在某些實施例中，環氧樹脂底部填充材料236可包括顆粒增強物。舉例而言，底部填充材料236可包括由矽、玻璃或類似者製成之填料微粒。藉助於實例，底部填充材料236可具有允許底部填充材料藉由毛細管底部填充製程施配之黏度。額外實施例可包括具有適合於以不流動底部填充製程使用之黏度的底部填充材料236。通常，不流動底部填充 製程中使用之底部填充材料具有較毛細管底部填充製程中使用之底部填充材料更高的黏度。藉助於實例，底部填充材料可具有介於大約5.0Pa.s與100Pa.s之間的黏度。在一實施例中，底部填充材料236可覆蓋裝置晶粒230之邊緣223的一部分。如所說明，並未在裝置晶粒230之頂表面之上形成底部填充材料236，但實施例並不限於此等組配。舉例而言，可將底部填充材料236沈積至允許在裝置晶粒230之頂表面上形成底部填充材料236的厚度。
本發明之實施例包括在載帶基板210之表面之上形成的強化層220。在圖2A中所說明之特定實施例中，在載帶基板210之第一表面261上之阻焊層212之上形成強化層220。在一額外實施例中，強化層220可與載帶基板及導電跡線224直接接觸。通過強化層220形成之開口229可於載帶基板210上暴露一或多個阻焊劑開口228。根據本發明之一實施例，開口229之寬度W可經大小設定以適應一或多個裝置晶粒230。根據圖2A中所描繪之實施例，開口229之寬度W經大小設定以容納單個裝置晶粒230。根據一實施例，相較於裝置晶粒230之寬度，可形成較大寬度W的開口229。增加開口之寬度W提供開口229之側壁225與裝置晶粒230之邊緣223之間的更大間隙G。間隙G之增加的大小可允許更快地沈積底部填充材料236。因此，可增加封裝製程之輸貫量。
隨著載帶基板210之更多表面區域由強化層220覆蓋，載帶基板210之硬度增加且因此減少翹曲。根據一實 施例，最小化間隙G之大小以便對載帶基板210提供增加之硬度。舉例而言，間隙G之最小大小可取決於毛細管底部填充製程。舉例而言，與具有較低黏度之底部填充材料相比較，具有較高黏度之底部填充材料將需要更大之間隙大小G。藉助於實例，間隙G可小於大約0.5mm。額外實施例可包括介於大約0.5mm與4.0mm之間的間隙G。
在一實施例中，裝置晶粒230可自開口229偏心地安裝。因此，開口之側壁225與裝置晶粒之邊緣223之間的間隙可不相等。舉例而言，裝置晶粒230之側中之一者上的間隙G1可大於或小於裝置晶粒230之相對側上的間隙G﹁2。在圖2B中說明此實施例。圖2B中之FCBGA裝置封裝體201實質上類似於圖2A中所說明之FCBGA裝置封裝體200，唯裝置晶粒230自開口229偏心地安裝外。在此等實施例中，裝置晶粒230之邊緣223與開口229之側壁225之間的第一間隙G1可大於裝置晶粒230之第二邊緣223與開口229之第二側壁225之間的第二間隙G2。偏心地定位裝置晶粒230允許形成足夠大之間隙以允許底部填充材料之施配而無需增加開口229之寬度W。因此，可獲得較大程度之硬度同時仍維持速率，可以該速率沈積底部填充材料236。
返回至圖2A，根據本發明之實施例，可將強化層220模製至載帶基板210。在此等實施例中，強化層220可為適用於模製之材料。藉助於實例，強化層220可為聚合物或環氧樹脂材料。在一實施例中，可選擇所選擇用於強化層220之材料以便匹配載帶基板210之熱膨脹係數(CTE)。藉 助於實例，載帶基板210可具有介於大約10ppm/℃與14ppm/℃之間的CTE。在此等實施例中，可選擇強化層220之CTE以匹配載帶基板220之CTE，且因此強化層220亦可具有介於大約10ppm/℃與14ppm/℃之間的CTE。
可藉由增加或減少包括於用於強化層220之環氧樹脂中之填料材料的量來調變強化層220之CTE。藉助於實例，填料材料可為矽微粒、玻璃微粒或類似者。將強化層220與載帶基板210之CTE值匹配允許在用以將裝置晶粒230附接至載帶基板210之回焊處理期間形成晶粒基板220之翹曲的經改良控制。舉例而言，由於強化層220可自具有實質上與載帶基板210相同之CTE的材料形成，在載帶基板210中不存在將由強化層320與載帶基板310之間的膨脹之不同比率以其他方式產生的褶曲。
可形成強化層220達對載帶基板210提供所需硬度之厚度TR。隨著厚度TR增加，裝置封裝體200之硬度變得更接近於強化層230之硬度。藉助於實例，可選擇強化層220之厚度TR，使得在裝置晶粒230之頂表面上方形成強化層220之頂表面，如圖2A中所展示。額外實施例可包括強化層220，該強化層具有經選擇以使得強化層210之頂表面與裝置晶粒230之頂表面實質上共面或在裝置晶粒230之頂表面下方的厚度。根據一實施例，厚度TR可小於大約100μm。本發明之額外實施例包括可小於大約1.0mm之厚度TR。舉例而言，根據實施例，強化層220之厚度TR可介於大約100μm與1mm之間。
根據一額外實施例，可用黏著層221將強化層220附接至載帶基板210，如圖2C中之FCBGA裝置封裝體202之橫截面說明中所展示。在一實施例中，黏著層221可為此項技術中常用之任何黏著劑。在一實施例中，黏著劑可為層合於載帶基板210之表面、強化層220之表面或兩者之上的一黏著劑層。在一額外實施例中，黏著層可為擴散於載帶基板210之表面、強化層220之表面或兩者之上的膠。藉助於實例，黏著劑可為環氧樹脂、聚酯或丙烯酸材料。
黏著層221之使用允許將與射出模製製程不相容之材料利用於強化層220。舉例而言，在使用黏著層221時，金屬材料亦可用於強化層220。藉助於實例，強化層可為鋼、不鏽鋼、鋁或類似者。根據一額外實施例，強化層220亦可為非金屬材料。藉助於實例，強化層220亦可為聚合材料、玻璃強化環氧樹脂層合物(例如，FR4)、味之素複合膜(Ajinomoto build-up films；ABF)、陶瓷或類似者。
由於此等金屬材料之硬度大體上大於模製材料(諸如，聚合物及環氧樹脂)之硬度，所以使用強化層220之金屬材料為有利的。因此，在模製聚合物或環氧樹脂材料用於強化層220時，與將所需以提供等效硬性裝置封裝體的厚度TR相比，可減少強化層220之厚度TR。因此，在將強化層220與模製至載帶基板210相對地黏著至載帶基板210時，可減少總體封裝體厚度。除包括黏著層221以外，裝置封裝體202可實質上類似於圖2A中所說明之裝置封裝體200。
本發明之實施例能夠在薄基板(諸如，載帶基板)上執行倒裝晶片接合，此係由於在接合製程之前形成強化層。在接合之前形成強化層允許強化層之硬度以防止載帶基板210之翹曲。此外，在接合之前包括強化層允許使用標準倒裝晶片處理裝備，此係由於載帶基板之硬度更接近於通常用於倒裝晶片接合之複合基板的硬度。
現參看圖3A至圖3I，提供根據本發明之實施例的用於形成裝置封裝體的製程。在圖3A處，展示根據本發明之實施例的載帶基板310的橫截面說明。本發明之實施例包括載帶基板310，該載帶基板為聚合物基板。藉助於實例，載帶基板310可為聚醯胺或聚醯亞胺材料。載帶基板310可具有一厚度T。藉助於實例，厚度T可小於大約100μm。在一實施例中，厚度T可為大約75μm或以下。在一實施例中，載帶基板310可為單層載帶基板。額外實施例亦可包括多層載帶基板，諸如包括層合在一起的兩個或兩個以上薄且可撓性層的基板。
可通過載帶基板310形成一或多個導電通孔326。導電通孔326在載帶基板310之第一側361與第二側362之間提供電連接。在一實施例中，可用雷射切除製程使導電通孔圖案化通過載帶基板310。在一實施例中，可用諸如銅的導電材料電鍍通孔326。通孔326可提供至在下文中關於圖3H所描述之後續處理操作中形成於載帶基板310之第二側362上之第二級互連(SLI)焊球338的電連接。
如所說明，可在載帶基板310之第一側361之上形 成導電跡線324。根據一實施例，導電跡線324可為金屬材料，諸如，銅或類似者。在一實施例中，可藉由蝕刻掉層合於載帶基板310之上的導電層之數個部分而形成導電跡線。在一實施例中，可在載帶基板310的第一側361之數個部分之上及導電跡線324之數個部分之上形成阻焊層312。藉助於實例，阻焊層312可為此項技術中已知之任何阻焊劑材料，諸如，聚合材料或環氧樹脂材料。在一實施例中，用網版印刷製程沈積阻焊層312。可將阻焊劑開口328圖案化至阻焊層312中以暴露導電跡線324之部分。如所說明，可將阻焊劑開口328集合在一起以形成多個C4區域327。C4區域中之每一者可為將用倒裝晶片接合製程安裝裝置晶粒之位置，下文更詳細地描述。
現參看圖4A，展示圖3A中所說明之載帶基板310之示意性平面圖。在一實施例中，載帶基板310足夠大以形成多個C4區域327。為簡單起見且不會不必要地混淆本發明之實施例，將每一C4區域327說明為一方框。在一實施例中，每一C4區域327可包括用於將裝置晶粒330連接至導電跡線之多個個別SRO 328(圖4A中未展示)。因此，實施例允許自單一載帶基板310形成多個裝置封裝體。藉助於實例，載帶基板310可為面板級基板、四分之一面板級基板、晶圓級基板或任何其他大小之基板。
現參看圖3B，展示定位於載帶基板310之上的模具350之橫截面說明。在一實施例中，模具350可與阻焊層312接觸。根據一實施例，模具350可為用於射出模製製程 或真空輔助射出模製製程之模具。模具350包括呈所需強化層320之形狀的一或多個凹部352。舉例而言，凹部352之高度H可實質上等於強化層320之所需厚度TR。另外，凹部352以實質上等於強化層320中之開口329之所需寬度W的距離彼此間隔開。
根據一實施例，模具350可包括形成於模具350之面向載帶基板310之第一表面361的表面之上的順應層354。順應層354改良模具之密封且防止模製材料漏泄至C4區域327中。藉助於實例，順應層354可為聚合材料或橡膠材料。在一實施例中，經氟化聚合材料可用於順應層354。在一實施例中，順應層可為足夠順應的以填充SRO 328。根據圖3B中所說明之實施例，模具350包括形成於載帶基板之頂表面361之上的單一組件，然而實施例並不限於此等組配。舉例而言，實施例亦可包括定位於載帶基板310之第二表面362之上的底部模具件。在此實施例中，在模製製程期間可將底部模具件夾持至上部模具件(例如，模具350)。
在已經對準模具350且將其固定至載帶基板310之後，可將模製材料射出至模具350中以形成強化層320，如圖3C中所展示。在一實施例中，射出模製製程或真空輔助射出模製製程可用以將模製材料射出至模具350中。根據一實施例，可選擇模製材料以具有所需CTE。舉例而言，可選擇模製材料之CTE以匹配載帶基板310之CTE。藉助於實例，模製材料之CTE可介於大約10ppm/℃與14ppm/℃之間。額外實施例包括基於諸如黏度的流動特性選擇模製材 料。舉例而言，具有較低黏度之模製材料可允許相對於利用較高黏度材料之模製製程更快地執行模製製程。藉助於實例，模製材料可為環氧樹脂。在一實施例中，模製材料可包括可用以調變強化層320之黏度、CTE及/或硬度之額外填料材料，諸如，矽或玻璃微粒。
現參看圖3D，自載帶基板310之表面移除模具350。凹部352在模具350中之存在導致模製材料採取C4區域327周圍之強化層320的形式如圖4B中之對應平面圖中所展示，強化層320中之開口329可大於C4區域327。儘管將C4區域327說明為實質上集中於強化層320中之正方形開口329內，但實施例並不限於此等組配。舉例而言，C4區域327之外部周界可與強化層320中之開口329之每一側壁不等距。在一實施例中，C4區域327之外部周界距每一壁可為不等距，由於開口329與C4區域327形狀並不相同。舉例而言，C4區域327之外部周界可為實質上正方形，然而開口為實質上矩形。額外實施例包括自強化層320中之開口329偏心的C4區域327。不包括距強化層之側壁等距之C4區域327的實施例可為有益的，此是由於其提供強化層320之側壁與將安裝於C4區域327之上的裝置晶粒330之邊緣之間的更大間隙G。舉例而言，在圖2B中所說明之FCBGA封裝體201中展示此偏心之裝置晶粒及C4區域。
根據一額外實施例，可將強化層320黏著至載帶基板310而非模製至基板上。在此等實施例中，可在將強化層320與載帶基板310對準並附接至該載帶基板之前於強化 層320之底表面上形成黏著層。替代地，可將黏著層塗覆於載帶基板310的部分之上。藉助於實例，黏著劑可為環氧樹脂、聚酯或丙烯酸材料。此實施例將接著遵循下文關於圖3E至圖3I所描述之實質上類似的處理操作且將產生實質上類似於圖2C中所說明之裝置封裝體202之裝置封裝體，且因此本文中將不再重複。
現參看圖3E，將裝置晶粒330於C4區域327之上對準且將其置放至載帶基板310上。在一實施例中，用抓放工具將裝置晶粒置放至載帶基板310上。如圖4C中之對應示意性平面圖中所展示，可將多個裝置晶粒330各自於載帶基板310之C4區域327之上對準且置放。返回至圖3E，在一實施例中，裝置晶粒330包括一或多個支柱332。藉助於實例，可將支柱332對準以使得將支柱332中之每一者於不同SRO 328之上對準。支柱332允許製造自裝置晶粒330中之主動裝置至載帶基板310的電連接。
在一實施例中，支柱為金屬材料，諸如，銅、金、鋁或其合金。額外實施例包括支柱，該等支柱包括一或多個層之堆疊。舉例而言，支柱232可包括障壁層、OSP層、金屬層或其任何組合。在一實施例中，在將裝置晶粒330置放於載帶基板310上之前於支柱332中之每一者上形成焊料凸塊334，諸如，C4凸塊。在一額外實施例中，可在將裝置晶粒330置放至載帶基板310上之前於SRO 328之上各自形成焊料凸塊334。
現參看圖3F，回焊焊料凸塊。在回焊期間，焊料 可填充SRO 328且將裝置晶粒330電氣地耦接至載帶基板310上之跡線324。在一實施例中，回焊為同時回焊焊料凸塊中之每一者的質量回焊。根據一實施例，回焊溫度為足以熔融焊料凸塊之溫度。藉助於實例，回焊溫度可大於大約215℃。額外實施例包括介於大約215℃與260℃之間的回焊溫度。根據一實施例，回焊溫度並不使載帶基板310由於強化層320之存在而實質上或永久地翹曲或以其他方式變形。強化層320之硬度防止翹曲。此外，由於可自具有與載帶基板310實質上相同之CTE的材料形成強化層320，載帶基板310並不在SRO區域327中褶曲。舉例而言，若載帶基板310之CTE與強化層320之CTE不同，則載帶基板310及強化層320可具有不同膨脹率。不同膨脹率可導致載帶基板310之SRO區域327褶曲或以其他方式變形。
在已回焊焊料凸塊334之後，本發明之實施例可包括在經回焊焊料凸塊及互連件周圍施配底部填充材料336。圖3G為在已於焊料凸塊及互連件周圍施配底部填充材料336之後的裝置封裝體之橫截面說明。藉助於實例，底部填充材料336可為環氧樹脂材料。在一實施例中，底部填充材料336可具有適用於毛細管底部填充製程之黏度。在此實施例中，可經由裝置晶粒330之邊緣323與強化層320之側壁325之間的間隙G中之一或多者施配底部填充材料336。
根據一額外實施例，底部填充材料336可為不流動底部填充材料。在使用不流動底部填充材料時，可在將裝置晶粒330置放至載帶基板310上之前於C4區域327之上 施配底部填充材料。在利用不流動底部填充材料之一實施例中，可接著用熱壓接合(TCB)製程將裝置晶粒330接合至載帶基板。
現參看圖3H，展示根據一實施例的在已執行第二級互連(SLI)球附接製程之後的裝置封裝體的橫截面說明。如所說明，實施例包括一或多個第二級焊料凸塊338在載帶基板310之第二表面362上的形成。在一實施例中，可用球滴製程、模板印刷製程、噴射製程或類似者形成第二級焊料凸塊338。藉助於實例，第二級焊料凸塊338中之每一者可由導電跡線324及通過載帶基板310形成之通孔326電氣地耦接至裝置晶粒330之互連件中的一者。在一實施例中，第二級焊料凸塊338可為通常用於裝置封裝中之任何焊料，諸如，基於鉛錫之焊料或無鉛焊料。
現參看圖3I，本發明之實施例包括沿單體化線370自載帶基板310單體化裝置封裝體中之每一者的單體化製程。藉助於實例，可用雷射單體化或鋸割製程來單體化裝置封裝體。
本發明之實施例亦可包括具有安裝於裝置晶粒上方的第二晶粒之裝置封裝體及製造此等裝置封裝體之方法。舉例而言，第二晶粒可為記憶體晶粒，該記憶體晶粒藉由形成於裝置晶粒之頂表面之上的局部記憶體互連件(local memory interconnect；LMI)襯墊及通過裝置晶粒形成的矽通孔(through silicon via；TSV)電氣地耦接至裝置晶粒的積體電路。在一實施例中，第二晶粒可大於裝置晶粒。 因此，第二晶粒之一部分可延伸超出裝置晶粒的外部邊緣。通常，在包括安裝於較小裝置晶粒之上的較大第二晶粒的封裝體中，模具層需要形成於裝置晶粒周圍以便支撐整個第二晶粒。在已將裝置晶粒安裝至基板之後通常用暴露晶粒模製製程來形成此等模具層。然而，暴露晶粒模製製程之使用導致可能降低產物產率之額外問題。
一個此類問題為暴露晶粒模製製程中使用之模具可在形成於第一裝置晶粒之表面之上的LMI襯墊上造成過多壓縮壓力，即使在保形層形成於模具的接觸裝置晶粒的表面之上時。舉例而言，模具可在LMI襯墊上施加介於大約10MPa與100MPa之間的壓力。此等高壓力可導致LMI襯墊機械斷裂。另外，來自模具之壓力亦可導致導電跡線及形成於導電跡線之上的保形介電材料斷裂。
另外，在保形層接觸LMI襯墊時，靜電放電(ESD)損害可能損壞裝置晶粒之電晶體。在一些封裝體中，LMI襯墊可藉由一或多個TSV直接電氣地耦接至第一裝置晶粒的積體電路。在此等實施例中，可能將積聚於保形層上之任何電荷直接放電至裝置晶粒中之電路並對裝置晶粒造成永久性損害。
此外，暴露晶粒模製製程可能並非為完美潔淨製程。舉例而言，可能在第一裝置晶粒之頂表面及LMI襯墊之部分之上留下某模製材料。在模製材料存在於LMI襯墊之上時，模製材料可能降低用以將第二晶粒連接至裝置晶粒之接合製程的有效性。舉例而言，在用TCB製程接合第 二晶粒時，LMI襯墊之上的模具殘餘物可能防礙第一裝置晶粒與第二晶粒之間的電接觸。
因此，本發明之實施例為有益的，此是由於在將裝置晶粒630安裝至基板之前形成用以支撐第二晶粒631的強化層620。因此，消除對暴露晶粒模製製程的需要，該暴露晶粒模製製程將以其他方式損害LMI襯墊，造成ESD損害或降低接合製程的有效性。圖6A至圖6B中說明根據本發明之實施例的用於形成此封裝體的製程。
現參看圖6A，提供實質上類似於圖3G中所說明之裝置封裝體的裝置封裝體。用以形成圖6A中所說明之裝置封裝體之處理實質上類似於用以形成圖3G中所說明之封裝體之處理，且因此，此處將不予以重複。然而，應注意，在將裝置晶粒630安裝至基板610之前形成強化層(例如，藉由將強化層模製至基板或藉由使用黏著劑以將離散強化層組件黏著至基板，如上文更詳細地描述)。
儘管用以形成圖6A中所說明之封裝體之處理實質上類似於用以形成圖3G中所展示之封裝體的處理，但在封裝體中存在此處應注意的若干差異。首先，裝置晶粒630可包括一或多個LMI襯墊655。在一實施例中，可用一或多個金層或其他薄膜電鍍材料(諸如，銅、金與銅之合金或類似者)來電鍍LMI襯墊。根據一實施例，LMI襯墊655可電氣地耦接至諸如銅跡線的一或多個導電跡線，該等一或多個導電跡線連接至形成於裝置晶粒630中之一或多個TSV中的一者。額外實施例可包括形成於跡線之數個部分之上的 介電層，諸如，阻焊層。在一實施例中，TSV及導電跡線將LMI襯墊655耦接至第一裝置晶粒630之積體電路。為簡單起見且以便不會不必要地混淆本發明之實施例，自圖式省略跡線、介電層、TSV及積體電路。
另外，圖6A中之基板610經說明為實質上類似於圖3A至圖3I中所說明之載帶基板310，然而，實施例並不限於載帶基板。舉例而言，基板610可為剛性基板，諸如，多層堆積結構。在一實施例中，基板610可具有核心，或基板610可為無核心基板。藉助於實例，基板可包括一或多個交替介電材料層及導電再分佈層。在一實施例中，可用消減製程、加成製程或半加成製程(semi-additive process；SAP)來形成基板610。
現參看圖6B，將第二晶粒631安裝至裝置晶粒630。在一實施例中，第二晶粒631藉由焊料凸塊656電且機械地耦接至LMI襯墊655。在額外實施例中，可用任何互連件(諸如，焊盤柵格陣列、C4凸塊等)進行電及機械耦接。根據一實施例，可質量回焊焊料凸塊656。額外實施例可包括替代接合製程，諸如，TCB製程。在一實施例中，第二晶粒631可為記憶體晶粒。藉助於實例，記憶體晶粒可為任何類型之記憶體晶粒，諸如，靜態隨機存取記憶體(SRAM)、動態隨機存取記憶體(DRAM)、非依電性記憶體(NVM)等。
在一實施例中，第二晶粒631可具有大於第一裝置晶粒630之寬度的寬度。在一實施例中，第二晶粒631之 寬度大於開口629的寬度。根據此等實施例，在將第二晶粒631安裝於第一裝置晶粒630之上時，第二晶粒631之數個部分可在強化層620之頂表面之上延伸。因此，第二晶粒631可沿其實質上全部寬度支撐。在一實施例中，亦可在第二晶粒631之安裝期間使用助焊劑材料637。藉助於實例，助焊劑材料637可為基於環氧樹脂之助焊劑。亦可沿第二晶粒631之整個寬度安置助焊劑材料637以便填充第二晶粒631與第二晶粒631下方之材料(諸如，裝置晶粒630、底部填充層636及/或強化層620)之間的空間。因此，本發明之實施例允許支撐整個寬度的第二晶粒631。
根據一實施例，圖6B中所說明之封裝體之處理可用實質上與上文關於圖3H至圖3I所說明且所描述之相同的處理操作繼續，且因此本文將不予以詳細重複。舉例而言，在一實施例中，第二級互連件可視情況形成於基板610之第二表面662之上。另外，實施例可包括沿單體化線單體化基板610以便形成個別封裝體。
因此，本發明之實施例能夠將第二晶粒631電且機械地耦接至裝置晶粒630而無需經歷上文所描述之不利問題。舉例而言，在形成用以支撐延伸寬度之第二晶粒631的強化層620期間並未將LMI襯墊655暴露於高壓力，此是由於在將裝置晶粒630安裝至基板之前於基板610上形成強化層620。另外，由於LMI襯墊655並未與模具接觸，因此在裝置晶粒630中將不出現ESD損害。此外，不存在將在LMI 655之上形成模製材料殘餘物之風險，且因此使接合製程更 容易且更可靠。
圖5說明根據一實施例之計算裝置500。計算裝置500收容機板502。機板502可包括多個組件，包括(但不限於)處理器504及至少一通訊晶片506。處理器504實體地且電氣地耦接至機板502。在一些實施中，至少一通訊晶片506亦實體地且電氣地耦接至機板502。在其他實施中，通訊晶片506可為處理器504之部分。
取決於應用，計算裝置500可包括可以或可不實體地且電氣地耦接至主機板502之其他組件。此等其他組件包括(但不限於)：依電性記憶體(例如，DRAM)、非依電性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位信號處理器、密碼處理器、晶片組、天線、顯示器、觸控式螢幕顯示器、觸控式螢幕控制器、電池、音訊寫碼解碼器、視訊寫碼解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速度計、陀螺儀、微機電系統(MEMS)、揚聲器、攝影機及大量儲存裝置(諸如，硬碟機、光盤(CD)、數位通用光碟(DVD)等)。
通訊晶片506實現無線通訊以用於傳送資料至計算裝置500以及自計算裝置500傳送資料。術語「無線」及其衍生詞可用以描述可經由非固體媒體經由使用經調變電磁輻射來傳達資料的電路、裝置、系統、方法、技術、通訊頻道等。該術語並不暗示相關聯裝置並不含有任何導線，但在一些實施例中該等裝置可能含有導線。通訊晶片506可實施多個無線標準或協定中之任一者，其包括(但不限於)Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、 IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其衍生物以及指定為3G、4G、5G及以上之任何其他無線協定。計算裝置500可包括多個通訊晶片506。舉例而言，第一通訊晶片506可專用於較短距離無線通訊，諸如，Wi-Fi及藍芽，且第二通訊晶片506可專用於較長距離無線通訊，諸如，GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他。
計算裝置500之處理器504包括封裝於處理器504內之積體電路晶粒。在一些實施例中，將處理器之積體電路晶粒封裝於根據本發明之一實施例的具有載帶基板及載帶基板之上的強化層且包圍裝置晶粒的裝置封裝體中。術語「處理器」可指處理來自暫存器及/或記憶體之電子資料以將彼電子資料變換為可存儲於暫存器及/或記憶體中之其他電子資料的任何裝置或裝置之部分。
通訊晶片506亦包括封裝於通訊晶片506內之積體電路晶粒。根據另一實施例，將通信晶片之積體電路晶粒封裝於根據本發明之實施例的具有載帶基板及載帶基板之上的強化層且包圍裝置晶粒的裝置封裝體中。
在其他實施中，收容於計算裝置500內之另一組件可含有積體電路晶粒，該積體電路晶粒包括一或多個裝置，諸如封裝於根據本發明之一實施例的具有載帶基板及載帶基板之上的強化層且包圍裝置晶粒的裝置封裝體中之裝置。
在各種實施中，計算裝置500可為膝上型電腦、上網本、筆記型電腦、超級本、智慧型電話、平板電腦、 個人數位助理(PDA)、超級行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描儀、監視器、機上盒、娛樂控制單元、數位攝影機、攜帶型音樂播放器或數位視訊錄製器。在其他實施中，計算裝置500可為處理資料之任何其他電子裝置。
本發明之一實施例可包括一種用於形成裝置封裝體之方法，其包含：在基板之上形成強化層，其中通過強化層形成一或多個開口；將裝置晶粒置放至開口中之一者中；藉由回焊定位於裝置晶粒與基板之間的一或多個焊料凸塊將裝置晶粒接合至基板。額外實施例可包括形成裝置封裝體，其中形成強化層包含：將模具置放於基板之表面之上，將模製材料射出至模具中，及自基板移除模具。額外實施例可包括形成裝置封裝體，其中模具包含一或多個凹部及順應性襯裡。額外實施例可包括形成裝置封裝體，其中用射出模製製程將模製材料射出至模具中。額外實施例可包括形成裝置封裝體，其中射出模製製程為真空輔助射出模製製程。額外實施例可包括形成裝置封裝體，其中模製材料為環氧樹脂。額外實施例可包括形成裝置封裝體，其中環氧樹脂包含強化微粒。額外實施例可包括形成裝置封裝體，其中形成強化層包含：將黏著層塗覆至強化層之表面，將強化層置放於基板之上，其中黏著層機械地將強化層耦接至基板。額外實施例可包括形成裝置封裝體，其中強化層為鋼、不鏽鋼或鋁。額外實施例可包括形成裝置封裝體，其中在將裝置晶粒置放至開口中之前於裝置晶粒上形成一或多個焊料凸塊。額外實施例可包括形成裝置封裝體，其中在獨立金屬支柱上形成一或多個焊料凸 塊中之每一者，該等金屬支柱電氣地耦接至裝置晶粒之積體電路。額外實施例可包括形成裝置封裝體，其中裝置晶粒之第一邊緣與開口之第一側壁之間的第一間隙大於裝置晶粒之第二邊緣與開口之第二側壁之間的第二間隙。額外實施例可包括形成裝置封裝體，其進一步包含：將第二晶粒電且機械地耦接至裝置晶粒之頂表面，其中第二晶粒之一寬度寬於開口之寬度，且其中第二晶粒之一部分由強化層支撐。額外實施例可包括形成裝置封裝體，其中第二晶粒為記憶體晶粒，該記憶體晶粒由以下各者電氣地耦接至裝置晶粒之積體電路：形成於裝置晶粒中之一或多個通孔，形成於裝置晶粒之表面之上的一或多個導電跡線，及形成於裝置晶粒之表面之上的一或多個局部記憶體互連件。額外實施例可包括形成裝置封裝體，其中基板之厚度小於大約100μm。
本發明之一實施例可包括裝置封裝體，該裝置封裝體包含：基板，其具有形成於基板之第一表面之上的一或多個導電跡線；一或多個導電通孔，其自基板之第一表面至基板的與基板之第一表面相對的第二表面形成，其中導電通孔中之一或多者電氣地耦接至導電跡線；強化層，其形成於基板之上，其中強化層具有暴露導電跡線之部分的一或多個開口；及裝置晶粒，其由一或多個焊料凸塊電氣地耦接至一或多個導電跡線。額外實施例可包括裝置封裝體，其中強化層為環氧樹脂材料。額外實施例可包括裝置封裝體，其中強化層藉由黏著層耦接至基板。額外實施例可包括裝置封裝體，其中強化層為鋼、不鏽鋼或鋁。額外實施例可包括裝置封裝體，其進一步包含：阻焊層，其 形成於基板之部分之上及導電跡線之部分之上；以及一或多個阻焊劑開口，其通過阻焊層的由強化層中之開口暴露之部分形成。額外實施例可包括裝置封裝體，其中裝置晶粒之第一邊緣與開口之第一側壁之間的第一間隙大於裝置晶粒之第二邊緣與開口之第二側壁之間的第二間隙。額外實施例可包括裝置封裝體，其進一步包含：第二晶粒，其電且機械地耦接至裝置晶粒之頂表面，其中第二晶粒之一寬度寬於開口之寬度，且其中第二晶粒之一部分由強化層支撐。
本發明之一實施例可包括裝置封裝體，該裝置封裝體包含：基板，其具有形成於基板之第一表面之上的一或多個導電跡線，其中基板之厚度小於100μm；一或多個導電通孔，其自基板之第一表面至基板的與基板之第一表面相對之第二表面形成，其中一或多個導電通孔中之每一者電氣地耦接至導電跡線；強化層，其形成於基板之上，其中強化層具有暴露導電跡線之部分的一或多個開口；裝置晶粒，其由一或多個焊料凸塊電氣地耦接至一或多個導電跡線；底部填充材料，其安置於裝置晶粒與基板之間且在一或多個焊料凸塊周圍；第二晶粒，其機械地且電氣地耦接至裝置晶粒之頂表面，其中第二晶粒之寬度寬於開口之寬度，且其中第二晶粒之一部分由強化層支撐；以及一或多個第二級互連件，其形成於基板之第二側上。額外實施例可包括裝置封裝體，其進一步包含：黏著層，其形成於強化層與基板之間，其中強化層為鋼、不鏽鋼或鋁。額外實施例可包括裝置封裝體，其中裝置晶粒之第一邊緣與開口之第一側壁之間的第一間隙大於裝置晶粒之第二邊緣 與開口之第二側壁之間的第二間隙。
200‧‧‧帶倒裝晶片球柵陣列封裝體/帶倒裝晶片球柵陣列裝置封裝體
210‧‧‧載帶基板
212‧‧‧阻焊層
220‧‧‧強化層
223‧‧‧邊緣
224‧‧‧導電跡線
225‧‧‧側壁
226‧‧‧導電通孔
228‧‧‧阻焊劑開口
229‧‧‧開口
230‧‧‧裝置晶粒
232‧‧‧支柱
234‧‧‧焊料凸塊
236‧‧‧底部填充材料
238‧‧‧第二級互連焊球
261‧‧‧第一側/第一表面
262‧‧‧第二側
G‧‧‧間隙
T、TR‧‧‧厚度
W‧‧‧寬度

Claims (25)

  1. 一種用於形成一裝置封裝體之方法，其包含：在一基板之上形成一強化層，其中一或多個開口通過該強化層被形成；將一裝置晶粒置放至該等開口中之一者中；藉由回焊定位於該裝置晶粒與該基板之間的一或多個焊料凸塊將該裝置晶粒接合至該基板。
  2. 如請求項1之方法，其中形成該強化層包含：將一模具置放於該基板之該表面之上；將一模製材料射出至該模具中；以及自該基板移除該模具。
  3. 如請求項2之方法，其中該模具包含一或多個凹部及一順應性襯裡。
  4. 如請求項2之方法，其中該模製材料以一射出模製製程被射出至該模具中。
  5. 如請求項4之方法，其中該射出模製製程為一真空輔助射出模製製程。
  6. 如請求項2之方法，其中該模製材料為一環氧樹脂。
  7. 如請求項6之方法，其中該環氧樹脂包含強化微粒。
  8. 如請求項1之方法，其中形成該強化層包含：將一黏著層塗覆至該強化層之一表面；將該強化層置放於該基板之上，其中該黏著層將該強化層機械地耦接至該基板。
  9. 如請求項8之方法，其中該強化層為鋼、不鏽鋼或鋁。
  10. 如請求項1之方法，其中該等一或多個焊料凸塊係在該裝置晶粒被置放至該開口中之前形成於該裝置晶粒上。
  11. 如請求項10之方法，其中該等一或多個焊料凸塊中之每一者係形成於電氣地耦接至該裝置晶粒之積體電路的獨立金屬支柱上。
  12. 如請求項1之方法，其中該裝置晶粒之一第一邊緣與該開口之一第一側壁之間的一第一間隙係大於該裝置晶粒之一第二邊緣與該開口之一第二側壁之間的一第二間隙。
  13. 如請求項1之方法，其進一步包含：將一第二晶粒電氣地且機械地耦接至該裝置晶粒之一頂表面，其中該第二晶粒之一寬度係寬於該開口之一寬度，且其中該第二晶粒之一部分係由該強化層所支撐。
  14. 如請求項13之方法，其中該第二晶粒為由以下各者電氣地耦接至該裝置晶粒之積體電路的一記憶體晶粒：形成於該裝置晶粒中之一或多個通孔，形成於該裝置晶粒之一表面之上的一或多個導電跡線，及形成於該裝置晶粒之一表面之上的一或多個局部記憶體互連件。
  15. 如請求項1之方法，其中該基板之一厚度係小於大約100μm。
  16. 一種裝置封裝體，其包含：一基板，其具有形成於該基板之一第一表面之上的 一或多個導電跡線；一或多個導電通孔，其自該基板之該第一表面至與該基板之該第一表面相對之該基板的一第二表面所形成，其中該等導電通孔中之一或多者係電氣地耦接至一導電跡線；一強化層，其形成於該基板之上，其中該強化層具有暴露該等導電跡線之數個部分的一或多個開口；以及一裝置晶粒，其由一或多個焊料凸塊電氣地耦接至該等一或多個導電跡線。
  17. 如請求項16之裝置封裝體，其中該強化層為一環氧樹脂材料。
  18. 如請求項16之裝置封裝體，其中該強化層係由一黏著層所耦接至該基板。
  19. 如請求項18之裝置封裝體，其中該強化層為鋼、不鏽鋼或鋁。
  20. 如請求項16之裝置封裝體，其進一步包含：一阻焊層，其形成於該基板之數個部分之上及該等導電跡線之數個部分之上；以及一或多個阻焊劑開口，其通過該阻焊層的由該強化層中之該開口所暴露之部分所形成。
  21. 如請求項16之裝置封裝體，其中該裝置晶粒之一第一邊緣與該開口之一第一側壁之間的一第一間隙係大於該裝置晶粒之一第二邊緣與該開口之一第二側壁之間的一第二間隙。
  22. 如請求項16之裝置封裝體，其進一步包含一第二晶粒，其機械地且電氣地耦接至該裝置晶粒之一頂表面，其中該第二晶粒之一寬度係寬於該開口之一寬度，且其中該第二晶粒之一部分係由該強化層所支撐。
  23. 一種裝置封裝體，其包含：一基板，其具有形成於該基板之一第一表面之上的一或多個導電跡線，其中該基板之一厚度係小於100μm；一或多個導電通孔，其自該基板之該第一表面至與該基板之該第一表面相對之該基板的一第二表面所形成，其中該等一或多個導電通孔中之每一者電氣地耦接至一導電跡線；一強化層，其形成於該基板之上，其中該強化層具有暴露該等導電跡線之多個部分的一或多個開口；一裝置晶粒，其由一或多個焊料凸塊電氣地耦接至該等一或多個導電跡線；一底部填充材料，其安置於該裝置晶粒與該基板之間且在該等一或多個焊料凸塊周圍；一第二晶粒，其機械地且電氣地耦接至該裝置晶粒之一頂表面，其中該第二晶粒之一寬度係寬於該開口之一寬度，且其中該第二晶粒之一部分係由該強化層所支撐；以及一或多個第二級互連件，其形成於該基板之該第二側上。
  24. 如請求項23之裝置封裝體，其進一步包含：一黏著層，其形成於該強化層與該基板之間，其中該強化層為鋼、不鏽鋼或鋁。
  25. 如請求項23之裝置封裝體，其中該裝置晶粒之一第一邊緣與該開口之一第一側壁之間的一第一間隙係大於該裝置晶粒之一第二邊緣與該開口之一第二側壁之間的一第二間隙。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110112115A (zh) * 2018-02-01 2019-08-09 台湾积体电路制造股份有限公司 集成电路封装件及其形成方法
TWI689023B (zh) * 2019-07-25 2020-03-21 力成科技股份有限公司 堆疊式半導體封裝結構
TWI804195B (zh) * 2022-02-17 2023-06-01 南茂科技股份有限公司 半導體封裝結構及其製造方法
TWI807943B (zh) * 2021-11-25 2023-07-01 美商萬國商業機器公司 半導體晶粒封裝及其製造方法

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9899238B2 (en) 2014-12-18 2018-02-20 Intel Corporation Low cost package warpage solution
US9691675B1 (en) * 2015-12-22 2017-06-27 Intel Corporation Method for forming an electrical device and electrical devices
US10177060B2 (en) 2016-10-21 2019-01-08 Powertech Technology Inc. Chip package structure and manufacturing method thereof
DE102017117802B4 (de) 2016-11-14 2024-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-Bauelement und Verfahren
US10141253B2 (en) * 2016-11-14 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10714448B2 (en) 2017-05-09 2020-07-14 Unimicron Technology Corp. Chip module with porous bonding layer and stacked structure with porous bonding layer
US10685922B2 (en) * 2017-05-09 2020-06-16 Unimicron Technology Corp. Package structure with structure reinforcing element and manufacturing method thereof
US10950535B2 (en) 2017-05-09 2021-03-16 Unimicron Technology Corp. Package structure and method of manufacturing the same
US10178755B2 (en) 2017-05-09 2019-01-08 Unimicron Technology Corp. Circuit board stacked structure and method for forming the same
TWI685284B (zh) * 2018-12-11 2020-02-11 欣興電子股份有限公司 封裝結構及其製造方法
US10446521B2 (en) * 2017-11-07 2019-10-15 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating an integrated fan-out package
US10797007B2 (en) * 2017-11-28 2020-10-06 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10943843B2 (en) * 2019-01-07 2021-03-09 Advanced Semiconductor Engineering, Inc. Semiconductor package structure
US11088086B2 (en) * 2019-04-26 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US11164804B2 (en) 2019-07-23 2021-11-02 International Business Machines Corporation Integrated circuit (IC) device package lid attach utilizing nano particle metallic paste
US11031353B2 (en) 2019-08-23 2021-06-08 Micron Technology, Inc. Warpage control in microelectronic packages, and related assemblies and methods
CN112670191A (zh) * 2019-10-16 2021-04-16 长鑫存储技术有限公司 半导体封装方法、半导体封装结构及封装体
US11183474B2 (en) * 2019-11-04 2021-11-23 Advanced Semiconductor Engineering, Inc. Electronic device package and method for manufacturing the same
US11482461B2 (en) 2019-12-31 2022-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method for making the same
US11552029B2 (en) * 2020-09-04 2023-01-10 Micron Technology, Inc. Semiconductor devices with reinforced substrates
US20220093559A1 (en) * 2020-09-22 2022-03-24 Western Digital Technologies, Inc. Reducing keep-out-zone area for a semiconductor device
US20220367413A1 (en) * 2021-05-13 2022-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Packages With Multiple Types of Underfill and Method Forming The Same
US11908764B2 (en) * 2021-08-31 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including a circuit substrate having a cavity and a floor plate embedded in a dielectric material and a semiconductor die disposed in the cavity
US20230411251A1 (en) * 2022-06-16 2023-12-21 Stmicroelectronics, Inc. Thin substrate package and lead frame

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3584948B2 (ja) 1995-04-14 2004-11-04 京セラケミカル株式会社 液状樹脂の封止成形方法
JP2924840B2 (ja) * 1997-02-13 1999-07-26 日本電気株式会社 Ｔａｐｅ−ＢＧＡタイプの半導体装置
US6112875A (en) * 1997-12-15 2000-09-05 Gibson; Edward F. Conveyor frame roller shaft alignment strip and conveyor repair method
US6188582B1 (en) * 1998-12-18 2001-02-13 Geoffrey Peter Flexible interconnection between integrated circuit chip and substrate or printed circuit board
JP2000243867A (ja) 1999-02-24 2000-09-08 Hitachi Ltd 半導体装置及びその製造方法並びに半導体装置の積層構造並びに半導体装置の実装構造
US6395124B1 (en) * 1999-07-30 2002-05-28 3M Innovative Properties Company Method of producing a laminated structure
US6277672B1 (en) * 1999-09-03 2001-08-21 Thin Film Module, Inc. BGA package for high density cavity-up wire bond device connections using a metal panel, thin film and build up multilayer technology
US6287890B1 (en) * 1999-10-18 2001-09-11 Thin Film Module, Inc. Low cost decal material used for packaging
US6507119B2 (en) * 2000-11-30 2003-01-14 Siliconware Precision Industries Co., Ltd. Direct-downset flip-chip package assembly and method of fabricating the same
US20030170450A1 (en) * 2002-03-05 2003-09-11 Stewart Steven L. Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive
JP2004158474A (ja) 2002-11-01 2004-06-03 Murata Mfg Co Ltd ベアチップ部品を使用した電子部品の製造方法
TWI241675B (en) * 2003-08-18 2005-10-11 Siliconware Precision Industries Co Ltd Chip carrier for semiconductor chip
TWI237364B (en) * 2004-12-14 2005-08-01 Advanced Semiconductor Eng Flip chip package with anti-floating mechanism
TWI251316B (en) 2004-12-22 2006-03-11 Ind Tech Res Inst Chip package structure
TWI267967B (en) * 2005-07-14 2006-12-01 Chipmos Technologies Inc Chip package without a core and stacked chip package structure using the same
TWI317995B (en) 2006-11-22 2009-12-01 Lu Wei Hua Anti-warpage structure of semiconductor device
TWI419242B (zh) * 2007-02-05 2013-12-11 Chipmos Technologies Inc 具有加強物的凸塊結構及其製造方法
JP5394625B2 (ja) 2007-10-05 2014-01-22 新光電気工業株式会社 配線基板及びその製造方法
US20110163348A1 (en) * 2008-03-25 2011-07-07 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base heat spreader and inverted cavity in bump
US8110446B2 (en) * 2008-03-25 2012-02-07 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with a post/base heat spreader and a conductive trace
US8354688B2 (en) * 2008-03-25 2013-01-15 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump
US8269336B2 (en) * 2008-03-25 2012-09-18 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and signal post
US8378372B2 (en) * 2008-03-25 2013-02-19 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and horizontal signal routing
DE102008019571A1 (de) * 2008-04-18 2009-10-22 Giesecke & Devrient Gmbh Chipkarte und Verfahren zu deren Herstellung
JP5245917B2 (ja) 2009-03-03 2013-07-24 凸版印刷株式会社 半導体装置
US8405211B2 (en) * 2009-05-08 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Bump pad structure
US20110096507A1 (en) * 2009-10-24 2011-04-28 Kester, Inc. Microelectronic thermal interface
US9059187B2 (en) * 2010-09-30 2015-06-16 Ibiden Co., Ltd. Electronic component having encapsulated wiring board and method for manufacturing the same
US8343808B2 (en) * 2010-11-22 2013-01-01 Bridge Semiconductor Corporation Method of making stackable semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
JP5855905B2 (ja) * 2010-12-16 2016-02-09 日本特殊陶業株式会社 多層配線基板及びその製造方法
US8536695B2 (en) * 2011-03-08 2013-09-17 Georgia Tech Research Corporation Chip-last embedded interconnect structures
KR102038407B1 (ko) * 2012-02-27 2019-10-30 삼성전자주식회사 배선 기판 및 이를 포함하는 반도체 모듈
EP2897166A4 (en) 2012-09-14 2016-06-29 Renesas Electronics Corp METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT
US20140091461A1 (en) * 2012-09-30 2014-04-03 Yuci Shen Die cap for use with flip chip package
US8643184B1 (en) * 2012-10-31 2014-02-04 Intel Corporation Crosstalk polarity reversal and cancellation through substrate material tuning
US8836098B1 (en) * 2013-05-15 2014-09-16 Freescale Semiconductor, Inc. Surface mount semiconductor device with solder ball reinforcement frame
US9305853B2 (en) * 2013-08-30 2016-04-05 Apple Inc. Ultra fine pitch PoP coreless package
US9604340B2 (en) * 2013-12-13 2017-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Carrier head having abrasive structure on retainer ring
US9356009B2 (en) * 2014-05-27 2016-05-31 Micron Technology, Inc. Interconnect structure with redundant electrical connectors and associated systems and methods
US9391029B2 (en) * 2014-06-12 2016-07-12 Kabushiki Kaisha Toshiba Electronic device
US9355983B1 (en) * 2014-06-27 2016-05-31 Stats Chippac Ltd. Integrated circuit packaging system with interposer structure and method of manufacture thereof
US9899238B2 (en) * 2014-12-18 2018-02-20 Intel Corporation Low cost package warpage solution
US20190206833A1 (en) * 2015-12-23 2019-07-04 Intel IP Corporation Eplb/ewlb based pop for hbm or customized package stack
WO2017139542A1 (en) * 2016-02-11 2017-08-17 Skyworks Solutions, Inc. Device packaging using a recyclable carrier substrate
US10679949B2 (en) * 2016-03-11 2020-06-09 Mediatek Inc. Semiconductor package assembly with redistribution layer (RDL) trace
US10770405B2 (en) * 2017-05-31 2020-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal interface material having different thicknesses in packages
WO2019139625A1 (en) * 2018-01-12 2019-07-18 Intel Corporation First layer interconnect first on carrier approach for emib patch
WO2021061246A1 (en) * 2019-09-25 2021-04-01 Intel Corporation Molded interconnects in bridges for integrated-circuit packages
JP2021093516A (ja) * 2019-12-11 2021-06-17 インテル・コーポレーション 集積回路パッケージのためのコンポジットブリッジダイツーダイ相互接続
DE102020119293A1 (de) * 2020-03-12 2021-09-16 Taiwan Semiconductor Manufacturing Co., Ltd. Die-stapelstruktur und verfahren zum bilden derselben
US11621245B2 (en) * 2020-06-03 2023-04-04 Micron Technology, Inc. Microelectronic device packages with EMI shielding, methods of fabricating and related electronic systems
US20220157732A1 (en) * 2020-11-13 2022-05-19 Mediatek Inc. Semiconductor package and method of forming the same
US20230116326A1 (en) * 2021-10-13 2023-04-13 Mediatek Inc. Semiconductor package with tsv die

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110112115A (zh) * 2018-02-01 2019-08-09 台湾积体电路制造股份有限公司 集成电路封装件及其形成方法
TWI689023B (zh) * 2019-07-25 2020-03-21 力成科技股份有限公司 堆疊式半導體封裝結構
TWI807943B (zh) * 2021-11-25 2023-07-01 美商萬國商業機器公司 半導體晶粒封裝及其製造方法
TWI804195B (zh) * 2022-02-17 2023-06-01 南茂科技股份有限公司 半導體封裝結構及其製造方法

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