JP5245917B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5245917B2 JP5245917B2 JP2009049128A JP2009049128A JP5245917B2 JP 5245917 B2 JP5245917 B2 JP 5245917B2 JP 2009049128 A JP2009049128 A JP 2009049128A JP 2009049128 A JP2009049128 A JP 2009049128A JP 5245917 B2 JP5245917 B2 JP 5245917B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- semiconductor chip
- stiffener
- semiconductor device
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Description
以上の工程で、本発明の半導体装置101を製造することができる。
本発明に係る半導体装置101の実施例1を図面に基づいて以下に説明する。まず図2(a)に示すような薄型の配線基板102を用意する。薄型の配線基板102は、Cuを主体とした導電パターンを有し、絶縁樹脂層にはポリイミドを用いている。次に図2(b)に示すように、エポキシ系樹脂のスティフナ接着剤107を用いて、配線基板102にスティフナ106を貼り付ける。
比較例1として、保護樹脂108を充填しない半導体装置を製造した。保護樹脂108を充填しない点以外は、同様の工程にて製造した後、半導体装置の配線基板102の外部接続用端子(パッド)と、第二の配線基板110の半導体装置搭載部とをはんだボール111で電気的に接続した。
<比較例2>
比較例2として、半導体チップ104とスティフナ106の間にエポキシ系樹脂を充填した半導体装置の配線基板102の外部接続用端子(パッド)と、第二の配線基板110の半導体装置搭載部とをはんだボール111で電気的に接続した。
実施例1の半導体装置101および比較例1及び2によって得られた半導体装置について、信頼性評価試験を行った。試験に用いた配線基板102の大きさは45mm角であり、スティフナ106の開口部分の大きさは30mm角である。また、使用した半導体チップ104の大きさは、20mm角である。
102・・・配線基板
103・・・アンダーフィル層
104・・・半導体チップ
105・・・バンプ
106・・・スティフナ
107・・・スティフナ接着剤
108・・・保護樹脂
109・・・リッド(蓋材)
110・・・第二の配線基板
111・・・はんだボール
Claims (4)
- 半導体チップの搭載された導電パターンを有する配線基板において、該配線基板上には前記半導体チップとスティフナと、前記半導体チップと前記スティフナの間の領域の前記配線基板上に保護樹脂を具備し、
前記半導体チップと前記配線基板の間にアンダーフィル層を具備し、
前記保護樹脂は、弾性率が0.5MPa以上10MPa以下の、シリコーン樹脂またはウレタン樹脂から選択された材料であり、
前記配線基板の厚さが0.05mm以上0.6mm以下であることを特徴とする半導体装置。 - 前記保護樹脂の厚さが60μm以上であることを特徴とする請求項1記載の半導体装置。
- 前記半導体チップと前記配線基板が、フリップチップ接続されていることを特徴とする請求項1または2に記載の半導体装置。
- 前記半導体チップと前記スティフナ上部まで前記保護樹脂が形成され、かつ、前記保護樹脂層上にリッドが形成されていることを特徴とする求項1から3の何れか一項記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009049128A JP5245917B2 (ja) | 2009-03-03 | 2009-03-03 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009049128A JP5245917B2 (ja) | 2009-03-03 | 2009-03-03 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010205887A JP2010205887A (ja) | 2010-09-16 |
JP5245917B2 true JP5245917B2 (ja) | 2013-07-24 |
Family
ID=42967110
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009049128A Expired - Fee Related JP5245917B2 (ja) | 2009-03-03 | 2009-03-03 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5245917B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9899238B2 (en) * | 2014-12-18 | 2018-02-20 | Intel Corporation | Low cost package warpage solution |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1032224A (ja) * | 1996-07-15 | 1998-02-03 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JPH11284124A (ja) * | 1998-03-27 | 1999-10-15 | Sumitomo Metal Mining Co Ltd | 半導体パッケージ用放熱板一体型補強板およびその製造方法 |
-
2009
- 2009-03-03 JP JP2009049128A patent/JP5245917B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2010205887A (ja) | 2010-09-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6401468B2 (ja) | パワーオーバーレイ構造およびその製造方法 | |
JP3973340B2 (ja) | 半導体装置、配線基板、及び、それらの製造方法 | |
TWI628750B (zh) | 功率覆蓋結構及其製造方法 | |
US7679176B2 (en) | Semiconductor device and electronic control unit using the same | |
JP3437369B2 (ja) | チップキャリアおよびこれを用いた半導体装置 | |
JP6302184B2 (ja) | 信頼性のある表面実装集積型パワーモジュール | |
US20090108429A1 (en) | Flip Chip Packages with Spacers Separating Heat Sinks and Substrates | |
WO1997020347A1 (en) | Semiconductor device, process for producing the same, and packaged substrate | |
KR20070038429A (ko) | 반도체 장치 | |
JP2009141041A (ja) | 電子部品実装用パッケージ | |
KR20070045894A (ko) | 적층형 반도체모듈 | |
JP2019075578A (ja) | 半導体パッケージ及びその製造方法 | |
JP2012518893A (ja) | 挿入層上に配置されたコンデンサーを有するicパッケージ | |
KR101697045B1 (ko) | 혼성 프레임 패널을 포함하는 상호접속 구조물 | |
US20080116588A1 (en) | Assembly and Method of Placing the Assembly on an External Board | |
JP3724954B2 (ja) | 電子装置および半導体パッケージ | |
JP2008159718A (ja) | マルチチップモジュールおよびその製造方法、並びにマルチチップモジュールの搭載構造およびその製造方法 | |
JP2004253738A (ja) | パッケージ基板及びフリップチップ型半導体装置 | |
JP5245917B2 (ja) | 半導体装置 | |
JP4449608B2 (ja) | 半導体装置 | |
US20090079062A1 (en) | Semiconductor package and electronic device | |
JP4577980B2 (ja) | 実装基板 | |
US20060278975A1 (en) | Ball grid array package with thermally-enhanced heat spreader | |
US20060118947A1 (en) | Thermal expansion compensating flip chip ball grid array package structure | |
JP2010219554A (ja) | 半導体装置及びそれを用いた電子制御装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120220 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20121127 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121225 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130218 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130312 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130325 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5245917 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160419 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |